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sec digital timer
NUCLEAR INSTRUMENTS AND METHODS 43 (1966) 365-367 ;
A. MODULAR It
NORTH-HOLLAND PUBLISHING CO.
Vii wc DIGITAL TIUNIER*
M. ECKHAUS' :, R . T. SIEGEL and R. E_ WELS1-i College caf IVilliarz and Mary, ! 'flliamsburg, Virginia, U.S.A. Received 16 January 1966 A digital time analyzer employing flexible plug-in logic and time base frequencies up to 100 Mc/sec is described . Tests and performance in moon and pion lifetime experiments indicate
linearity to better than 0. 1%. The aaaiyzer is comprised entirely of commercially available modular circuit elements.
. Introduction
2 .1 . PULSE SHAPING
A digital time analyzer has been corsiructed and
used at this laboratory primarily for the study of muon disappearance rates') and a determinat :on of the lifetime of the positive pion') . S;r .-iilar in operation fo the "digitron" reported by Lundy ; ` and , cawvc circuitry in use at other laboratories, this device employs commercially available un ti l. The control-logic circuitry is comprised of flexible plug-.n circuits). The basic timing frequency may be set by a front panel switch to 100 Mc/sec, 50 Melsec or 20 Mc/sec and can easily be extended to lower frequencies. 2. Basic tinning operation The basic principles of operation of the timer are shown in gig.;, l . A h stabic gate') is opened acrd ^lo<.ed . Thus a gated train of pulses by : rxrrtand stop pulses
f:%~-ninmng o cillator') i fcd to the discrims ~~~~Ct' Nilee rhc phase dlfâ renct-. b.-,~t1v'ccn theoscillator and the gate is random, the number of gated pulses passed to the -shaper has an inherent resolution of one pulse. The scaler') was one of two commercially available when this timer was constructed and was chosen because it contained "transfer-gates", i .e., transistors connected to each binary stage of the 100 Mc/sec scaler which will emit a. pulse upon interrogation with a command pulse if the corresponding binary stage is in the "1" state . 1roir.
Supported in ;dart by the National Aerc
Administration .
naLE60
SP:We
WId
The scaler contains a gate circuit and pulse shaper but not a voltage discriminator and thus gating and discrimination is performed externally. A "perfect" voltage discriminator is required to reshape the gated wave train in order that all pulses of the train be of the same height and shape at the scaler input. Without such reshaping, the gated wave trains would present a wide spectrum of pulse shapes to the scaler . Since most 100 Mc/sec sealers have "units" decades which are composed of a twisted ring of five binaries, these sealers possess ten different input voltage thresholds, depending on the last "units" digit being scaled . It follows that those digits which trigger at a lower voltage would be counted more Pfciently, i .e ., the time channels would exhibit non-random :ät~ctc.attons and thus rix~re-rhacîfleI Nvidths would be unequal. In the device reported. here, this is avoided by gating and shaping the «- .vc ti-,9in with t3 c~~m :ne=t. aj ! ) ü-`lsv,`sec AND gate s ), which provides the 1 .5 V output levels required to drive the scaler . Z .?.
SCALING AND STORAGE
The binary-coded-decimal (BCD) outputs from the scaler decades are connected through gating transistors to the address register of a 400 channel pulse height analyzer (PHA). A command pulse to the gating transistors causes the PHA address register to be set to the number in the scaler and then a count is added to the P1-IA mernory location corresponding to that
op r;~ k TIMING
osc .
100 me/sec
DISCRIMINATOR I
GATE
SHAPER
CLOSE
_I
Fig. 1 . Principles of operation of fated oscillator timer.
365
-1
I
SCALER j
M. ECKHAUSE et al.
M11V18RATOR OUTPUT PULSE WIDTH " (
LE- LEADING EDGE
FLIP-FLOP
TE- TRAILING EDGE
"AND"
INHIBIT ---~ INPUT
R= RESETTABLE UNIVISRATOR
Fig. 2. Condensed schematic diagram of control-logic circuitry employed in negative muon disappearance rate measurements. dress. Most commercial PHA's are available with such a "paralleJ access" modification prewired to the address mister, including a gating transistor on each binary line . 3. C
ßl-
, circuitry
A condensed schematic diagram of the logic-control circuitry- is shown in fig. 2. Various types of logic circuits ha`` e tx-en used in this timing device depending upon the experiment being performed . The logic circuit employs plug-in modules which may be interconnected with "hook-up" wire, thus allowing great flexibility i a the logic. The circuit depicted in fig. 2 is typical of those employed in negative muon capture experiments, The start pulse opens the timing gate, unless fp-flop 3 (FF3) is in the "1" state, which indicates that a timing or store operation is in progress . ivibrator 4 sends a delayed trigger to the "store" coincidence gate 7 and also "enables" univibrator 6. Univibrator 6 will then trigger if a second start pulse arrives at univibrator 1 durine the maximum range of the timing process, T. T is determined by a fixed capacitor and is slightly less than 4 psec when the Mc'sec timing frequency is used . Gate widths appropriate to the various timing frequencies may be set by front panel switches for logic elements 2, 4, 6, 8 and g. For the 50 Mc/see. and 20 Mc/sec timing frequencies, corresponding values of Tare < 8 psec and < 20 psec, respectively. Univibrator 2 is a "resettable" univibrator, i .e ., it returns from the "on" (1) to the "off" (0) state only
after an interval of time Tfrom its last input signal has elapsed. This ensures that univibrator 2 remains quiescent for a period T before transmitting a timing pulse to FF3. If, therefore, FF3 is reset immediately after the arrival of a muon, a period T will elapse before FF3 can receive its next timing start pulse. This eliminates possible distortions in the timing measurements caused by events in which two muons arrive within a time t < T of each other, with the first of the two arriving just before FF3 is reset and the second initiating a timing event in the normal manner . Since the timing gate would subsequently be closed by the earliest signature of decay, a bias toward erroneously short lifetimes could be introduced into the time spectrum') . Univibrator 8 is set for a time slightly greater than T, the timing range, so that no more than one stop pulse can be transmitted to the tinting gate in a time T. This ensures that background stops which are uncorrelated with the start pulse shall contribute only a linear backôt'ot1ndl of zero slope to the time spectrum ,r.,.... ..... . In . . the . .~ event . ... ...
that (a) a stop pulse has arrived within T after the start pulse, causing gate 7 to be enabled and (b) no second start pulse has caused univibrator 6 to disable gate 7, the timing event is stored and the circuit reset. if condition (a) and/or (b) is not fulfilled, the circuit is reset but storage in the PHA is inhibited . The storagereset sequence is arranged so that (1) the BCD output levels from the scaler reach operating values before transfer to the PHA address register is begun, (2) transfer to the PHA is completed prior to the start of
A MODULAR
100 Mc/sec DIGITAL TIMFR
36'
the scaler reset pulse ; and (3) the scaler reset circuit is allowed to become completely quiescent before FF3 i's-, reSCÉ to permit initiation a new tinlâng ed , ent . The times required for the above three events are (1) 5 psec ; (2) 9.5 .asec ; (3) 26 jusec (including 16 psec for scaler reset) and the sum of these plus the maximum timing range T constitutes the dead time of the instrument .
The oscillator employed in this device has exhibited an abSOlz!te accuracy of 1 part in 10' for each timing frequency and drjhts of less than 1 part in 10' per week .
4. Operation and testing This device has operated satisfactorily in laboratory tests, in muon disappearance rate measurements and in an experiment to measure the mean lifetime of the positive pion . Tests for noniinearity have been performed both by simulating starts with a random source and stops from a time-marker generator and also by initiating both starts and stops from separate uncorrelated random sources. Under either condition, with counts stored in excess of 106 per channel, no fluctuations outside of statistics were evident. The channel widths are therefore equal to an accuracy better than 1 part in 103. Rates for both starts and stops were as high as 2 x 10'/sec. No rate dependences were evident.
3) R. A. Lundy, Rev. Sci. Instr. 34 (1963) 146 . 4) Series 11 and 12 Modules, Lecroy Research Systems Inc .,
References
1) M. Eckhause, T. A. Filippas, R. T. Siegel and R. E. Welsh, to
be published in Nucl. Physics.
2) M. Eckhause, R. Harris, W. B. Shuler, R. T. Siegel and R. E.
Welsh, Physics Letters 19 (1965) 348. Irvington-on-Hudson, New York.
5) This gate consisted of a Chronetics Inc ., Model 102 Four-Fold
AND gate. One ofthe inputs ofthe AND gate was modified by the addition of two 15 MFD capacitors to the ac-coupled input stage thus preventing differentiation of the timing gate. The more recent Model 103 of this company has a dc-coupled veto input which could be employed in this timer without modification . 6) Lecroy Research Systems Inc. Model FF-11 . 7) Model 49-48-001, Radiation Instrument Development Laboratories . 8) The output stage of the Chronetics Model AND gate served as the discriminator-shaper . 4) For a detailed discussion of logical aspects of fast timing experiments see R. A . Lundy, Phys. Rev . 125 (1962) 1686.
A. MODULAR It
NORTH-HOLLAND PUBLISHING CO.
Vii wc DIGITAL TIUNIER*
M. ECKHAUS' :, R . T. SIEGEL and R. E_ WELS1-i College caf IVilliarz and Mary, ! 'flliamsburg, Virginia, U.S.A. Received 16 January 1966 A digital time analyzer employing flexible plug-in logic and time base frequencies up to 100 Mc/sec is described . Tests and performance in moon and pion lifetime experiments indicate
linearity to better than 0. 1%. The aaaiyzer is comprised entirely of commercially available modular circuit elements.
. Introduction
2 .1 . PULSE SHAPING
A digital time analyzer has been corsiructed and
used at this laboratory primarily for the study of muon disappearance rates') and a determinat :on of the lifetime of the positive pion') . S;r .-iilar in operation fo the "digitron" reported by Lundy ; ` and , cawvc circuitry in use at other laboratories, this device employs commercially available un ti l. The control-logic circuitry is comprised of flexible plug-.n circuits). The basic timing frequency may be set by a front panel switch to 100 Mc/sec, 50 Melsec or 20 Mc/sec and can easily be extended to lower frequencies. 2. Basic tinning operation The basic principles of operation of the timer are shown in gig.;, l . A h stabic gate') is opened acrd ^lo<.ed . Thus a gated train of pulses by : rxrrtand stop pulses
f:%~-ninmng o cillator') i fcd to the discrims ~~~~Ct' Nilee rhc phase dlfâ renct-. b.-,~t1v'ccn theoscillator and the gate is random, the number of gated pulses passed to the -shaper has an inherent resolution of one pulse. The scaler') was one of two commercially available when this timer was constructed and was chosen because it contained "transfer-gates", i .e., transistors connected to each binary stage of the 100 Mc/sec scaler which will emit a. pulse upon interrogation with a command pulse if the corresponding binary stage is in the "1" state . 1roir.
Supported in ;dart by the National Aerc
Administration .
naLE60
SP:We
WId
The scaler contains a gate circuit and pulse shaper but not a voltage discriminator and thus gating and discrimination is performed externally. A "perfect" voltage discriminator is required to reshape the gated wave train in order that all pulses of the train be of the same height and shape at the scaler input. Without such reshaping, the gated wave trains would present a wide spectrum of pulse shapes to the scaler . Since most 100 Mc/sec sealers have "units" decades which are composed of a twisted ring of five binaries, these sealers possess ten different input voltage thresholds, depending on the last "units" digit being scaled . It follows that those digits which trigger at a lower voltage would be counted more Pfciently, i .e ., the time channels would exhibit non-random :ät~ctc.attons and thus rix~re-rhacîfleI Nvidths would be unequal. In the device reported. here, this is avoided by gating and shaping the «- .vc ti-,9in with t3 c~~m :ne=t. aj ! ) ü-`lsv,`sec AND gate s ), which provides the 1 .5 V output levels required to drive the scaler . Z .?.
SCALING AND STORAGE
The binary-coded-decimal (BCD) outputs from the scaler decades are connected through gating transistors to the address register of a 400 channel pulse height analyzer (PHA). A command pulse to the gating transistors causes the PHA address register to be set to the number in the scaler and then a count is added to the P1-IA mernory location corresponding to that
op r;~ k TIMING
osc .
100 me/sec
DISCRIMINATOR I
GATE
SHAPER
CLOSE
_I
Fig. 1 . Principles of operation of fated oscillator timer.
365
-1
I
SCALER j
M. ECKHAUSE et al.
M11V18RATOR OUTPUT PULSE WIDTH " (
LE- LEADING EDGE
FLIP-FLOP
TE- TRAILING EDGE
"AND"
INHIBIT ---~ INPUT
R= RESETTABLE UNIVISRATOR
Fig. 2. Condensed schematic diagram of control-logic circuitry employed in negative muon disappearance rate measurements. dress. Most commercial PHA's are available with such a "paralleJ access" modification prewired to the address mister, including a gating transistor on each binary line . 3. C
ßl-
, circuitry
A condensed schematic diagram of the logic-control circuitry- is shown in fig. 2. Various types of logic circuits ha`` e tx-en used in this timing device depending upon the experiment being performed . The logic circuit employs plug-in modules which may be interconnected with "hook-up" wire, thus allowing great flexibility i a the logic. The circuit depicted in fig. 2 is typical of those employed in negative muon capture experiments, The start pulse opens the timing gate, unless fp-flop 3 (FF3) is in the "1" state, which indicates that a timing or store operation is in progress . ivibrator 4 sends a delayed trigger to the "store" coincidence gate 7 and also "enables" univibrator 6. Univibrator 6 will then trigger if a second start pulse arrives at univibrator 1 durine the maximum range of the timing process, T. T is determined by a fixed capacitor and is slightly less than 4 psec when the Mc'sec timing frequency is used . Gate widths appropriate to the various timing frequencies may be set by front panel switches for logic elements 2, 4, 6, 8 and g. For the 50 Mc/see. and 20 Mc/sec timing frequencies, corresponding values of Tare < 8 psec and < 20 psec, respectively. Univibrator 2 is a "resettable" univibrator, i .e ., it returns from the "on" (1) to the "off" (0) state only
after an interval of time Tfrom its last input signal has elapsed. This ensures that univibrator 2 remains quiescent for a period T before transmitting a timing pulse to FF3. If, therefore, FF3 is reset immediately after the arrival of a muon, a period T will elapse before FF3 can receive its next timing start pulse. This eliminates possible distortions in the timing measurements caused by events in which two muons arrive within a time t < T of each other, with the first of the two arriving just before FF3 is reset and the second initiating a timing event in the normal manner . Since the timing gate would subsequently be closed by the earliest signature of decay, a bias toward erroneously short lifetimes could be introduced into the time spectrum') . Univibrator 8 is set for a time slightly greater than T, the timing range, so that no more than one stop pulse can be transmitted to the tinting gate in a time T. This ensures that background stops which are uncorrelated with the start pulse shall contribute only a linear backôt'ot1ndl of zero slope to the time spectrum ,r.,.... ..... . In . . the . .~ event . ... ...
that (a) a stop pulse has arrived within T after the start pulse, causing gate 7 to be enabled and (b) no second start pulse has caused univibrator 6 to disable gate 7, the timing event is stored and the circuit reset. if condition (a) and/or (b) is not fulfilled, the circuit is reset but storage in the PHA is inhibited . The storagereset sequence is arranged so that (1) the BCD output levels from the scaler reach operating values before transfer to the PHA address register is begun, (2) transfer to the PHA is completed prior to the start of
A MODULAR
100 Mc/sec DIGITAL TIMFR
36'
the scaler reset pulse ; and (3) the scaler reset circuit is allowed to become completely quiescent before FF3 i's-, reSCÉ to permit initiation a new tinlâng ed , ent . The times required for the above three events are (1) 5 psec ; (2) 9.5 .asec ; (3) 26 jusec (including 16 psec for scaler reset) and the sum of these plus the maximum timing range T constitutes the dead time of the instrument .
The oscillator employed in this device has exhibited an abSOlz!te accuracy of 1 part in 10' for each timing frequency and drjhts of less than 1 part in 10' per week .
4. Operation and testing This device has operated satisfactorily in laboratory tests, in muon disappearance rate measurements and in an experiment to measure the mean lifetime of the positive pion . Tests for noniinearity have been performed both by simulating starts with a random source and stops from a time-marker generator and also by initiating both starts and stops from separate uncorrelated random sources. Under either condition, with counts stored in excess of 106 per channel, no fluctuations outside of statistics were evident. The channel widths are therefore equal to an accuracy better than 1 part in 103. Rates for both starts and stops were as high as 2 x 10'/sec. No rate dependences were evident.
3) R. A. Lundy, Rev. Sci. Instr. 34 (1963) 146 . 4) Series 11 and 12 Modules, Lecroy Research Systems Inc .,
References
1) M. Eckhause, T. A. Filippas, R. T. Siegel and R. E. Welsh, to
be published in Nucl. Physics.
2) M. Eckhause, R. Harris, W. B. Shuler, R. T. Siegel and R. E.
Welsh, Physics Letters 19 (1965) 348. Irvington-on-Hudson, New York.
5) This gate consisted of a Chronetics Inc ., Model 102 Four-Fold
AND gate. One ofthe inputs ofthe AND gate was modified by the addition of two 15 MFD capacitors to the ac-coupled input stage thus preventing differentiation of the timing gate. The more recent Model 103 of this company has a dc-coupled veto input which could be employed in this timer without modification . 6) Lecroy Research Systems Inc. Model FF-11 . 7) Model 49-48-001, Radiation Instrument Development Laboratories . 8) The output stage of the Chronetics Model AND gate served as the discriminator-shaper . 4) For a detailed discussion of logical aspects of fast timing experiments see R. A . Lundy, Phys. Rev . 125 (1962) 1686.