- Email: [email protected]
A new approach to the topological design of hybrid circuits
World Abstracts continued from page 39
A silicon and alumlnium dynamic memory technology R. A. LARSEN IBM J. Res. Devel. 24(3) 268 (1980). The Silicon and Aluminium Metal Oxide Semiconductor (SAMOS) technology is presented as a high-yield, low-cost process to make one-device-cell random access memories. The characteristics of the process are a multilayer dielectric gate insulator (oxide-nitride), a p-type polysilicon field shield, and a doped oxide diffusion source. Added yield-enhancing features are backside ion implant gettering, dual dielectric insulators between metal layers, and circuit redundancy. A family of chips is produced using SAMOS, ranging from 18K bits to 64K bits. System features such as on-chip data registers are designed on some chips. The chip technology is merged with 'flip-chip' packaging to provide one-inch-square modules from 72K bits through 512K bits, with typical access times from 90ns to 300ns.
Numerical analysis of the resistance of interference-fit pin connections E. GUANCIAL IEEE Trans. Components, tlybrids Affng Technol. Chmt-3(3), 402 0980). A three-dimensional analysis is presented for the resistance of an interference-fit pin connection in a plated-through hole. The analysis examines the electric potential distribution resulting from the application of a four-wire resistance measurement method. In light of the resultant potential distributions, the utility of the test method is discussed and found to give variable results with respect to resistance changes of the pin and plated-through hole contact. Actual resistance changes are generally underestimated by a factor of four or less. For large changes in resistance of the order of 300bt~, this method is acceptable since the underestimation factor is fairly constant and is approximately equal to unity.
64-K static RAM surrounds n-MOS cdis with C-MOS circuits T. O H Z O N E Electronics p. 145 (1980). N-doped wells replace p-type in C-MOS process to cut fabrication steps and optimise memory-cell transistors.
A new approach to the topological design of hybrid circuits W. ULBRICH and R. Van Der LEEDEN Electrocomp. Sci. Techt;ol. 7, 181 (1980). A computer-aided topological hybrid layout-design procedure is proposed, that yields the wanted principal routing in the form of a geometrical planarisation graph. A so-called grid-embedding of a circuit graph into the Euklidean plane enables us to observe all except one of the various technological constraints. The real problem is reduced to finding a proper arrangement of 'nets' and 'flocks' in the plane in order to meet the omitted cross-capacity constraint. The solution is accomplished by a constructive and implicit enumeration procedure, which is used within an interactive man-machine design process.
3. Microprocessors Peripheral controller chip ties into 8- and 16-bit systems J. BANNING and P. LIN Electronics p. 143 (1980). Based on one-chip-microcomputer architecture, universal peripheral controller comes with either multiplexed or non-multiplexed address and data lines, provides ROM-less and prototyping packages for product development.
4.
Hybrids
Design and production of hybrid circuit artwork A. D. MILNE Electrocomp. Sci. TechnoL 7, 23 (1980). The demand for greater complexity in hybrid circuits requires new techniques to be applied to the production of artwork. The paper discusses the use of a high precision pattern generator and the relevance of integrated circuit CAD software to the production of hybrid circuits.
Active filters and hybrid technology P. L. M O R A N Electrocomponent Sci. Technol. 6, 67 (1980). The conditions under which the choice of circuit used for the active filter is important are discussed with relationship to both the technology used and the application of the circuit. A number of common circuits are critically analysed and compared with respect to these criteria.
TiNx thin-film resistors for hybrid integrated circuits Z. KEMPISTY, L. KROL-STEPNIEWSKA andW. POSADOWSKI Electrocomponent Sci. Technol. 6, 231 (1980). TiNx thin-films have been evaluated for use as thin-film resistors. Thin-films were obtained by reactive triode sputtering of titanium in nitrogen atmosphere on crystallised glass substrates. In the resistive TiNx layers, the values ofx was 0.96. The value of the sheet resistance of the tested layers was 30 ohm/sq. Stability and TCR were measured during accelerated ageing.
A method for the computer-assisted design of the topology of thlck-film hybrid circuits W. B U R K H A R D T , D. HENNIG, H. H A G E R and U. SCHROTER Nachrichtentech. Elektron. 30(9), 359 (1980). (In German). The computer-assisted design of thick-film hybrid circuits uses as mathematical basis the graph theory. In the placement of the components the substrate is decomposed in rectangles. The plotting is made according to a line search method. 40
Design and development of a 68-lead nonhermetic leaded chip carrier A. J. MASESSA and R. G. MOHR IEEE Trans. Components, Hybrids Mfng TechnoL Chmt-3(3), 424 (1980). The design and development of a 68-lead nonhermetic leaded chip carrier (CC) suitable for packaging a high-speed bipolar gate array device with several watts of power dissipation are covered. This CC was designed to make use of thin-film hybrid assembly technology with a package outline generally consistent with the J E D E C Leaded Type A Standards. The CC is compatible with different silicon integrated circuit (SIC) attachment methods and provides high thermal performance. The CC was constructed using titanium/palladium/gold thinfilm circuitry on 99.5% alumina, with package leads attached to the thin-film circuit by thermal compression bonding. The assembly of the silicon device to the ceramic involved epoxy die bonding and thermosonic gold wire bonding. The majority of the work on the CC was performed with a thermal test chip. The assembled CC device was coated with RTV and an epoxy for environmental protection, and the external leads were formed around a plastic insert to meet the J E D E C outline. An aluminium heat spreader was attached to the back surface of the ceramic. A surface solder method for the attachment of the CC to a printed wiring board (PWB) was developed. The fatigue resistance of the solder joints was demonstrated to be adequate. Temperature rise versus power measurements were made on CCs with and without heat spreaders and on a CC/PWB assembly. From the data, the thermal resistances of the packages were determined and used in defining a simple model of the CC package and a CC/PWB package combination. Depending on the environment of the CC device, a forced air velocity range was determined to maintain chip junction temperatures below alloffed maximums. It was determined that the thermal performance of the CC packaged device would be satisfactory for use with a 2-W chip in a moderate forced air environment. A computer programme with temperature gradient capability for the network anal) sis of hybrid circuits C. R. ZII~dMER Electrocomponent Sci. TechnoL 6, 277 (1980). A modified version of the computer programme SINC-S is described which permits the user to specify independently up to 30 different device temperatures in a given problem when the proper control statement is included. An additional option is an algorithm for the steady-state solution of a non-linear network with periodic inputs, so that realistic system operation may be simulated. The programme may he used to provide more accurate simulation of circuits where large temperature gradients are present, and to furnish input data for other thermal analysis programmes.
A silicon and alumlnium dynamic memory technology R. A. LARSEN IBM J. Res. Devel. 24(3) 268 (1980). The Silicon and Aluminium Metal Oxide Semiconductor (SAMOS) technology is presented as a high-yield, low-cost process to make one-device-cell random access memories. The characteristics of the process are a multilayer dielectric gate insulator (oxide-nitride), a p-type polysilicon field shield, and a doped oxide diffusion source. Added yield-enhancing features are backside ion implant gettering, dual dielectric insulators between metal layers, and circuit redundancy. A family of chips is produced using SAMOS, ranging from 18K bits to 64K bits. System features such as on-chip data registers are designed on some chips. The chip technology is merged with 'flip-chip' packaging to provide one-inch-square modules from 72K bits through 512K bits, with typical access times from 90ns to 300ns.
Numerical analysis of the resistance of interference-fit pin connections E. GUANCIAL IEEE Trans. Components, tlybrids Affng Technol. Chmt-3(3), 402 0980). A three-dimensional analysis is presented for the resistance of an interference-fit pin connection in a plated-through hole. The analysis examines the electric potential distribution resulting from the application of a four-wire resistance measurement method. In light of the resultant potential distributions, the utility of the test method is discussed and found to give variable results with respect to resistance changes of the pin and plated-through hole contact. Actual resistance changes are generally underestimated by a factor of four or less. For large changes in resistance of the order of 300bt~, this method is acceptable since the underestimation factor is fairly constant and is approximately equal to unity.
64-K static RAM surrounds n-MOS cdis with C-MOS circuits T. O H Z O N E Electronics p. 145 (1980). N-doped wells replace p-type in C-MOS process to cut fabrication steps and optimise memory-cell transistors.
A new approach to the topological design of hybrid circuits W. ULBRICH and R. Van Der LEEDEN Electrocomp. Sci. Techt;ol. 7, 181 (1980). A computer-aided topological hybrid layout-design procedure is proposed, that yields the wanted principal routing in the form of a geometrical planarisation graph. A so-called grid-embedding of a circuit graph into the Euklidean plane enables us to observe all except one of the various technological constraints. The real problem is reduced to finding a proper arrangement of 'nets' and 'flocks' in the plane in order to meet the omitted cross-capacity constraint. The solution is accomplished by a constructive and implicit enumeration procedure, which is used within an interactive man-machine design process.
3. Microprocessors Peripheral controller chip ties into 8- and 16-bit systems J. BANNING and P. LIN Electronics p. 143 (1980). Based on one-chip-microcomputer architecture, universal peripheral controller comes with either multiplexed or non-multiplexed address and data lines, provides ROM-less and prototyping packages for product development.
4.
Hybrids
Design and production of hybrid circuit artwork A. D. MILNE Electrocomp. Sci. TechnoL 7, 23 (1980). The demand for greater complexity in hybrid circuits requires new techniques to be applied to the production of artwork. The paper discusses the use of a high precision pattern generator and the relevance of integrated circuit CAD software to the production of hybrid circuits.
Active filters and hybrid technology P. L. M O R A N Electrocomponent Sci. Technol. 6, 67 (1980). The conditions under which the choice of circuit used for the active filter is important are discussed with relationship to both the technology used and the application of the circuit. A number of common circuits are critically analysed and compared with respect to these criteria.
TiNx thin-film resistors for hybrid integrated circuits Z. KEMPISTY, L. KROL-STEPNIEWSKA andW. POSADOWSKI Electrocomponent Sci. Technol. 6, 231 (1980). TiNx thin-films have been evaluated for use as thin-film resistors. Thin-films were obtained by reactive triode sputtering of titanium in nitrogen atmosphere on crystallised glass substrates. In the resistive TiNx layers, the values ofx was 0.96. The value of the sheet resistance of the tested layers was 30 ohm/sq. Stability and TCR were measured during accelerated ageing.
A method for the computer-assisted design of the topology of thlck-film hybrid circuits W. B U R K H A R D T , D. HENNIG, H. H A G E R and U. SCHROTER Nachrichtentech. Elektron. 30(9), 359 (1980). (In German). The computer-assisted design of thick-film hybrid circuits uses as mathematical basis the graph theory. In the placement of the components the substrate is decomposed in rectangles. The plotting is made according to a line search method. 40
Design and development of a 68-lead nonhermetic leaded chip carrier A. J. MASESSA and R. G. MOHR IEEE Trans. Components, Hybrids Mfng TechnoL Chmt-3(3), 424 (1980). The design and development of a 68-lead nonhermetic leaded chip carrier (CC) suitable for packaging a high-speed bipolar gate array device with several watts of power dissipation are covered. This CC was designed to make use of thin-film hybrid assembly technology with a package outline generally consistent with the J E D E C Leaded Type A Standards. The CC is compatible with different silicon integrated circuit (SIC) attachment methods and provides high thermal performance. The CC was constructed using titanium/palladium/gold thinfilm circuitry on 99.5% alumina, with package leads attached to the thin-film circuit by thermal compression bonding. The assembly of the silicon device to the ceramic involved epoxy die bonding and thermosonic gold wire bonding. The majority of the work on the CC was performed with a thermal test chip. The assembled CC device was coated with RTV and an epoxy for environmental protection, and the external leads were formed around a plastic insert to meet the J E D E C outline. An aluminium heat spreader was attached to the back surface of the ceramic. A surface solder method for the attachment of the CC to a printed wiring board (PWB) was developed. The fatigue resistance of the solder joints was demonstrated to be adequate. Temperature rise versus power measurements were made on CCs with and without heat spreaders and on a CC/PWB assembly. From the data, the thermal resistances of the packages were determined and used in defining a simple model of the CC package and a CC/PWB package combination. Depending on the environment of the CC device, a forced air velocity range was determined to maintain chip junction temperatures below alloffed maximums. It was determined that the thermal performance of the CC packaged device would be satisfactory for use with a 2-W chip in a moderate forced air environment. A computer programme with temperature gradient capability for the network anal) sis of hybrid circuits C. R. ZII~dMER Electrocomponent Sci. TechnoL 6, 277 (1980). A modified version of the computer programme SINC-S is described which permits the user to specify independently up to 30 different device temperatures in a given problem when the proper control statement is included. An additional option is an algorithm for the steady-state solution of a non-linear network with periodic inputs, so that realistic system operation may be simulated. The programme may he used to provide more accurate simulation of circuits where large temperature gradients are present, and to furnish input data for other thermal analysis programmes.