A new compact model for external latchup

Microelectronics Reliability 49 (2009) 1447–1454

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A new compact model for external latchup Farzan Farbiz *, Elyse Rosenbaum Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1308 West Main St., Urbana, IL 61801, United States

a r t i c l e

i n f o

Article history: Received 9 May 2008 Available online 19 January 2009

a b s t r a c t A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS. Ó 2008 Elsevier Ltd. All rights reserved.

1. Introduction Latchup occurs when a parasitic PNPN device is triggered into its low impedance state [1]. External latchup describes the situation in which a disturbance at a signal pad causes substrate current injection and consequent triggering on of a PNPN that is connected to a supply line. For example, cable discharge events (CDE) can trigger latchup [2]. CDE occurs when charge is transferred into a circuit as a result of plugging in a cable, e.g. Ethernet cable. Cables can accumulate static charge when they are pulled through a conductor or dragged across a carpet [3,4]. In addition to CDE, other system-level ESD events can cause external latchup. The substrate current injector which produces external latchup may be an ESD protection device, such as a diode. Fig. 1 shows the cross-section of a substrate diode and a nearby parasitic PNPN device. If the diode momentarily becomes forward-biased by a transient voltage at the I/O, electrons will be injected into the substrate. If the injected carriers are collected at the N-well of the PNPN, latchup can occur. Substrate current injection from N+-diffusion/P-well junctions is studied in this work. Another type of current injector is a forward-biased N-well/P-substrate junction, such as that associated with an N-well diode. If an N-well diode is connected between the I/O pad and VSSO, its effect on latchup can be modeled using the same approach presented here for substrate diodes. This case is examined in detail in [5]. 2. Circuit modeling of external latchup Fig. 2 shows a circuit model corresponding to the cross-section of Fig. 1, for the case of a negative transient at the I/O pad; this is analogous to the negative I-test described in the latchup testing standard JESD78A [6]. In Fig. 2, QPNP1 and QNPN1 represent the cross-coupled bipolar transistors that form the PNPN, and QNPN2

represents the lateral NPN formed by the N+ cathode of the diode, the P-substrate, and the N-well. Most of the electrons injected into the substrate by the diode will recombine with holes, but some will be collected by the Nwell of the PNPN. The resulting N-well current will flow through RNW, which lies in parallel with the base–emitter junction of QPNP1. Therefore, the voltage drop across RNW forward-biases the base– emitter junction of QPNP1.Turning on QPNP1 is necessary but not sufficient to induce latchup. The collector current of QPNP1 must be large enough to forward-bias the base–emitter junction of QNPN1. Due to current flow through Rdiode, the substrate in the vicinity of the undershooting I/O is at a lower potential than VSS (see Fig. 1); the resulting majority-carrier substrate current through RPW1 and RSUB tends to reverse-bias the base–emitter junction of QNPN1. IC,PNP1 must be large enough to counteract the substrate current flowing from PW1 to the diode, in order for latchup to occur. Latchup is triggered if the current collected by the N-well is large enough to result in forward-biasing of both bipolar transistors. The necessary current is denoted as Icrit coll , and is given by

Icrit coll ¼

crit V BE;on P IC;PNP1 þ ; RNW bPNP1

Icrit C;PNP1 is found by solving the nodal equation at the base of QNPN1: I

trig ðRdiode þ Rsub ÞIcrit C;PNP1  Rdiode bNPN2

Rdiode þ Rsub þ RPW 1

0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.12.003



V BE;on N ¼ 0: RPW 1

ð2Þ

VBE,on_P and VBE,on_N represent the base–emitter voltage drops of QPNP1 and QNPN1, respectively, at the PNPN triggering point. bNPN2 and bPNP1 represent the common-emitter current gains of QNPN2 and QPNP1, respectively. Itrig is the external latchup trigger current, that is, it is the minimum value of Iinj that triggers latchup. The current collected by the N-well, Icoll, may be related to the substrate current injected by the diode, as follows:

Icoll ¼ aNPN2  Iinj : * Corresponding author. E-mail address: [email protected] (F. Farbiz).

ð1Þ

ð3Þ

aNPN2 is the common-base current gain of QNPN2. From (3), one finds

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F. Farbiz, E. Rosenbaum / Microelectronics Reliability 49 (2009) 1447–1454

IN I/O VSSO

VDD VDD

N+ P+ GR PW2

a VSS VSS

OUT

N+ P+ P+

N+ N+ P+

NW

PW1

Detector

Injector Cathode Anode

Linj_det

P+ N+ P+

GR

NW P+ N+ PW LN/P LTAP LTAP N+ P+ N+ P+ NW1

PW2

P-Substrate

PW1

P-Substrate

Fig. 1. Cross-section of a substrate diode next to a CMOS inverter.

b

Injector

Detector

Cathode Anode

Linj_det

P+ N+ P+

DT

PW2

NW P+ N+ PW LN/P LTAP LTAP DT N+ P+ N+ P+ PW1 NW1

P-Substrate

c

Detector

Injector Cathode Anode

Linj_det

P+ N+ P+ PW2

DT

NW P+ N+ PW L LTAP N/P LTAP DT N+ P+ N+ P+ PW1 NW1 NBL

P-Substrate Fig. 2. Injector–detector circuit schematic including the parasitic components for the case of a negative transient at the I/O.

Itrig ¼

Icrit coll

aNPN2

ð4Þ

:

Eqs. (1), (2), and (4) may be solved for the external latchup trigger current:

Itrig ¼

Rdiode þRsub þRPW1 RPW1

þRsub þ Rdiode bPNP1 V BE;ON P RNW Rdiode bPNP1 bNPN2 Rsub Þ bNPN2 þ1  bNPN2 þ1

V BE;ON

ðRdiode þ

N

ð5Þ

:

If RSUB >> RPW1 and RSUB >> Rdiode, then (5) reduces to

Itrig ¼

V BE;ON RPW1

N

þ bPNP1 bPNP1 bNPN

2

bNPN2 þ1

V BE;ON RNW

P

¼

1

aNPN2



V BE;ON N V BE;ON þ bPNP1 RPW1 RNW

P

 :

ð6Þ

On the far right-hand side of Eq. (6), the expression inside the parentheses is equal to Icrit coll and it is a function of only the PNPN layout. The PNPN layout spacings are known to have a significant impact on the trigger current for internal latchup [1]; internal latchup refers to latchup that is triggered by overshoot on VDD. For example, the internal latchup trigger current is an increasing function of LN/P (defined in Fig. 3); similarly, one may predict that Icrit coll will also be an increasing function of LN/P due to the bPNP term that appears in its denominator. Specifically, bPNP1, the current gain of

Fig. 3. Test structures used in this work. Each contains a substrate diode (injector) and a PNPN device (detector). LTAP and LN/P were not varied in the experiments. (a) CMOS technology. GR represents an N-well guard ring. (b) SmartMOS technology. DT denotes deep trench isolation. (c) SmartMOS technology with an N-type buried layer (NBL).

QPNP1, is a decreasing function of LN/P. The other layout-dependent parameters in the expression for Icrit coll are RPW1 and RNW; small well resistances will increase the trigger current for both internal and external latchup. We conclude that Icrit coll is correlated with the internal latchup trigger current. In contrast, aNPN2 of Eq. (6) is relevant only to external latchup. In the following sections of this paper, a model is presented for aNPN2. The symbol will be shortened to a, and this quantity will henceforth be referred to as the collection efficiency. 3. Experimental setup Test structures were fabricated in two different technologies: 0.18-lm RF-CMOS and 0.25-lm SmartMOS [7]. A substrate diode was used as the substrate current injector. Figs. 3 and 4 show the test structures. In RF-CMOS, the injector is a 15 lm wide, singlestripe diode, and the detector contains a 15 lm wide N-well. In SmartMOS, the injector has 25 N+-stripes, each 25 lm wide (25  25 lm), and the detector is 60 lm wide.

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a

r2 np ¼

Detector

Injector

L2n



ð7Þ

In (7), Ln is the electron diffusion length in the substrate. Given the electron distribution, one may calculate the current crossing the boundary of the detector by solving

W det

NW

W inj

np

J n ¼ qDn rnp 

ð8Þ

A closed-form, analytic solution to (7) does not exist for the geometry of Fig. 4 [8]. A closed-form solution may be obtained only by simplifying the problem geometry. If the injector width, Winj, is much less than the injector to detector spacing, Linj_det, then the injector may be modeled as a point source, and (7) should be solved using spherical coordinates. Conversely, if Winj >> Linj_det, then the injector may be modeled as an infinite line source, and a cylindrical coordinate system is used. Neither inequality is valid for all values of Winj and Linj_det used in this work; nevertheless, good results are obtained using the line source model. For an infinitely long, line source of minority carriers, centered at the origin of the coordinate system, (7) may be rewritten as

L inj_det

GR L det

b Injector

Winj

r2

@ 2 np @np np ðrÞ þr ¼ r2 2 ; @r 2 @r Ln

r > 0:

A Neumann boundary condition is taken at the silicon surface, i.e., the normal component of the current is zero. Below the silicon surface, for a finite-sized detector, the boundary condition for (9) will be spatially non-uniform. Further simplification of the problem geometry is needed in order to obtain a closed-form solution.

Linj_det

GR

4.1.1. Case I: No detector First, Eq. (9) is solved for the case that there is no detector. In this case, one boundary condition is

Wdet

lim np ðrÞ ¼ 0:

c

ð9Þ

ð10Þ

r!1

Injector

The solution to (9) is thus

Linj_det

Wdet

Winj

np ðrÞ ¼ C 1 K 0

GR

  r ; Ln

ð11Þ

where K0(x) is the modified Bessel function of the second type and order zero. Define Iinj as the current injected into the substrate per unit length. C1 in (11) is found by substituting (11) into (8) and setting

J n ð0Þ ¼ c lim r!0

1

pr

Iinj :

ð12Þ

One thus obtains

C1 ¼

cIinj ; pqDn

ð13Þ

Fig. 4. Top view of a test structure with a single finger injector, (a) 0° oriented, (b) 90° oriented and (c) 180° oriented detector.

where c is the electron injection efficiency, defined as the ratio of the injected electron current to the total injected current.

Referring to Fig. 3, a was measured with the anode grounded, a negative current source of magnitude Iinj connected to the cathode, the NW terminal connected to VDD, and all other terminals floating. Note that when the N-well guard ring is left floating, it does not impede the flow of minority carriers (electrons) in the substrate. VDD is set to 2 V, unless otherwise noted.

c¼

4. Carrier collection efficiency model 4.1. Collection efficiency vs. injector to detector spacing The electron distribution in the substrate is found by solving the diffusion equation,

Iinjn Iinjn ¼ : Iinj Iinjn þ Iinjp

ð14Þ

From (8), (11), and (13), one obtains

 

jJn ðrÞj ¼

cIinj r ; K pLn 1 Ln

ð15Þ

where K1(x) is the modified Bessel function of the second type and order one. 4.1.2. Case II: Radially uniform detector Next, Eq. (9) is solved for the case that one boundary condition is np(r = Linj_det) = 0. Indeed, np = 0 is the boundary condition at the edge of the depletion region outside the real detector, provided the

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carrier velocity inside the N-well is not saturated. The solution to (9) is

    r r np ðrÞ ¼ C 1 K 0 þ C 2 I0 ; Ln Ln

r > 0;

cIinj : pqDn

ð17Þ

C2 is found by satisfying the boundary condition np(r = Linj_det) = 0:



L

C 2 ¼ C 1



K 0 injLndet  : L I0 injLndet

Collection efficiency (%)

ð16Þ

where I0(x) and K0(x) and are the modified Bessel functions of the first and the second type, respectively, and order zero. Using (12) as the boundary condition at r = 0, one obtains

C1 ¼

W det =W0 6.5

ð18Þ

  1   K Linj det   0 c Ln r r A @  I1 ; jJ n ðrÞj ¼  K1 þ  Ln Ln pLn I0 Linj det

4.1.3. General solution The device simulation results of Fig. 5 indicate that the diffusion current in the substrate follows two main trajectories. Group I flow lines leave the injector as if there were no detector. Some of these lines bend in the vicinity of the detector but, to first order, the carrier density is given by (11). Group I carriers are primarily collected by the bottom plate of the reverse-biased N-well/P-substrate junction. Group II flow lines leave the injector as if there were a radially uniform detector. The carrier density is given by (16). Group II carriers are primarily collected by the N-well detector sidewall that lies closest to the injector. For group I, the collected current may be written using (15),

 

ð20Þ

For group II, the collected current may be written using (19),

0

IcollII

 



Linj

det



5

40

60

80

100

Temperature (° C)

ð19Þ

where I1(x) is the modified Bessel function of the first type and order one.

c r Iinj K ¼ aI Iinj : pLn 1 Ln W inj

5.5

4 20

0

Ln

IcollI ¼ GdetI

6

4.5

Current density is found using (8), (16), (17), and (18);

Iinj

W det =4W 0

Fig. 6. Collection efficiency, a  100%, vs. temperature for two different detector widths, Wdet. RFCMOS technology. W0 = 15 lm. Room temperature.

Above, Winj is the injector width. GdetI and GdetII are geometric factors that model the effective collection areas; these are functions of detector width and length, Wdet and Ldet. Note that Wdet is set equal to the width of the N-well, rather than the width of the N+ diffusion inside the well, because measurement data show that a is a far stronger function of the former dimension [9]. The effective collection area is not linearly proportional to Wdet or Ldet. In Fig. 6, it is shown that a 4 increase in Wdet produces only a 1.2 increase in collection efficiency [9]. In Fig. 7, it is shown that doubling Ldet by a factor of 2 does not increase a by a factor of two; this result was expected since the minority carrier density decreases as the distance to the injector increases, so one does not expect a uniform current density across the bottom plate of the N-well. The collection efficiency, and thus Gdet, is also a function of N+ diffusion orientation within the N-well detector. Fig. 8 shows that the collection efficiency is higher for a 90°-oriented detector than

1  

K 0 Ln c @ r r A Iinj  I1 ¼ GdetII  K1 ¼ aII Iinj þ  Linj det Ln L pLn W inj n I0 Ln

18.5 Measurement Model

ð21Þ

Collection efficiency (%)

18

17.5

17

16.5 15 Fig. 5. Current density in a test structure was simulated using DESSIS. The injector diode is forward-biased and the detector N-well is reverse-biased.

20

25

30 35 40 N-well length (º µm)

45

50

55

Fig. 7. Collection efficiency, a  100%, vs. Ldet. SmartMOS technology. Room temperature.

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F. Farbiz, E. Rosenbaum / Microelectronics Reliability 49 (2009) 1447–1454

7

6

90 ° oriented detector 0 ° oriented detector

6.5

5 Collection efficiency (%)

Collection efficiency (%)

T=25 °C T=75 °C T=100 °C

5.5

6 5.5 5

4.5 4 3.5 3 2.5

4.5 4 20

2

40

60 Temperature

80

100

1.5 10

20

30

40

(ºC)

50 60 Linj_det (µm)

70

80

90

Fig. 8. Collection efficiency vs. temperature for a 0° oriented detector and a 90° oriented detector. RF-CMOS technology. Room temperature.

Fig. 10. Collection efficiency, a  100%, vs. Linj_det and temperature. RF-CMOS technology. Model parameter Ln = 55 lm.

for a 0°-oriented detector [9]. This explains why others have observed that the trigger current is lower for a 90°-oriented detector [10]. Fig. 9 shows that the collection efficiency of a 180°-oriented detector is smaller than that of a 0°-oriented detector. This result is expected given the larger distance the electrons must travel in the substrate to get to the N-well for a 180°-oriented detector. However, data presented in [10,11] indicate that a 180°-oriented detector is more susceptible to latchup than is a 0°-oriented detector. This seeming discrepancy arises because the effective value of RNW is different in the two cases. Recall that Icrit coll is a decreasing function of RNW. Carriers are primarily collected at the edge of the detector that is closest to the injector, then the carriers travel through the N-well to the contact (labeled NW in Fig. 3). For the case of a 180°-oriented detector, the carriers must travel a longer distance through the N-well, leading to a higher effective well resistance. Scaling Wdet will affect the physical areas of the N-well sidewall and bottom-plate identically. Therefore, the width dependencies of

GI and GII are assumed to be the same. GI may be expressed as in (22), below.

GI ðW det ; Ldet ; orientationÞ  GII ðW det ; orientationÞGI ðLdet Þ:

Assuming that some fraction q of the minority carriers in the substrate fall into group I and the rest into group II, the total collected current may be written as

Icoll ¼ qIcolI þ ð1  qÞIcolII ¼ ðqaI þ ð1  qÞaII ÞIinj :

21

19 Collection efficiency (%)

Collection efficiency (%)

12

T=25 °C T=75 °C T=100 °C

20

0° oriented detector 180 ° oriented detector

14

ð23Þ

In Figs. 10 and 11, measurement results for both technologies are compared with the model, Eq. (23). As expected for a physicsbased model, the extracted values of Ln are the same order of magnitude, 55 lm and 25 lm for RF-CMOS and SmartMOS technologies, respectively. Furthermore, the fit of the model to data is good. The model for collection efficiency was developed assuming a single-stripe injector; either of two approaches may be used to

18

16

ð22Þ

18 17 16 15 14 13

10

12 8

0

5

10 Linj_det (µm)

15

Fig. 9. N-well collection efficiency, a  100%, vs. Linj_det for detectors with two different orientations. SmartMOS technology. Room temperature.

0

5

10 Linj_det ( µm)

15

Fig. 11. Collection efficiency, a  100%, vs. Linj_det and temperature. SmartMOS technology. Markers are measurement data and solid lines are the model. Model parameter Ln = 25 lm. For these multi-finger injectors, Linj_det is measured from the injector finger closest to the detector.

F. Farbiz, E. Rosenbaum / Microelectronics Reliability 49 (2009) 1447–1454

apply it to a multi-stripe injector. One approach is to represent the multi-stripe device as a single-finger injector that’s located at the center of the array. Alternatively, each finger may be considered to be a separate injector and the solution is found using superposition, i.e., the sum of solutions for each single-finger injector. Both approaches provide a good fit to the measurement data, but only the results from the superposition approach are shown in this work. 4.2. Temperature dependence From Figs. 10 and 11, one may conclude that the collection efficiency is an increasing function of temperature. The latchup trigger current is also an increasing function of temperature [1]. As a result of these two temperature dependencies, external latchup is more strongly temperature accelerated than is standard, internal latchup [9]. The two key temperature-dependent parameters in the model for a are diffusion length Ln and electron injection efficiency c. It has been shown that, over the range 25–100 °C, Ln is an increasing function of temperature [12]. c is analogous to the emitter injection efficiency of an NPN bipolar transistor, which is an increasing function of temperature [13]. Therefore, both Ln and c contribute to the positive temperature dependence of a. From electrical measurements of the test structures employed in this work, it is not possible to separately extract the temperature dependence of Ln and that of c. Therefore, for simplicity, all of the temperature dependencies are modeled inside c. It is found that a linear model well represents c(T). This linear model was employed in Figs. 10 and 11. 4.3. Collection efficiency vs. VDD The collection efficiency is an increasing function of VDD, as shown in Fig. 12. Empirically, this can be well modeled using an Early voltage construct, indicated as

  V aðV det Þ ¼ að0Þ 1  det : jV A j

tion of Linj_det. The data in Figs. 13 and 14 show that the extracted early voltage is fairly insensitive to Linj_det. Furthermore, the extracted values of VA are much smaller than would be expected for the true early effect. It is further noted that VA is insensitive to temperature and detector geometry. 4.4. Collection efficiency for detectors with N-type buried layers Many CMOS and BiCMOS technologies provide an N-type buried layer for making bipolar transistors or for isolating P-wells from the substrate. Fig. 3c shows the cross-section of a detector that has an N-type buried layer (NBL) beneath its P-well. Collection efficiencies of detectors with and without NBLs are compared in Fig. 15. The data show that the addition of an NBL increases the collection efficiency. It was previously established that collection efficiency is an increasing function of the detector area; see Fig. 7. Comparison of Fig. 3b and c reveals that the addition of an NBL increases the effective N-well area of the detector. Furthermore, the addition of this NBL lowers the internal latchup trigger current [14]

8 T=25 °C T=75 °C T=100 °C

7.5 7 Early voltage (V)

1452

6.5 6 5.5 5

ð24Þ

4.5

Physically, however, the voltage dependence is not due to the early effect. If the VDD dependence were a result of the early effect, then the extracted early voltage, VA, would be an increasing func-

4 10

20

30

40

50 60 Linj_det ( µm)

70

80

90

Fig. 13. VA is extracted from the data in Fig. 12, and data measured at other temperatures. RFCMOS technology.

4.5 Linj_det = 13 µm Linj_det = 30 µm

40

Linj_det = 50 µm

35

3.5 30 Early voltage (V)

Collection efficiency (%)

4

3 2.5

25 20 15 10

2 5

1.5

0

0

0.5

1

1.5

2

Detector voltage (V) Fig. 12. Collection efficiency, a  100%, vs. Linj_det and VDD. RF-CMOS technology. Room temperature.

0

5

10 Linj_det ( µm)

15

Fig. 14. Extracted values of VA vs. Linj_det. SmartMOS technology. Room temperature.

F. Farbiz, E. Rosenbaum / Microelectronics Reliability 49 (2009) 1447–1454

trons are collected at the bottom of both NW1 and PW1. As a result the presence of an NBL in the detector will cause Ln to be more heavily weighted toward Ln_sub; this will tend to raise Ln because Ln_sub > Ln_PW.

35 With NBL Without NBL 30 Collection efficiency (%)

1453

4.5. Parameter extraction procedure

25

The model parameters are Ln, GII, GI , c, q, and VA. Below is a list of test structures needed to extract the model parameters. Note that the model parameters will be technology-dependent.

20

15

10

0

5

10 Linj_det ( µm)

15

20

Fig. 15. Collection efficiency, a*100%, vs. Linj_det for a detector that has NBL and a detector that does not have NBL. SmartMOS technology. Room temperature.

and presumably Icrit,coll. Therefore, detectors with NBL’s are expected to be more susceptible to external latchup. This conjecture is consistent with the measurement data in [15]. The model for collection efficiency that was presented in Section 4.1 applies equally well when the detector contains an NBL. The results are shown in Fig. 16. The extracted Ln is slightly higher than what was used in Fig. 11 for the same technology. This result may be explained by considering the non-uniform doping along the path that electrons travel between the injector and the detector. Ln in the substrate (Ln_sub) is smaller than Ln in PW2 (Ln_PW) because of the lighter substrate doping density. In the analysis of Section 4.1, a uniform background doping density was implicitly assumed. More precisely, Ln in (20) and (22) should be thought of as the weighted combination of Ln_sub and Ln_PW. For example, if the distance that the electrons travel in the substrate is much longer than the distance the electrons travel in the P-well, then Ln is almost equal to Ln_sub. Adding an NBL to the detector increases the average distance carriers travel in the substrate because elec-

32 Measurement Model

30

1. To extract Ln and q: Test structures with variable Linj_det, but fixed injector and detector geometries. 2. To extract GII: Test structures with variable Wdet and orientation. All other geometric features are fixed. 3. To extract GI : Test structures with variable Ldet. All other geometric features are fixed.

c and VA are extracted by measuring collection efficiency at different temperatures and values of VDD, respectively. 5. Conclusions A parasitic PNPN device will be triggered on, resulting in latchup, if current larger than a critical value is injected into the substrate. The key factors determining whether external latchup occurs are (i) the critical current that is needed to trigger on the PNPN, (ii) the amount of current injected into the substrate (Iinj), and (iii) the amount of current collected by the N-well (Icoll). Iinj and Icoll are linked by a parameter called the collection efficiency. A model for the critical current can be developed along the lines of existing models for the (internal) latchup trigger current [1]. A physics-based, semi-empirical model for the collection efficiency was presented in this work. Model parameters are extracted from measurements performed on a limited number of test structures. Subsequently, latchup hazards can be identified in any layout. As part of the model development procedure, it was observed that external latchup is more strongly temperature accelerated than is internal latchup. It was also observed that collection efficiency does not increase linearly with the PNPN dimensions. We found that adding an N-type buried layer (NBL) to a PNPN increases the collection efficiency. This observation, taken together with the fact that adding an NBL lowers the PNPN’s trigger current, causes the PNPN with NBL to be significantly more susceptible to external latchup.

Collection efficiency (%)

Acknowledgements

28

SmartMOS test structures were donated by Freescale. C. Gill of Freescale is thanked for facilitating the donation. Many useful discussions on the subject of external latchup were held with R. Gauthier and K. Chatty of IBM.

26 24

References

22 20

0

5

10 Linj_det ( µm)

15

20

Fig. 16. Collection efficiency, a  100%, vs. Linj_det. Detector has an NBL underneath its P-well. SmartMOS technology. Markers are measurement data and solid lines are the model. Model parameter Ln = 29 lm.

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