A new fast-converged estimation approach for Dynamic Voltage Restorer (DVR) to compensate voltage sags in waveform distortion conditions

Electrical Power and Energy Systems 54 (2014) 598–609

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Electrical Power and Energy Systems journal homepage: www.elsevier.com/locate/ijepes

A new fast-converged estimation approach for Dynamic Voltage Restorer (DVR) to compensate voltage sags in waveform distortion conditions Hamed Abdollahzadeh a, Mostafa Jazaeri b,⇑, Arash Tavighi c a

Department of Electrical Engineering, East Tehran Branch, Islamic Azad University, Tehran, Iran Electrical and Computer Engineering Faculty, Semnan University, PO Box 35131-19111, Semnan, Iran c Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran b

a r t i c l e

i n f o

Article history: Received 1 June 2012 Received in revised form 14 August 2013 Accepted 21 August 2013

Keywords: Voltage sag DVR Estimation approach Symmetrical components Harmonic Control scheme

a b s t r a c t The on-line estimation of symmetrical components from network voltages and currents is widely used in the field of power quality monitoring and improvement of relevant disturbances, especially by CUstom Power Systems (CUPS). This paper proposes a new fast-converged estimation approach, which directly extracts amplitudes and phase angles of symmetrical components of desired frequencies from harmonic-distorted network voltages. The adequate convergence time and accuracy of this approach make it applicable in Dynamic Voltage Restorer (DVR) as an application in which the quickness of response is of the most important requirements. According to this objective, sensitivity analyses are prepared to assess the impacts of sag depth variations, phase angle jumps and frequency variations on the performance of the proposed algorithm. Further, in these analyses complete comparisons are made between the proposed approach and well-known algorithms such as KF, ADALINE and FFT using MATLAB/SIMULINK. The application of the proposed estimation approach in the DVR is realized by introducing a new control scheme. The proposed control scheme provides the compensation of different voltage sags through both pre-sag and in-phase strategies. Finally, simulation results, carried out in PSCAD/EMTDC environment, confirm the effectiveness of the suggested control scheme. Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction Research in the field of power quality improvement indicates that Dynamic Voltage Restorer (DVR), which is classified into CUstom Power Systems (CUPS), is the most economically and technically effective alternative to protect sensitive loads against a highly irritating and probable power quality disturbance known as voltage sag [1–3]. Voltage sags are sudden reductions in rms voltage between 0.1 and 0.9 per unit with duration from half a cycle to 1 min [4]. The impacts of voltage sags on industrial equipments is an important issue in the field of power quality and required to be thoroughly detected and suppressed [5]. A dynamic voltage restorer is the power electronic-based equipment that is connected in series with the feeder of sensitive loads between the supply and load buses [6], as shown in Fig. 1. DVRs usually consist of three single-phase Voltage Source Inverters (VSI), an energy storing unit, passive harmonic filters, injection transformers and a control scheme [7,8] which itself comprises three parts: an estimation unit, a compensation strategy and a switching pattern. An appropriate design of the control scheme ⇑ Corresponding author. E-mail addresses: [email protected] (H. Abdollahzadeh), mjazaeri@ semana.ac.ir (M. Jazaeri), [email protected] (A. Tavighi). 0142-0615/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.ijepes.2013.08.012

enables the DVR to inject three-phase controllable voltages of required amplitudes and phase angles to maintain the load bus voltage in desired waveform during voltage sags [9,10]. In some schemes, the DVR is equipped with energy storage to supply real power to the system in order to compensate the voltage imbalance [11,12]. A closed loop control system design to maintain the load voltage within permissible limits in a DVR using transformer coupled H-bridge converter is proposed by [13]. In the paper, voltage sags for the laboratory system is generated with SmartSource 345ASX, which is programmable to achieve this objective. Mitigation of voltage sags by means of DVRs mainly depends on protected load characteristics. There are three conventional voltage sag compensating strategies, each having distinctive advantages. They are known as in-phase, pre-sag and optimized energy [14]. Fig. 2 shows the vector diagram of the in-phase and pre-sag strategies. In the in-phase compensating strategy, the DVR compensates only the voltage amplitude, i.e., regardless of the phase angle jump d (see Fig. 2), both the injected voltage (Vinj) and compensated load voltage (Vl) are in-phase with the sag voltage. This method is mostly recommended for linear loads, which do not need to be compensated for the phase angle. While, the pre-sag compensating strategy is recommended for non-linear loads such as thyristor controlled drives, which require the phase angle restoration as well

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Load Bus

Vinja Injection Transformer

Supply Bus Passive LS Filter

CS S1

S4

S3

S2

Sensitive Load Energy Storage

Control Module

Fig. 1. Single line diagram of a typical DVR.

Pre-Sag Strategy '

Vl g -sa

Vin′ j

V pre

Vl

δ Vsag

δ

In-Phase Strategy

Vinj

I pre-sag

Isag

Fig. 2. Vector diagram of the in-phase and pre-sage compensating strategies.

as the compensation. In this strategy, the injected volt amplitude  age V 0inj is the difference between the pre-sag and sag voltages [14,15]. In some control schemes have already been presented for the DVR, the injection voltage for the pre-sag compensating strategy is obtained by comparing the amplitude of the positive sequence component with its reference value and using the frozen angle that is tracked via a Phase-Locked Loop (PLL) [16]. It is necessary to notice that this injection voltage is not the difference between the pre-sag and sag voltages, and hence cannot correctly restore the load voltage to pre-sag waveform. Being quick in the response is accounted as the most important characteristic of a DVR for the voltage sag compensation [17,18]. In this regard, if the compensator is unable to restore the voltage for sensitive equipment within permissible duration, which is usually specified by ITIC (Information Technology Industry Council) and CBEMA (Computer Business Equipment Manufacturers Association) curves, as a consequence the equipment would fail [19]. The response time and compensation accuracy of a DVR are directly affected by the convergence time and accuracy of the estimation algorithm employed in the control scheme. An overview of previous investigations reveals that the application of Synchronous Reference Frame (SRF) algorithm is very widespread in DVR in order to detect voltage sags and to access the dq components of the voltage or those of positive and negative sequence voltages [20–23]. In spite of its accurate and swift performance in the case of balanced clean (sinusoidal) waveforms there would however be two major deficiencies distinguishable in the SRF. On the one hand, the SRF is a single-frequency algorithm. Namely, it extracts the

synchronous components (Vd and Vq) of the harmonic order for which it is defined. In fact, there is not the possibility of developing this algorithm to detect different frequency components, simultaneously. Consequently, in the presence of harmonic distortions in voltage waveforms, for which most of sensitive loads are responsible, the extracted components would be distorted, too. On the other hand, in case of unbalanced sags, the SRF tracks undesirable oscillatory components superimposed on dc value of the dq components due to the presence of negative/zero sequence voltages. Under these conditions, the compensating strategies in which the conventional proportional–integral (PI) controller is employed would be unable to track and generate reference compensating signals properly [24]. Applying some low-pass filters to remove the undesirable components from the SRF outputs, might be a remedy for the unbalanced/distorted waveform conditions, but it would introduce a considerable delay, occasionally acceptable, in attaining the final value of the SRF outputs, and hence in the compensation process. There are also renowned algorithms, which can be utilized for on-line tracking of symmetrical components. These are Kalman Filter (KF), ADaptive LINEar combiner (ADALINE) and Fast Fourier Transform (FFT). The KF approach is based on a set of recursive mathematical equations, which provides an efficient computational means to estimate symmetrical components in a way that minimizes the mean value of squared error. The performance of the KF is adjusted by choosing the parameters noise covariance matrix ‘‘Q’’ and measurement noise covariance matrix ‘‘R’’ [25]. The ADALINE is realized using a linear adaptive neural network, which has a set of adjustable parameters called weight vector ‘‘w’’ and learning factor ‘‘a’’. The weight vector of the ADALINE generates the Fourier coefficients of a signal using a non-linear weight adjustment algorithm based on a stable difference error equation [26]. Although the foregoing algorithms are known as the powerful tools in some applications such as harmonic tracking in Active Power Filters (APF) [27,28] they would reflect serious drawbacks when employed in the DVR’s estimation unit, as will be completely investigated in next sections. As mentioned above, waveform distortions and unbalanced voltage sags are the situations in which the SRF algorithm is unable to satisfy properly the requirements of the DVR; in addition, the algorithms such as KF, ADALINE and FFT are not the appropriate alternatives to the SRF algorithm. Thus, this paper aims to propose a new fast-converged approach for the on-line estimation of symmetrical components in harmonic distortion conditions. It is based on the minimization of total squared errors over an estimation window when a transition takes place in samples of network voltages due to a disturbance. The proposed estimation approach

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directly, with no filtering required, gives the amplitudes and phase angles of the positive, negative and zero sequences for specified harmonic frequencies with adequate accuracy and quickness and hence in consistence with the DVR’s requirements. Furthermore, it has the ability of being changed or extended to desired harmonic orders. To approve the application of the proposed approach in the DVR’s control scheme, sensitivity analyses are conducted in detail. The sensitivity analyses not only completely survey the impacts of sag depth, phase angle jump and frequency variations on the performance of the proposed approach, but also prepare comprehensive comparisons between the proposed, KF, ADALINE and FFT algorithms. Based on the proposed estimation approach, a new control scheme is introduced for the DVR, which covers both the pre-sag and in-phase compensation strategies. Finally, by implementing the proposed control scheme in a typical DVR and simulating this combination in a test distribution network using PSCAD/EMTDC, the efficiency of the suggested control scheme will be investigated in case of different voltage sags. 2. Proposed estimation approach This section aims to propose an effective estimation approach for on-line tracking of symmetrical components of network voltages. For this purpose, the distorted network voltages (va, vb and vc) in discrete-time format (sampled voltages) are formulated in terms of symmetrical components as: M h  i X v a ðjÞ ¼ Im eiðxk tj Þ jv 0k jeið/0k Þ þ jv pk jeið/pk Þ þ jv nk jeið/nk Þ

ð1Þ

k¼1

v b ðjÞ ¼

M h  i X Im eiðxk tj Þ jv 0k jeið/0k Þ þ jv pk jeið/pk 2pk=3Þ þ jv nk jeið/nk þ2pk=3Þ k¼1

ð2Þ

where

v a ¼ ½ v a ð1Þ v a ð2Þ



v a ðNÞ T

ð5Þ

v b ¼ ½ v b ð1Þ v b ð2Þ



v b ðNÞ T

ð6Þ

v c ¼ ½ v c ð1Þ v c ð2Þ



v c ðNÞ T

ð7Þ

2

a1   ak   aM a1   ak   aM a1   ak   aM

3

6 7 A ¼ 4 a1   ak   aM a01   a0k   a0M a001   a00k   a00M 5 a1   ak   aM a001   a00k   a00M a01   a0k   a0M 3N6M ð8Þ " ak ¼

w1 sin



w1 cos

   wj cos

wj sin



wN sin

   wN cos

#T ð9Þ 2N

wj sin ¼ sinðxk tj Þ ¼ sinðxk  jDtÞ

ð10Þ

wj cos ¼ cosðxk t j Þ ¼ cosðxk  jDtÞ

ð11Þ

" a0k

¼ "

a00k

¼

w1 sin



wj sin

w1 cos

   wj cos

wþ1 sin



wþ1 cos

   wþj cos

wþj sin



wN sin

   wN cos 

wþN sin

   wþN cos

#T ð12Þ 2N

#T ð13Þ 2N

wj sin ¼ sinðxk tj  2pk=3Þ

ð14Þ

wj cos ¼ cosðxk t j  2pk=3Þ

ð15Þ

 T x0 ¼ jv 01 j  cosð/01 Þ jv 01 j  sinð/01 Þ  jv 0M j  cosð/0M Þ jv 0M j  sinð/0M Þ 12M ð16Þ

M h  i X v c ðjÞ ¼ Im eiðxk tj Þ jv 0k jeið/0k Þ þ jv pk jeið/pk þ2pk=3Þ þ jv nk jeið/nk 2pk=3Þ k¼1

 T xp ¼ jv p1 j  cosð/p1 Þ jv p1 j  sinð/p1 Þ   jv pM j  cosð/pM Þ jv pM j  sinð/pM Þ 12M ð17Þ

ð3Þ where  j and k denote the sample number and harmonic order, respectively. Where M is the highest harmonic order considered in the voltage waveforms.  jv 0k j; jv pk j and jv nk j are the amplitudes of the zero, positive and negative sequence components of the kth harmonic, respectively.  /0k ; /pk and /nk are the phase angles of the zero, positive and negative sequence components of the kth harmonic, respectively.  xk ¼ 2pkf0 is the angular frequency of the kth harmonic, where f0 is the fundamental frequency.  tj ¼ jDt ¼ jf0 =fs is the jth time sample, where Dt and fs are the sampling period and sampling frequency, respectively. The network voltages assumed in Eqs. (1)–(3) are individually written for the N sequential samples (i.e., for j = 1, 2, . . . , N, respectively). Then, they are expanded using the trigonometric equality sin(a + b) = sin(a)  cos(b) + sin(b)  cos(a). The expanded equations are arranged in the matrix form as:

2

3 2 3 va x0 6 7 6 7 4 v b 5 ¼ A3N6M  4 xp 5 ¼ A  X vc xn

 T xn ¼ jv n1 j  cosð/n1 Þ jv n1 j  sinð/n1 Þ  jv nM j  cosð/nM Þ jv nM j  sinð/nM Þ 12M ð18Þ

If a disturbance such as a voltage sag causes network voltage waveforms to change from what assumed in Eqs. (1)–(3), the difference between the samples of the measured network voltages and the samples represented in the vector form in Eq. (4), is defined as the error matrix as follows:

2

3 2 3 2 3 ea v ma va 6 7 6 7 6 7 4 eb 5 ¼ 4 v mb 5  4 v b 5 ec v mc vc

where vma, vmb and vmc are the vectors which contain the samples of the measured network voltage in the phases a, b and c, respectively. Indeed, these vectors, which are obtained by regular sampling of the network voltages with a frequency of fs, totally form an estimation window with the size of 3N samples (N samples per phase) for the proposed approach at any time sample, as shown in Fig. 3. For simplification, Eq. (19) is re-written as:

Eabc ¼ V mabc  V abc ð4Þ

ð19Þ

ð20Þ

Substituting Eq. (4) into (20) gives:

Eabc ¼ V mabc  ðA  XÞ

ð21Þ

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1

Voltage

(a)

j=1

0.75

j=i

(b)

j=2

Amplitude (pu)

0.5

j=N-1

...

(c)

0.25 0 -0.25 -0.5

Time

-0.75

...

-1 0.05

j=N

0.075

0.1

0.125

0.15

Time (s)

Current Sample

(a)

Last Samples Fig. 3. 3N-sample estimation window.

0.8pu

(c) The summation of squared errors for the window size of 3N samples is calculated as:

Es ¼ e2abc ð1Þ þ e2abc ð2Þ þ    þ e2abc ð3NÞ ¼

3N X

e2abc ðkÞ

ð22Þ

(a)

0.2pu

30ο

0.5pu

k¼1

Appling some matrix properties, Eq. (22) can be expressed in terms of Eq. (21) as follows:

Es ¼ ðV mabc  ðA  XÞÞT  ðV mabc  ðA  XÞÞ

ð23Þ

If the matrix X is evaluated through Eq. (23) in such a way that the summation of the squared errors becomes minimized, an optimal estimation of the symmetrical components will be achieved. For this purpose, the derivative of the ES is calculated with respect to X and then equalized to zero.

dEs =dX ¼ AT  ðV mabc  ðA  XÞÞ  ððV mabc  ðA  XÞÞT  AÞ ¼ 2ðAT  V mabc  AT  A  XÞ ¼ 0

T

ð24Þ

Consequently, Eq. (23) is solved to find the matrix X. 1

X ¼ ððAT  AÞ

 AT Þ  V mabc ¼ C  V mabc

ð25Þ

The matrix X, which is resulted from the equation above, is a vector with a dimension of 6M whose elements are the estimated Fourier coefficients of the zero, positive and negative sequences, respectively. They have been arranged in € x from the fundamental component to the highest harmonic order (k = M). To obtain the amplitude and phase angle of each sequence, the estimated values is to be converted into the polar coordinates. The convergence time of the proposed estimation approach is dependent on the parameters: sampling frequency and estimation window size, which is determined as follows:

Conv ergency time ðt c Þ ¼ Estimation window size=ð3  Sampling frequencyÞ

ð26Þ

According to the Nyquist criterion, the sampling frequency should be chosen at least twice the highest harmonic order in the estimated waveform [29]. However, there is not an analytical method to determine the estimation window size for the algorithm. The harmonic orders which are defined in the coefficient matrix A in Eq. (8) are considered to be dominant harmonics of network voltage waveforms. The dominant harmonics are those harmonics that are stronger in amplitude. They can be identified in a primary signal processing stage using Fourier analysis.

(b)

1pu

(b) Fig. 4. (a) A typical unbalanced voltage sag waveform. (b) Vector diagram of the fundamental component.

With regard to the estimation window size and sampling frequency, the proposed algorithm behavior was studied under different scenarios and the following results were observed; For a certain size of the estimation window, although an increase in the sampling frequency (a decrease in the sampling period) accelerates the convergence; however, this will make the algorithm more sensitive to undefined harmonics and hence may lead to an oscillatory estimation or even to the algorithm divergence. While, for a certain sampling frequency, an increase in the estimation window size causes the convergence to take longer; however, this will enhance the sensitivity which was stated. For a given waveform, however, based on the trial and error it is possible to achieve an appropriate estimation by making a compromise between the sampling frequency and estimation window size. It might seem that the proposed estimation algorithm is hard to be implemented in real-time applications owing to the significant calculation burden. However, it should be noticed that as long as the algorithm is tolerant of network frequency variations, the coefficient matrix A in Eq. (8) would be a constant matrix whose entries are time-invariant. As a consequence, the matrix C in Eq. (25) would also be a constant one, which is calculated off-line. Thus, finding the inverse of a large-dimensional matrix at each sampling time is replaced by a matrix multiplication. In the situation where the algorithm is intolerant of the frequency variations, application of the on-line network frequency to the estimation unit through some methods such as a frequency estimator is required in order to avoid the algorithm misoperation. In this case, however, the computation effort would be considerably reduced by expressing the matrix C parametrically. The sensitivity of the proposed algorithm to frequency variations is dealt with in Section 3. The three-phase waveform shown in Fig. 4a is considered as a typical unbalanced voltage sag for the primary assessment of the

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0.2

1.1

0.175

1 (IV)

0.9

Amplitude (pu)

Amplitude (pu)

(III)

(II)

0.15 0.125

(I). Reference (II). Proposed (III). KF (IV). ADALINE (V). FFT

(V)

(I)

(IV)

0.1 0.075

0.025 0 0.095

0.1

0.105

0.11

0.115

0.12

(V) (I)

0.7 0.6

(I). Reference (II). Proposed (III). KF (IV). ADALINE (V). FFT

0.05

(II)

0.8

(III)

0.5 0.4 0.095

0.125

0.1

0.105

Fig. 5. Estimated amplitude of the zero sequence component.

According to the defined harmonics, the Total Harmonic Distortion (THD) of the waveform is around 8% at each phase before the sag event. During the sag (i.e., after t = 0.1 s) the THD of each phase decreases in proportion to the corresponding sag depth at the fundamental component. The amplitudes and phase angles of the fundamental component are specified in Fig. 4b as the vector diagrams. Note that after this, the term ‘‘symmetrical components’’ refers to the symmetrical components of the fundamental frequency voltage. The proposed approach, KF and ADALINE are extended for the harmonic orders of the under-studied voltage sag waveform. Then, they are taken into comparison in estimating the amplitudes of the symmetrical components. The comparison results are shown in Figs. 5–7 for the zero, positive and negative sequence components, respectively. Note that the proposed approach and the other algorithms have been implemented in MATLAB/SIMULINK software. The parameters related to the algorithms are chosen as follows:  Proposed approach: fs = 10 kHz and N = 25 samples.  KF algorithm: fs = 10 kHz, Q = 0.005 I and R = I, where I is the 30 by 30 identity matrix.  ADALINE algorithm: fs = 10 kHz and a = 0.1. Figs. 5–7 obviously demonstrate that the proposed estimation approach gives an accurate estimation of the symmetrical components within 3 ms. Whereas, the KF and ADALINE algorithms start tracking the reference values with the time delay of about 10 ms. The FFT algorithm accurately estimates the symmetrical components in 20 ms. According to the estimation window size of 75 samples and sampling frequency of 10 kHz chosen for the proposed approach, it is expected from Eq. (26) that the convergence time is 2.5 ms (tc = 75 samples 3  10 kHz) = 2.5 ms) rather than 3 ms. The difference between the convergence times has originated from applying some post-processing stage at the final part of the estimation

0.125

0.175 (II)

0.15

HD5 ¼ 4:3% and /5 ¼ 5p=6 HD9 ¼ 2:8% and /9 ¼ 9p=6

0.12

0.2

Amplitude (pu)

HD7 ¼ 3:2% and /7 ¼ 7p=6;

0.115

Fig. 6. Estimated amplitude of the positive sequence component.

proposed estimation algorithm. This waveform contains, besides the fundamental component, the odd harmonic of 3rd to 9th with the Harmonic Distortions (HD) and the phase angles which are defined as follows:

HD3 ¼ 5:3% and /3 ¼ 3p=6;

0.11

Time (s)

Time (s)

0.125

(III) (IV)

(V)

(I)

0.1 0.075 0.05

(I). Reference (II). Proposed (III). KF (IV). ADALINE (V). FFT

0.025 0 0.095

0.1

0.105

0.11

0.115

0.12

0.125

Time (s) Fig. 7. Estimated amplitude of the negative sequence component.

approach. This stage is applied to refine oscillations including over and under shoots created in the estimation at the time interval between the sag occurrence (0.1 s in the study case) and the time at which the proposed estimation approach is completely converged. Indeed, modification of the oscillations by means of the post-processing stage brings about an additional time delay from 0.5 to 1 ms at the convergence of the proposed approach. Fig. 8 shows the phase angles of the under-studied voltage sag estimated by the proposed algorithm. It is realized that the algorithm tracks the instantaneous phase angles ð/p1 ; /n1 and /01 Þ in the form of periodic functions with the fundamental frequency (50 Hz) and the variations between 180° and 180°.

3. Sensitivity analyses In order to validate the application of an estimation algorithm in the DVR’s control scheme, it should reflect acceptable performance in estimating voltage sags in different situations. In this section, sensitivity analyses are provided to study the impacts of sag depth, phase angle and frequency variations on the performance of the proposed estimation approach as well as the KF, ADALINE and FFT algorithms. For this purpose, it is initially necessary to

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Neg. Seq.

Zer. Seq

200 150

Angle (deg)

100 50 0 -50 -100 -150 -200 0.06

0.07

0.08

0.09

0.1

0.11

0.12

0.13

0.14

Time (s) Fig. 8. Estimated phase angles of the symmetrical components.

introduce some quantities as the analysis criteria, which will be discussed in the following section. 3.1. PSEE and NSEE criteria The area surrounded between the estimated amplitude curve and related reference value (see Figs. 5–7) can be considered as an appropriate criterion that typically demonstrates the estimation error of an estimation algorithm and hence is representative of its important features such as convergence time and accuracy. This criterion is defined under the titles of PSEE (Positive Sequence Estimation Error) and NSEE (Negative Sequence Estimation Error) as:

 PNc  ref   k¼1 v p   jv p ðkÞj   PSEE ¼  100   ð1  v ref p Þ  fs

ð27Þ

 PNc  ref   jv n ðkÞj k¼1 v n    100 v ref   fs

ð28Þ

NSEE ¼

n

   ref      are the during-sag reference values for the where v ref p  and v n amplitudes of the positive and negative sequence, respectively.         have been considered in the The terms 1  v ref and v ref p  n denominator of the equations above in order to make a uniformity in the error values over sag depth variations. This will help readers to visually recognize whether under-studied algorithm is sensitive to variations or not. The upper limit of the summations (Nc) can be chosen either equivalent to the convergence time of the understudied algorithm or greater than that. At the second choice, the criteria will also include the steady-state estimation error of the algorithm. Considering Figs. 5 and 7, it is found that the proposed approach has an identical behavior in estimating the negative and zero sequence components. For this reason, the sensitivity analyses are restricted to the estimation of the positive and negative sequence components. 3.2. Sensitivity to sag depth variations

amplitudes are decreased from the base case through the similar steps. Note that in the steps of the analysis, the THD of the base waveform changes at each phase in proportion to the corresponding sag depth. The incremental process continues until the amplitude of the fundamental component in every phase reaches 0.9 per unit and the decrementing one proceeds until reaching the symmetrical waveform of 0.1 per unit amplitude, i.e., the boundaries defined on IEEE1159-1995 standard for the voltage sag [30]. The proposed approach and the other algorithms are applied to estimate the waveform generated in each step. Consequently, the amplitudes of the associated positive and negative sequences are achieved. Finally, Eqs. (27) and (28) return the resultant estimation errors which are shown in Figs. 9 and 10, respectively. Considering Fig. 9, the PSEE values of the proposed approach are less than the half of those of the KF and ADALINE and also less than the quarter of the FFT’s error values. This confirms the faster convergence of the proposed approach in comparison with the other algorithms. As shown in Fig. 10, the NSEEs of the KF, ADALINE and FFT algorithms are non-uniform over the steps of the sensitivity analysis, especially at the final points of the decrementing process, where the error values rise with a sharp slope. This will be more evident if the variances of the NSEEs are calculated over the analysis’ steps, resulting in the values of 0.0053, 1.0294, 1.0889, and 0.2936 for the proposed approach, KF, ADALINE and FFT, respectively. The reason for the significant variances of the KF, ADALINE and FFT is severe overshoots that appear in the estimation of the algorithms at the beginning of the sag. This can be regarded as a drawback of the mentioned algorithms, whereas the proposed estimation approach has passed the analysis’ stages with more uniform and less estimation error values. The serious impact of the estimation algorithm on the DVR’s response time encouraged us to calculate the convergence time of the proposed approach and the other algorithms in the steps of the earlier sensitivity analysis. The results are shown in Fig. 11. Additionally, Fig. 12 illustrates the mean value of the convergence times in the form of the bar charts. In these calculations, the convergence time is considered as the time duration thereafter the estimated amplitudes of the positive and negative sequences    ref  settle in the range     of ‘‘v ref p   10% of sag depth’’ and ‘‘±90% of v n ’’, respectively. 3.3. Sensitivity to phase angle variations In most cases, voltage sag events are accompanied by some displacement in phase angles known as Phase Angle Jump (PAJ) [1]. 1.2 1.1 1 0.9 Proposed KF ADALINE FFT

0.8

PSEE (%)

Pos. Seq.

0.7 0.6 0.5 0.4 0.3

The sensitivity assessment of the proposed estimation algorithm to sag depth variations is carried out in a way that the three-phase waveform shown in Fig. 4a is considered as the base voltage sag. The PSEE and NSEE of the algorithm in estimating this waveform constitute the Base Points (BP) of the analysis. At first, in an incremental process, the amplitudes of the base case are increased in seven steps of 0.1 per unit. Then, in a decrementing one, the

0.2 0.1 0 -0.6

-0.4

-0.2

BP

0.2

0.4

0.6

Sag depth variation (pu) Fig. 9. Positive Sequence Estimation Error (PSEE).

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H. Abdollahzadeh et al. / Electrical Power and Energy Systems 54 (2014) 598–609

4.5

1.1

4

1 0.9

3.5

0.8 Proposed KF ADALINE FFT

2.5

Proposed (Var=0.0005) KF (Var=0.0053) ADALINE (Var=0.0037) FFT (Var=0.0214)

0.7

PSEE (%)

NSEE (%)

3

2

0.6 0.5

1.5

0.4

1

0.3

0.5

0.2 0.1

0 -0.6

-0.4

-0.2

BP

0.2

0.4

0.6

0 -90

Sag depth variation (pu)

-70

-50

-30

-10 0 10

30

50

70

90

Phase angle jump (deg) Fig. 10. Negative Sequence Estimation Error (NSEE). Fig. 13. Positive Sequence Estimation Error (PSEE).

20

Convergence time (ms)

17.5 Proposed ADALINE KF FFT

15 12.5 10 7.5 5 2.5 0 -0.6

-0.4

-0.2

BP

0.2

0.4

0.6

Sag depth variation (pu) Fig. 11. Convergence times in estimating the positive sequence (solid lines) and negative sequence (dashed lines).

22.5 20

18.3

17.5

Convergence time (ms)

18.9

Pos. Seq. Neg. Seq.

15 12.5 10

8.5 8.6

8.8 9.1

KF

ADALINE

7.5 5

3.0 2.8

2.5 0 Proposed

FFT

Fig. 12. Mean value of the convergence times.

Therefore, it is important to study the sensitivity of the proposed estimation algorithm to angle variations in the phases of the voltage. It is performed in such a way that the three-phase waveform shown in Fig. 4a, but with a balanced sag of 50% and zero phase

angle jump, is considered as the base waveform. At first, the phase angles of the base case are gradually increased in nine steps of 10° (lead PAJs), while the amplitudes of which remain unchanged. Afterwards, the phase angles are decreased from the base case through the identical steps until reaching the PAJ of 90° (lag PAJs). Ultimately, the estimation errors of the algorithms in each step are evaluated through Eq. (27). The results are shown in Fig. 13. Additionally, the variances of the error values have been illustrated in the legend of this figure. As can be found in figure above and is also emphasized by the resulted variances, the estimation errors of the proposed approach are very smooth in comparison with the other algorithms, denoting that it is insensitive to the phase angle jump. 3.4. Sensitivity to frequency variations Power systems frequently undergo variations in the frequency due to the reasons such as variations in the load/generation. Such variations occur at a slow rate and in a limited range around the nominal frequency. Estimation algorithms experience the frequency variations through the samples of the input signals measured from the network and hence can adversely be influenced in performance. Consequently, this section aims to investigate the sensitivity of the estimation algorithms to frequency variations. For this purpose, in the time interval between 0.05 and 0.15 s, the frequency of the base voltage sag signal in Fig. 4a is smoothly increased and decreased by 1 Hz from the nominal frequency (50 Hz) through the sinusoidal functions 50 ± 1  sin[5p(t  0.05)]. The estimation results of the under-studied algorithms for the two situations of the frequency variations are shown in Figs. 14 and 15. The results include the estimated amplitude of the positive and negative sequences. The estimated amplitude of the zero sequence is quite analogous to that of the negative sequence. As can be seen in the Figs. 14 and 15, as a result of applying the variations (both the rise and the reduction) in the frequency of the estimating signal, insignificant oscillations around the reference values are introduced in the estimation of the algorithms. The oscillation in the negative and zero sequences is fairly greater than in the positive sequence. From the results, it is evident regarding the proposed algorithm that the estimated parameters appropriately track the reference values with a distinct advantage in response time over the other algorithms. This points to the fact that the performance of the proposed estimation algorithm is tolerant of frequency variations.

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4. Proposed control scheme

1.1 1

Fig. 16 shows the block diagram of the proposed control scheme. The main function of the control scheme is to prepare the DVR in order to maintain the sensitive load voltage in required amplitudes and phase angles in case of different voltage sags. For this purpose, voltage signals that are constructed in the control scheme should restore the positive-sequence supply voltage. Additionally, in case of unbalanced sags, it should remove the negative and zero sequence components from the supply voltage. In the measurement and estimation unit, an estimation window with a size of 3N samples is initially created by the regular sampling of the three-phase supply voltage and using three serial-input parallel-output shift registers. Then, the amplitudes and phase angles of the symmetrical components are extracted from the estimation window at any time sample using the proposed estimation approach, which was introduced in Section 2. It must be pointed that for more simplification and also based on the fact that the zero sequence component is eliminated in delta/star-connected distribution transformers, therefore the elimination of this component is neglected in the control scheme. However, there will be the possibility of developing the control scheme for the removal of the zero sequence component, too. Moreover, in order to make a further clarification of the control structure and the function of the proposed control scheme, a flowchart demonstrating design steps is provided as shown in Fig. 17. According to the vector diagram of the pre-sag compensating strategy represented in Fig. 2, the compensating voltage for the positive sequence component is the difference between the vectors (phasors) of the pre-sag and sag voltages. Since the proposed estimation approach tracks the instantaneous phase angles (see Fig. 8), these vectors are not accessible. Thus, to implement the pre-sag strategy the alternative is to evaluate the compensating voltage by comparing samples of the instantaneous voltages at any time sample as follows:

0.9

Amplitude (pu)

0.8 0.7 0.6 0.5 0.4

Reference Proposed

0.3

KF & ADALINE

FFT

0.2 0.1 0 0.06 0.07 0.08 0.09

0.1

0.11 0.12 0.13 0.14 0.15

Time (s) Fig. 14. Estimation results of the under-studied algorithms during the rise in the frequency, the positive (upper group) and the negative (lower group) sequence amplitudes.

1.1 1 0.9

Amplitude (pu)

0.8 0.7 0.6 0.5 0.4

Reference

KF & ADALINE

Proposed

0.3

FFT

v pcom ðjÞ ¼ v ppresag ðjÞ  v psag ðjÞ

0.2

  ¼ jv ppresag j  sin x1 t k þ /ppresag  jv psag j    sin x1 tk þ /psag

0.1 0 0.06 0.07 0.08 0.09

0.1

0.11 0.12 0.13 0.14 0.15

Time (s)

ð29Þ

  where v ppresag  and /ppresag are, respectively, the estimated amplitude and phase angle of the supply voltage before sag  positive-sequence  events. In addition, v psag  and /psag are those during sags.

Fig. 15. Estimation results of the under-studied algorithms during the reduction in the frequency, the positive (upper group) and the negative (lower group) sequence amplitudes.

vˆ p1

vˆp1

va vb vc

Measurement and

Symmetrical Component Estimation By the Proposed Approach

sag

φˆp

vabc

p vˆpresag

delay

delay

S&H

p φˆpresag

Memory module

In-phase

φˆn1

S&H n φˆsag

+

vabc

+

-

vˆn ,φˆn

Neg. Seq. Elimination

vacb

Fig. 16. Proposed control scheme.

+ +

reference

n vˆpresag

vˆ n 1 n vˆ sag

vˆ p ,φˆp

Pre-sag

delay

Pos. Seq. Compensation

vˆp ,φˆp

p φˆsag

1

Estimation Unit

Compensation Strategy

Holding signal Sag detector vˆ p

viabc

Switching Pattern (PWM)

Pulses to VSI

H. Abdollahzadeh et al. / Electrical Power and Energy Systems 54 (2014) 598–609

Measurment & Estimation Unit

606

scheme to store the pre-sag phase angle, receive holding signals right at the instants voltage sags are identified by the sag detector. The sag detector is implemented through a comparator, making a comparison between the amplitude of the positive-sequence supply voltage, received from the estimation unit, and that of the nominal supply voltage (e.g., 1 pu). When the difference between these two becomes greater than a threshold, the comparator activates its output, indicating that a voltage sag has occurred. There would be an inevitable time delay in the performance of the sag detector, at least due to the time delay of the estimation unit, causing the amplitude and phase angle to be stored at values after sag events. This leads to an error in evaluating required reference voltages and will result in partial compensations. The solution to the forgoing problem is to calculate the number of the samples (Nd) which is equal to the sag detector’s time delay (Td) using the sampling frequency chosen for the proposed estimation approach (fs) as:

Measuring three-phase supply voltage Generating estimation window of N sample Extracting amplitude and phase angle of pos. & Neg. seq. through proposed approach Generating instantaneous pos. seq. supply voltage Holding pre-sag delayed pos. seq. amplitude through S&H when a sag is detected by sag detector

pre-sag or in-phase?

Nd ¼ ½T d  fs  þ 1

in-phase

Then, a delay with the same number of the samples is applied to the input of the S&H elements and the memory module through the transfer function Z ðNd Þ in discrete-time domain Z. It should be mentioned that the established time delay is such that it is ineffective on the response time of the control scheme. Besides the compensating voltage for the positive sequence, an eliminating voltage is constructed for the negative sequence in a way that is shown in Fig. 16. The DVR’s injection voltage (viabc) results from the summation of these voltages, and then is applied to a pulse width modulator (PWM) in order to obtain switching pulses for voltage source inverters. It is noted that the same implementation of the PWM as in [31] is considered in the proposed control scheme.

Control Strategy

pre-sag Holding pre-sag delayed pos. seq. phase angle through memory as a sag is detected by sag detector Generating instantaneous pos. seq. reference voltage from the pre-sag amplitude & phase angle

Generating instantaneous pos. seq. reference voltage from the pre-sag amplitude & during-sag phase angle

Subtracting the reference from supply voltage to attain pos. seq. compensating voltage

5. Simulation results

Generating instantaneous neg. seq. eliminating voltage from the neg. seq. amplitude & phase angle Adding the compensating and eliminating voltages to attain injecting voltage applied to PWM Fig. 17. Flow chart of design steps of the proposed control scheme.

Moreover, to realize the in-phase strategy, the compensating voltage for the positive sequence should be evaluated as follows:

v pcom ðjÞ ¼ v p0presag ðjÞ  v psag ðjÞ

          ¼ v ppresag   sin x1 tk þ /psag  v psag     sin x1 t k þ /psag

ð31Þ

ð30Þ

  As a consequence, having the amplitude v ppresag , two types of reference voltage are accessible using sample-based sinusoidal   functions. The one v ppresag , via the last-cycle samples of the phase p angle /presag which are stored into a memory module before sag   p events. The other one v p0 presag , via the phase angle /sag which is tracked by the estimation approach during sags. The difference between the resultant reference voltages and the instantaneous sag voltage v psag returns the compensating voltages which make the compensation of voltage sags selectively possible through the pre-sag or in-phase strategy. As shown in Fig. 16, the  amplitude of the positive-se pre-sag quence supply voltage v ppresag  can be stored in the control scheme using sample and hold (S&H) elements. These elements as well as the memory module, which is used in the control

Fig. 18 shows the configuration of a test distribution network. The test network with the parameters given in Appendix A is simulated in PSCAD/EMTDC environment. As shown in Fig. 18, it has been assumed that the test network is a part of a distribution system, which is energized by a medium voltage (MV) substation. The upstream power system has been modeled by the voltage source ‘‘VS’’ and the short circuit impedance ‘‘ZSC’’. The MV substation supplies the system loads at the Common Bus (CB) through the transformer T1. The loads 1 and 3 are inductive and pure resistive, respectively, whereas the load 2 comprises two parts: an inductive and a dc load. The dc part of the load 2, which is supplied through a three-phase diode rectifier, draws a non-linear current that brings about a harmonic distortion with a THD of around 5% in the voltage waveforms. The symmetrical and single-line to ground short circuits are considered at the end of the feeder 1 to make balanced and unbalanced sags in the other feeders. In order to protect the load 2, which is consider as the sensitive load, against the voltage sags, a DVR which is based on the control scheme represented in Fig. 16, is installed on the feeder 2 between the transformer T3 and the load bus. The configuration of the simulated DVR is the same as in Fig. 1 with specifications detailed in Appendix B. The balanced voltage sag is compensated by the in-phase strategy, whereas the unbalanced one is considered to be compensated by the pre-sag strategy. Figs. 19 and 20 illustrate the simulation results related to the compensation of the balanced and unbalanced voltage sags, respectively. These figures include, from up to down, the supply voltage (VS), injected voltage of the DVR (Vinj) and compensated load voltage (Vl), respectively. Furthermore, Fig. 21 demonstrates the restored phase angles of the load side voltage in the second simulation, which are compared with those of the supply side voltage. It

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H. Abdollahzadeh et al. / Electrical Power and Energy Systems 54 (2014) 598–609

(a) 5.4 #1

Vs (kV)

Zsc

T1

a

0

b

#2

-5.4

(b) R2 L2

L1

Feeder 3

Feeder 2

Feeder 1

R1

Vinj (kV)

CB R3

0 -3

b a b

#1

T4

T3

#2

#2

T2

Vl (kV)

(c) 5.4 #1

c

a +3

L3

Fault

#1

c

c

0 -5.4

#2

0.05

0.1

0.15

DVR

load1

Fig. 20. Simulation results of the unbalanced voltage sag compensation in pre-sage strategy: (a) Supply voltage (VS), (b) injected voltage (Vinj), and (c) compensated load voltage (Vl).

load2

+150

Fig. 18. Under-studied distribution network.

+100

b

-5.4

Vinj (kV)

b

c c

-50

(b)

-100 -150

(c)

-200 -250 0

-4

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Time (s) a

b

Fig. 21. Phase angles of the supply side voltage (dashed lines) and load side voltage (solid lines).

c

0 -5.4 0.05

0

a

0

(c) +5.4 Vl (kV)

Angle (deg)

Vs (kV)

a

0

+4

(a)

+50

(a) +5.4

(b)

0.2

Time (s)

load3

0.1

0.15

0.2

Time (s) Fig. 19. Simulation results of the balanced voltage sag compensation: (a) Supply voltage (VS), (b) injected voltage (Vinj), and (c) compensated load voltage (Vl).

is necessary to state that, these angles have been estimated by means of the FFT algorithm. As can be seen in Fig. 19, the symmetrical short circuit in the feeder 1 results in a balanced deep sag in the fundamental voltage of the feeder 2 with a remaining amplitude of 1.6 kV. In this case, the DVR injects a symmetrical voltage of 3.8 kV to the supply voltage to maintain the amplitude of the load voltage in the pre-fault value. As shown in Fig. 20, the single-line to ground short circuit (line ‘‘a’’ to ground) reduces the amplitude of the supply voltage in the

phases a and c identically to 3.4 kV and increases that in the phase b to 5.8 kV (i.e., 7.4% swell). In addition, Fig. 21 makes it obvious that the unbalanced short circuit leads to asymmetry in the phase angles of the supply voltage (VS). The phase angle jumps associated with the phases a, b and c are 0.9°, 20.3° and 23.2°, respectively. The simulation results in Figs. 20 and 21 indicate that the suggested control scheme has successful performance in restoring both the amplitudes and phase angles of the load side voltage (Vl) to the pre-fault values and accordingly ensures the achievement of the pre-sag compensating strategy. To have a further insight into the estimation algorithms’ impacts on the protective function of the DVR, the previous simulation related to the balanced voltage sag is individually repeated by applying the KF, ADALINE and FFT, besides the proposed algorithm, in the control scheme. During the simulations, the instantaneous active power, which is not supplied by the DVR, is evaluated as shown in Fig. 22. The illustrated power curves have been obtained through the voltage and current measured at the DC-link of the DVR.

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H. Abdollahzadeh et al. / Electrical Power and Energy Systems 54 (2014) 598–609

the symmetrical components have approved the application of the approach in the DVR. For this purpose, a new control scheme, in consistence with proposed estimation approach, has been introduced in detail, enabling the DVR to compensate different types of voltage sag. The simulation results have revealed the successful performance of the proposed control scheme, from the response time and accuracy standpoint, in restoring the load voltage through both the pre-sag and in-phase compensating strategies.

+600 (III)

(I). Proposed (II). KF (III). ADALINE (IV). FFT

(IV)

Active Power (kW)

+400

+200 (II)

0

Appendix A. Distribution network parameters

-200

-400

(I)

-600 0.095

0.1

0.105

0.11

0.115

0.12

0.125

Time (s) Fig. 22. Non-supplied instantaneous active power.

I. Supply: Vs = 63 kV, Ssc = 500 MVA. II. Transformers: T1: 63D/20Yg kV, 10 MVA, Uk = 15%, T2: 20D/ 0.4Yg kV, 1 MVA, Uk = 7%, T3: 20D/6.6Yg kV, 1.5 MVA, Uk = 7%, T4: 20D/11Yg kV, 3 MVA, Uk = 10%. III. Feeders: R1 = 0.3 X, L1 = 0.001 H, R2 = 0.2 X, L2 = 0.001 H, R3 = 0.1 X, L3 = 0.001 H. IV. Loads: P1 = 500 kW, Q1 = 100 kVar, P2 = 1 MW, Q2 = 500 kVar, P3 = 2.3 MW, Q3 = 0. Appendix B. Simulated DVR parameters

35

31.71

30

Energy (%)

25 20

17.69

References

15.77 15 10

7.02

5 0 Proposed

KF

ADALINE

Power rating: 1 MVA, Energy storage: Battery and Vdc = 2 kV, Injection transformer: 2/5.4 kV, 1 MVA, Uk = 5%, Passive filters: Cf = 30 uF, Lf = 0.5 mH, Voltage source inverter (VSI): H-bridge type with IGBT power electronic valves, Switching pattern: SPWM and fSW = 4 kHz.

FFT

Fig. 23. Percentage of the non-supplied energy.

Integrating each of the instantaneous power curves over the compensation period (200 ms), gives the total amount of the energy that is not supplied by the DVR. The non-supplied energy is expressed as the percentage of the energy that protected load consumes during one cycle period, as shown in Fig. 23.

6. Conclusions In this paper, a new approach has been proposed in order to estimate the symmetrical components of desired frequencies for on-line and fast-responding applications. With the objective of employing the approach in the DVR, sensitivity analyses have been conducted to investigate the impacts of sag depth, phase angle and frequency variations on its performance in estimating the fundamental-frequency symmetrical components. The results of the sensitivity analyses have indicated that the proposed approach not only has the smallest estimation errors in comparison with the KF, ADALINE and FFT algorithms, but also reflects very low sensitivity to the sag depth variations and phase angle jumps. In addition, the sensitivity analyses have demonstrated the robust performance of the proposed approach in frequency variation conditions. These features along with the convergence time of about 3 ms in estimating both the amplitude and phase angle of

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