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A new high injection efficiency non-volatile memory cell: BipFlash
Solid-State Electronics 46 (2002) 1739–1747 www.elsevier.com/locate/sse
A new high injection efficiency non-volatile memory cell: BipFlash q David Esseni a
a,*
, Luca Selmi a, Roberto Bez b, Alberto Modelli
b
DIEGM, University of Udine, Via delle Scienze 208, 33100 Udine, Italy b ST Microelectronics, Agrate Brianza, Italy
Abstract This paper presents a novel non-volatile memory cell architecture (BipFlash), which improves remarkably injection efficiency over that obtained with conventional channel hot-electron programming. The cell concept is validated by means of numerical device simulations including accurate Monte Carlo analysis of hot carrier transport and injection in the floating gate. Design strategies to achieve optimum device performance and possible solutions for cell layout and array organization are also discussed. We show that the superior performance of BipFlash in terms of injection efficiency can be traded to achieve either very low voltage, low power or high-speed operation. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction High-speed, low-power systems demand non-volatile memories (NVM) capable of a fast programming with a modest current absorption and at ever decreasing power supply voltages. For stacked-gate flash memories with a common ground NOR architecture that exploit channel hot-electron (CHE) programming the above requirements result in the need for a large gate current (IG ) and a small drain current (ID ), that is in the need for a high injection efficiency g ¼ ½IG =ID [1]. Unfortunately CHE injection is inherently characterized by a low programming efficiency and [IG /ID ] decreases rapidly when VDS drops below approximately 3.2 V because the potential energy difference between source and drain becomes lower than the energy barrier between silicon and SiO2 . In flash memories the need for a relatively large drain voltage (VD ) is frequently addressed by means of charge pump-circuits that generate a ‘bit-line’ voltage above the supply voltage [2,3]. This circuital technique, besides the obvious drawback of a
q
Patent pending. Corresponding author. Tel.: +39-43255-8294; fax: +3943255-8521. E-mail address: [email protected] (D. Esseni). *
silicon area overhead, limits the maximum current that can be reliably absorbed by the bit-line without causing an intolerable reduction of its voltage. Consequently low ID values and large injection efficiency are again very important figures of merit for the memory cell. A modern stacked-gate flash memory cell fabricated with an up-to-date technology can typically achieve an efficiency of only approximately g ¼ ð1–4Þ 105 with a drain bias VD ’ 4:5 [4]. Since a larger efficiency can be achieved using substrate hot-electron injection [5,6], attempts were made to generate electrons in the substrate using either a lateral bipolar transistor [7,8] or a buried diffusion [9]. However the low collection efficiency of the gate depletion region in scaled cells and the poor selectivity of such a programming operation seriously hampered the success of these approaches. In order to improve the programming performance of flash memories several alternative hot-electron mechanisms have been proposed [10,11] and cell architectures attaining a better CHE injection than conventional stacked-gate devices have been developed [12,13]. Recently the channel initiated substrate electron injection (CHISEL) [14–17] emerged as a very promising hot-electron mechanism to improve CHE injection efficiency especially in the low-voltage regime [18,19], but concerns exist about the impact of cell scaling on the injection efficiency of of this mechanism as discussed in [20].
0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 1 4 3 - 0
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This paper presents a new NVM cell architecture that we called bipolar flash (BipFlash) which exploits the injection of hot-electrons that are generated right into the depletion region of the cell thanks to the impact ionization of properly injected holes. This approach circumvents the difficult implementation of an electron source in the p-type substrate [7–9] and exploits an impact-ionization feedback mechanism similar to CHISEL but with a totally different source for the holes flowing toward the substrate. The results of our study indicate that the BipFlash cell can achieve remarkably high injection efficiency and seems particularly promising in the perspective of very low-voltage applications. The realization of the pþ injector within the drain results in an area penalty for the BipFlash with respect to a standard stacked-gate flash cell that suggests how the new cell design might be more convenient for embedded rather than stand-alone applications.
floating gate voltage VFG > VD is enforced by means of the external control gate voltage (VCG ). The pþ emitter is forward biased with respect to the drain (VEM > VD ) so that holes are injected to the drain region and, if they escape recombination, can eventually reach the substrate as it is well known from the theory of the bipolar junction transistor (BJT) [21]. A fraction of holes traveling in the high electric field, depletion region below the channel of the cell can create electron–hole pairs by impact ionization and the generated electrons are accelerated back towards the Si–SiO2 interface and can be eventually injected into the floating-gate. It is apparent that using these programming conditions there is no channel current flowing from source to drain and the largest current in the device should be the substrate current IB that is the total hole current due to holes injected from the pþ emitter plus those generated by impact ionization. 2.2. An analytic expression for the injection efficiency
2. The bipolar flash cell 2.1. Basic concept of the cell Fig. 1 shows a sketch of the BipFlash indicating the pþ shallow hole emitter embedded in the drain junction and the voltages and currents which are relevant for the device operation. The read and erase operation can be performed similarly to the conventional stacked-gate flash cell. In these operations, in fact, the hole emitter plays no role and can be either left floating or shortcircuited to the drain. The programming operation is where the innovative device structure is used. During programming source and drain are short circuited and reverse biased with respect to the substrate (i.e. VS ¼ VD > VB ) and a large
If we consider the sketch of the bipolar device of Fig. 1 and neglect the recombination current in the drain region (the base of the pnp bipolar transistor) we can express the emitter current as: ðEMÞ
IEM ¼ Ih
ðEMÞ þ Irec
ð1Þ
ðEMÞ Ih
is the current due to hole diffusion from where emitter to drain whereas IEM rec is due to the recombination of electrons injected from the drain to the pþ emitter [22]. If we denote with Mp an overall multiplication factor for holes injected from the drain toward the bulk ðEMÞ then Ih;ion ¼ ðMp 1ÞIh is the current produced by hole impact ionization in the depletion region of the cell so that the substrate and drain currents can be written as: ðEMÞ
I B ¼ Mp Ih
ð2Þ ðEMÞ
ðEMÞ ðMp 1ÞIh ID ¼ Irec
ð3Þ
According to the above IEM and IB expression we can write the common base current gain of the BJT as: hFB ¼
Fig. 1. Sketch of the BipFlash cell during programming. Mp is the multiplication factor of holes in the drain/substrate depletion region and PB is the probability that secondary electrons are injected back into the gate. A graded N doping region below the emitter favours hole injection at the edge of the channel as described in detail in Section 3. The equivalent pnp bipolar transistor consisting of the pþ hole emitter, the drain junction and the p-type substrate is also sketched.
ðEMÞ Ih ðEMÞ ðEMÞ Ih þ Irec
ð4Þ
Using Eqs. (2)–(4) the emitter current can be rewritten as ðEMÞ IEM ¼ Ih =hFB and we readily see that IB is the largest current of the device if Mp > h1 FB whereas IEM becomes larger than IB otherwise. Furthermore, if we indicate with PB an overall injection probability for electrons generated in the depletion region, as schematically illustrated in Fig. 1, the gate current can be written as: ðEMÞ
IG ¼ PB ðMp 1ÞIh
ð5Þ
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so that, assuming that IB is the largest current of the device (i.e. Mp > h1 FB ), we can finally express the injection efficiency of the BipFlash as: IG Mp 1 : ð6Þ g ¼ ¼ PB IB Mp It is apparent from Eq. (6) that the injection efficiency is independent of the BJT current gain as long as Mp > h1 FB and that, furthermore, IG =IB increases weakly with Mp when this latter is larger than approximately 1.2. In this case only a modest advantage is obtained by operating the cell at much larger multiplication levels. If hFB is so low that Mp < h1 FB , instead, IEM is the largest current in the device and the efficiency becomes: IG ¼ PB ðMp 1ÞhFB : g¼ IEM
ð7Þ
In the above analysis we have used simple parameters (Mp and PB ) to concisely refer to the multiplication factor of holes in the depletion region and to the injection probability of generated electrons. Note, however, that in general PB is different from the electron injection probability in substrate hot-electron injection experiments [5,6], because both the electron generation rate (due to hole impact ionization) and the electric fields accelerating electrons back toward the interface are spacially non-uniform and part of generated electrons can be simply swept into the drain without contributing to the gate current. Therefore, a realistic calculation of the gate current, hence injection efficiency, demands 2D numerical simulations of both electron and hole transport. Monte Carlo simulations dealing with the above problem will be presented in Section 4 while some issues concerning the design of the cell are first discussed in Section 3.
3. Issues in the design of the BipFlash cell In order to validate the operation of the BipFlash we first performed extensive drift–diffusion simulations to describe the hole emission from the pþ region (Fig. 1). For our calculations we always considered the equivalent transistor of the cell (i.e. the transistor that would be obtained if the floating-gate were directly accessible). The simulated device structure is compatible with the design constraints of a 0.25 lm flash technology and the numerical values of the main technological parameters are indicated in Fig. 2. As can be readily seen from Eq. (5), the fraction of the emitter current that is useful for hot-electron injection is ðEMÞ Ih and, furthermore, the flux of holes must be mostly directed toward the depletion region below the channel of the cell to become effective for the cell programming. ðEMÞ In order to increase the useful fraction of Ih it is ad-
Fig. 2. Sketch of the equivalent transistor used for the simulations of the BipFlash cell and numerical values of the technological parameters. Tox is the tunnel oxide thickness (between floating-gate and silicon), xjnþ , xjn and xjpþ are the depths of the nþ , n and pþ diffusion, respectively, and Lmet is the metallurgical channel length.
vantageous to introduce an n diffusion, as illustrated in Figs. 1 and 2, that is able to increase the hole current density directed toward the channel with respect to the current density toward the nþ portion of the drain. Fig. 3(b) reports the simulated integral of the emitter hole current density (normalized to IEM ) along a curved perimeter of the emitter junction as indicated in Fig. 3(a). These simulations account for the variations of the intrinsic carrier concentration in the pþ , n and nþ regions due to the effective band-gap narrowing [23–25]. A large fraction (>80%) of IEM is injected in the pþ /n portion of the emitter junction (hence toward the channel) if the n doping concentration is an order of magnitude lower than the nþ one. These results confirm the effectiveness of the doping gradient in enhancing lateral hole injection. We also verified that, according to simulations, the decrease of drain doping in the n region does not cause an excessive increase of the series resistance, hence degradation of the read current. Leakage across the pþ /nþ part of the emitter junction is not necessarily a problem because the cell can be operated avoiding reverse bias conditions on this junction. Another possible issue in the design of the BipFlash is that a parasitic p-MOS transistor is formed by the n region when this latter is fully overlapped by the gate as illustrated in Fig. 4(a). If VD is large enough with respect to VFG then the parasitic p-MOSFET can turn on and short-circuit the BJT transistor. In order to prevent the p-MOSFET from turning on it is sufficient that the pþ emitter does not reach the thin oxide region diffusing below the spacer. In fact, whenever the n is not fully overlapped by the gate then the p-MOSFET cannot be turned on. This is readily confirmed by the numerical simulations in Fig. 4(b) showing the onset of the
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Fig. 3. (a) Curve around the emitter used for hole current density calculations. (b) Simulated integral of the hole current density (normalized to the total IEM ) along the emitter perimeter for different values of the peak doping concentration of the N extension. The peak concentration of the N extension is approximately 7 1018 cm3 . A large fraction (>80%) of IEM is injected in the pþ /n portion of the emitter junction.
parasitic current when the n is fully overlapped and its complete suppression when the n is not fully overlapped. In the latter case the length of the n extension which is not overlapped by the gate is slightly shorter than 0.1 lm. The introduction of the n extension and the constraint to avoid a complete overlap between the floatinggate and the n region finally explain the structure of the cell proposed in Fig. 1.
4. Numerical simulations of the injection efficiency The gate current characteristics and injection efficiency of the BipFlash have been numerically calculated
Fig. 4. (a) Sketch showing the parasitic p-MOSFET when the N extension is fully overlapped by the floating-gate. (b) Emitter current IEM versus the floating-gate voltage for a given VD . When no overlap is present the parasitic conduction is fully suppressed whereas IEM increases at low VFG for the fully overlapped N extension because of the parasitic p-MOSFET. In the non-fully overlapped case the length of the N extension which is not overlapped by the gate is slightly shorter than 0.1 lm.
using a full-band Monte Carlo simulator extensively described in previous papers [26]. The impact-ionization scattering rates have been validated both on MOS and BJT transistors [27], the high-energy electron transport and oxide injection models have been calibrated in [6] and a quantitatively adequate description of the CHISEL mechanism is documented in [20]. In order to achieve an efficient simulation procedure a current boundary condition is imposed during Monte Carlo simulations where holes are injected along the perimeter of the pþ emitter according to the hole current density profile obtained by drift–diffusion simulations
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(see Fig. 3). Then a complete simulation including both holes and electrons generated by impact ionization is performed. The impact ionization of both holes and electrons is considered for the calculation of the overall substrate current IB whereas those electrons that are accelerated back toward the interface and eventually injected through the oxide contribute to the gate current IG . Fig. 5(a) illustrates typical results for the electron generation rates due to hole impact ionization within the
Fig. 6. BipFlash injection efficiency IG /IB versus VD ¼ VS and jVB j. For a given VFG > VD , IG /IB is essentially a function of VDB ¼ VD VB as confirmed by the two curves at jVB j ¼ 0 and 2.0 V.
Fig. 5. (a) Simulated electron generation rate Ge (cm3 s1 ) due to hole impact ionization in the BipFlash cell. The drain junction (i.e. the junction between p-type channel and N extension) is at X ¼ 0:58 lm. The Si–SiO2 interface is at y ¼ 0. VD ¼ 3 V, jVB j ¼ 2 V, VFG ¼ 5 V. (b) Gate current density at the Si–SiO2 interface for two possible programming bias conditions with either VB ¼ 0 V or jVB j ¼ 2 V.
depletion region of the cell. The maximum of the generation rate takes place relatively close to the drain-bulk junction and Fig. 5(b) shows that the maximum density of the gate current is injected at the Si–SiO2 right above the region of electron generation. In the simulated device the condition Mp > h1 FB is always verified so that in the following of the paper the injection efficiency of the BipFlash is always calculated according to Eq. (6) as IG /IB . Fig. 6 illustrates the BipFlash efficiency versus the drain voltage (that is equal to the source voltage) and for two different substrate voltages. As can be seen, a large efficiency (approximately 5 104 ) with respect to conventional CHE can be achieved with VD ’ 3:3 V even with no substrate bias. Furthermore, when a jVB j ¼ 2 V is used a very remarkable IG =IB ’ 3 103 is predicted by simulations. It is worth noting that in the programming mechanism employed by the BipFlash the most important bias governing the injection efficiency is the drain to substrate voltage (VDB ), provided VFG is large enough to induce strong inversion in the channel, and in fact Fig. 6 shows that approximately the same IG /IB value is obtained either for VD ¼ 1:5 V and jVB j ¼ 2 V or for VD ¼ 3:5 V and jVB j ¼ 0 V that give the same VDB ¼ 3:5 V. Fig. 7 reports IG /IB versus the floating-gate voltage and shows how, for given values of VD ¼ VS and VB , hotelectron injection can be suppressed by reducing VFG . The IG /IB drop at low VFG can be explained as follows. If VFG becomes smaller than VD þ VT , where VT is the threshold voltage possibly increased by the body-effect when VD > VB , then the potential at the Si–SiO2 interface starts decreasing thus reducing the total bulk-to-interface voltage drop that is crucial for electron injection. At this regard, we can also add that a larger available
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As for the values of gate current that can be obtained by the BipFlash, it is apparent from Eqs. (2), (3) and (5) that both IG and IB are simply proportional to IEM in any IEM range where hFB is fairly constant and the hole current density does not significantly change the electric field configuration so that Mp and PB are also approximately constant. This fact is confirmed by the results of Fig. 8 showing the IG versus IB curve that is obtained by changing the emitter current for given VFG , VD and VB values. As can be seen IG is essentially proportional to IB so that, for a fixed injection efficiency, IG can be easily varied to achieve different programming speeds. 5. Calculation of the programming characteristics
Fig. 7. BipFlash injection efficiency, IG /IB , as a function of floating gate voltage VFG . The IG decrease at low VFG demonstrates the possibility to suppress injection in unselected cells by enforcing a low VFG value through the control-gate bias (i.e. the word-line voltage).
voltage budget is provided by applying a negative VB and this explains why in Fig. 7 the IG /IB drop with decreasing VFG is stronger for the two curves having VB ¼ 0 V. Furthermore, when VFG becomes lower than VD , then the oxide field is reversed close to source and drain junctions thus suppressing the electron injection (at least in the periphery of the channel) because of an increased energy barrier. The IG suppression at low VFG is an essential feature for a memory cell in order to inhibit programming of unselected cells connected to a given bit-line by grounding the corresponding ‘wordline’.
Once the IG versus VFG characteristics have been obtained using Monte Carlo simulations, the corresponding programming characteristics can also be simulated as follows. During a programming operation where VCG , VD and VB are constant and the emitter current IEM is also fixed, the equation governing the floating-gate voltage transient is given by [28,29]: dVFG IG ½VFG ðtÞ ¼ aCG ; Cpp dt
ð8Þ
where Cpp is the inter-poly capacitance and aCG is the control to floating-gate capacitive coupling ratio [30]. Eq. (8) is a differential equation that can be solved for using the Runge–Kutta method [31] with an initial value for the floating-gate voltage: VFG0 ¼ VT-FG þ aCG ðVCG VT0 Þ þ aD VD þ aS VS :
ð9Þ
In Eq. (9) VT-FG is the threshold voltage at the floating-gate, aD (aS ) is the control-gate to drain (source) coupling ratio and, if we denote with QFG0 the initial value of the floating-gate charge (QFG0 ¼ 0 for a neutral floating-gate), then the initial threshold voltage is VT0 ¼ VT-FG =aCG QFG0 =Cpp . The solution of Eq. (8) readily provides also the time dependent gate current IG [VFG (t)]. Then the threshold voltage can be calculated as: QFG ðtÞ Cpp Z t 1 ¼ VT0 þ IG ½VFG ðgÞ dg: Cpp 0
VT ðtÞ ¼ VT0
Fig. 8. BipFlash gate current versus substrate current. IG is approximately proportional to IB . A relatively large range of IG values can be obtained for a given efficiency (g ’ 103 in this figure).
ð10Þ
Figs. 9 and 10 show the VT versus time evolution for different programming conditions where the values used for parameters aCG , aD , aS and Cpp are reported in the figure captions and are realistic for the device structure used for simulations [4]. With VD ¼ 3:0 V, jVB j ¼ 2:0 V and IB ¼ 10 lA, the BipFlash can achieve a 4-V shift of VT in only 300 ns (high speed programming––Fig. 9) while the same VT shift can be obtained with VD ¼ 3:3
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achieve different tradeoffs between programming time and power consumption. This flexibility in the programming conditions is an advantageous feature of the BipFlash that is inherently related to its hot-electron programming mechanism. 6. Array organization and biasing scheme
Fig. 9. High-speed programming characteristics of the BipFlash for VD ¼ 3:0 V and jVB j ¼ 2:0 V. aCG ¼ 0:6, aD ¼ 0:1, Cpp ¼ 1 fF.
In order to maintain at the array level the low power dissipation characteristics of the BipFlash and to achieve a selective programming, it is mandatory that no other emitters than those of the cells being programmed is forward biased during the program operation. This result is easily accomplished by providing separate bit-lines for the source and drain, running the pþ emitter lines parallel to the word-lines and keeping the emitter junction of the unselected cells at equilibrium by biasing the un-selected bit-lines at the emitter potential. Fig. 11 presents a possible array organization and a biasing scheme for the programming operation that fulfill these requirements. The pþ emitter lines can be fabricated in metal 1 and run horizontally across the array on top of the control
Fig. 10. Low-voltage programming characteristics of the BipFlash for VD ¼ 3:3 V and VB ¼ 0 V. aCG ¼ 0:6, aD ¼ 0:1, Cpp ¼ 1 fF.
but no substrate bias in approximately 2 ls (Fig. 10). The results of Fig. 10 are particularly promising in the viewpoint of an elimination of charge pumping circuits in embedded memory applications to be used in 3.3 V single supply systems. In the above programming characteristics we deliberately used an IB ¼ 10 lA value which is much smaller than typical drain currents absorbed during channel hotelectron programming in conventional stacked-gate flash cells. Since Fig. 8 demonstrates that IG is proportional to IB (through IEM ) in a relatively large IB range, then the programming time is approximately inversely proportional to the maximum current absorption (IB ) so that the emitter current IEM represents a useful knob to
Fig. 11. Schematic drawing of a possible array organization for the BipFlash. emitter and word-lines run in the horizontal direction whereas each column has both independent bit and source lines that run in the vertical direction. A possible bias scheme for the Array during the program operation is also indicated in the Table.
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gate word-lines whereas two separate metal 2 bit-lines (main source and bit-lines) can run in the vertical direction. A preliminary study of the cell layout indicates that the implementation of an optimized BipFlash results in a cell size that is approximately six times larger than a standard stacked-gate flash cell in a NOR array. This area penalty is not so severe and makes the BipFlash a promising device especially for embedded applications in very low power systems. 7. Conclusions We demonstrated a new NVM cell concept, BipFlash, suitable to attain efficient carrier injection in the floating gate at low voltage. Numerical simulations suggest that properly optimized BipFlash cells could attain an injection efficiency up to two orders of magnitude higher than a conventional stacked-gate flash cell in a NOR array that is programmed by CHEs. The cell size, although larger than that of the conventional stacked-gate cell, is expected to be still adequate for embedded applications especially where low density but very low voltage, low power consumption are required. Two independent quantities, the pþ emitter current and the drain to substrate voltage, can be separately adjusted to attain the desired performance in terms of programming speed and power consumption. These features of the BipFlash cell open a wide range of possibilities to tailor its programming characteristics to the needs of specific applications. In particular, simulations suggest that it might be possible to program the cell with adequate speed while driving the main programming current directly from a 3.3-V power supply line, thus eliminating the need for the area consuming charge pumping circuits. As a result, the BipFlash appears to be an extremely promising approach to scale floating-gate NVM cells towards significantly lower operating voltages than those currently in use.
Acknowledgements The authors would like to thank P. Palestri (DIEGM, University of Udine) for support with Monte Carlo simulations and P. Cappelletti (ST Microelectronics, Italy) for helpful discussions.
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A new high injection efficiency non-volatile memory cell: BipFlash q David Esseni a
a,*
, Luca Selmi a, Roberto Bez b, Alberto Modelli
b
DIEGM, University of Udine, Via delle Scienze 208, 33100 Udine, Italy b ST Microelectronics, Agrate Brianza, Italy
Abstract This paper presents a novel non-volatile memory cell architecture (BipFlash), which improves remarkably injection efficiency over that obtained with conventional channel hot-electron programming. The cell concept is validated by means of numerical device simulations including accurate Monte Carlo analysis of hot carrier transport and injection in the floating gate. Design strategies to achieve optimum device performance and possible solutions for cell layout and array organization are also discussed. We show that the superior performance of BipFlash in terms of injection efficiency can be traded to achieve either very low voltage, low power or high-speed operation. Ó 2002 Elsevier Science Ltd. All rights reserved.
1. Introduction High-speed, low-power systems demand non-volatile memories (NVM) capable of a fast programming with a modest current absorption and at ever decreasing power supply voltages. For stacked-gate flash memories with a common ground NOR architecture that exploit channel hot-electron (CHE) programming the above requirements result in the need for a large gate current (IG ) and a small drain current (ID ), that is in the need for a high injection efficiency g ¼ ½IG =ID [1]. Unfortunately CHE injection is inherently characterized by a low programming efficiency and [IG /ID ] decreases rapidly when VDS drops below approximately 3.2 V because the potential energy difference between source and drain becomes lower than the energy barrier between silicon and SiO2 . In flash memories the need for a relatively large drain voltage (VD ) is frequently addressed by means of charge pump-circuits that generate a ‘bit-line’ voltage above the supply voltage [2,3]. This circuital technique, besides the obvious drawback of a
q
Patent pending. Corresponding author. Tel.: +39-43255-8294; fax: +3943255-8521. E-mail address: [email protected] (D. Esseni). *
silicon area overhead, limits the maximum current that can be reliably absorbed by the bit-line without causing an intolerable reduction of its voltage. Consequently low ID values and large injection efficiency are again very important figures of merit for the memory cell. A modern stacked-gate flash memory cell fabricated with an up-to-date technology can typically achieve an efficiency of only approximately g ¼ ð1–4Þ 105 with a drain bias VD ’ 4:5 [4]. Since a larger efficiency can be achieved using substrate hot-electron injection [5,6], attempts were made to generate electrons in the substrate using either a lateral bipolar transistor [7,8] or a buried diffusion [9]. However the low collection efficiency of the gate depletion region in scaled cells and the poor selectivity of such a programming operation seriously hampered the success of these approaches. In order to improve the programming performance of flash memories several alternative hot-electron mechanisms have been proposed [10,11] and cell architectures attaining a better CHE injection than conventional stacked-gate devices have been developed [12,13]. Recently the channel initiated substrate electron injection (CHISEL) [14–17] emerged as a very promising hot-electron mechanism to improve CHE injection efficiency especially in the low-voltage regime [18,19], but concerns exist about the impact of cell scaling on the injection efficiency of of this mechanism as discussed in [20].
0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 3 8 - 1 1 0 1 ( 0 2 ) 0 0 1 4 3 - 0
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This paper presents a new NVM cell architecture that we called bipolar flash (BipFlash) which exploits the injection of hot-electrons that are generated right into the depletion region of the cell thanks to the impact ionization of properly injected holes. This approach circumvents the difficult implementation of an electron source in the p-type substrate [7–9] and exploits an impact-ionization feedback mechanism similar to CHISEL but with a totally different source for the holes flowing toward the substrate. The results of our study indicate that the BipFlash cell can achieve remarkably high injection efficiency and seems particularly promising in the perspective of very low-voltage applications. The realization of the pþ injector within the drain results in an area penalty for the BipFlash with respect to a standard stacked-gate flash cell that suggests how the new cell design might be more convenient for embedded rather than stand-alone applications.
floating gate voltage VFG > VD is enforced by means of the external control gate voltage (VCG ). The pþ emitter is forward biased with respect to the drain (VEM > VD ) so that holes are injected to the drain region and, if they escape recombination, can eventually reach the substrate as it is well known from the theory of the bipolar junction transistor (BJT) [21]. A fraction of holes traveling in the high electric field, depletion region below the channel of the cell can create electron–hole pairs by impact ionization and the generated electrons are accelerated back towards the Si–SiO2 interface and can be eventually injected into the floating-gate. It is apparent that using these programming conditions there is no channel current flowing from source to drain and the largest current in the device should be the substrate current IB that is the total hole current due to holes injected from the pþ emitter plus those generated by impact ionization. 2.2. An analytic expression for the injection efficiency
2. The bipolar flash cell 2.1. Basic concept of the cell Fig. 1 shows a sketch of the BipFlash indicating the pþ shallow hole emitter embedded in the drain junction and the voltages and currents which are relevant for the device operation. The read and erase operation can be performed similarly to the conventional stacked-gate flash cell. In these operations, in fact, the hole emitter plays no role and can be either left floating or shortcircuited to the drain. The programming operation is where the innovative device structure is used. During programming source and drain are short circuited and reverse biased with respect to the substrate (i.e. VS ¼ VD > VB ) and a large
If we consider the sketch of the bipolar device of Fig. 1 and neglect the recombination current in the drain region (the base of the pnp bipolar transistor) we can express the emitter current as: ðEMÞ
IEM ¼ Ih
ðEMÞ þ Irec
ð1Þ
ðEMÞ Ih
is the current due to hole diffusion from where emitter to drain whereas IEM rec is due to the recombination of electrons injected from the drain to the pþ emitter [22]. If we denote with Mp an overall multiplication factor for holes injected from the drain toward the bulk ðEMÞ then Ih;ion ¼ ðMp 1ÞIh is the current produced by hole impact ionization in the depletion region of the cell so that the substrate and drain currents can be written as: ðEMÞ
I B ¼ Mp Ih
ð2Þ ðEMÞ
ðEMÞ ðMp 1ÞIh ID ¼ Irec
ð3Þ
According to the above IEM and IB expression we can write the common base current gain of the BJT as: hFB ¼
Fig. 1. Sketch of the BipFlash cell during programming. Mp is the multiplication factor of holes in the drain/substrate depletion region and PB is the probability that secondary electrons are injected back into the gate. A graded N doping region below the emitter favours hole injection at the edge of the channel as described in detail in Section 3. The equivalent pnp bipolar transistor consisting of the pþ hole emitter, the drain junction and the p-type substrate is also sketched.
ðEMÞ Ih ðEMÞ ðEMÞ Ih þ Irec
ð4Þ
Using Eqs. (2)–(4) the emitter current can be rewritten as ðEMÞ IEM ¼ Ih =hFB and we readily see that IB is the largest current of the device if Mp > h1 FB whereas IEM becomes larger than IB otherwise. Furthermore, if we indicate with PB an overall injection probability for electrons generated in the depletion region, as schematically illustrated in Fig. 1, the gate current can be written as: ðEMÞ
IG ¼ PB ðMp 1ÞIh
ð5Þ
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so that, assuming that IB is the largest current of the device (i.e. Mp > h1 FB ), we can finally express the injection efficiency of the BipFlash as: IG Mp 1 : ð6Þ g ¼ ¼ PB IB Mp It is apparent from Eq. (6) that the injection efficiency is independent of the BJT current gain as long as Mp > h1 FB and that, furthermore, IG =IB increases weakly with Mp when this latter is larger than approximately 1.2. In this case only a modest advantage is obtained by operating the cell at much larger multiplication levels. If hFB is so low that Mp < h1 FB , instead, IEM is the largest current in the device and the efficiency becomes: IG ¼ PB ðMp 1ÞhFB : g¼ IEM
ð7Þ
In the above analysis we have used simple parameters (Mp and PB ) to concisely refer to the multiplication factor of holes in the depletion region and to the injection probability of generated electrons. Note, however, that in general PB is different from the electron injection probability in substrate hot-electron injection experiments [5,6], because both the electron generation rate (due to hole impact ionization) and the electric fields accelerating electrons back toward the interface are spacially non-uniform and part of generated electrons can be simply swept into the drain without contributing to the gate current. Therefore, a realistic calculation of the gate current, hence injection efficiency, demands 2D numerical simulations of both electron and hole transport. Monte Carlo simulations dealing with the above problem will be presented in Section 4 while some issues concerning the design of the cell are first discussed in Section 3.
3. Issues in the design of the BipFlash cell In order to validate the operation of the BipFlash we first performed extensive drift–diffusion simulations to describe the hole emission from the pþ region (Fig. 1). For our calculations we always considered the equivalent transistor of the cell (i.e. the transistor that would be obtained if the floating-gate were directly accessible). The simulated device structure is compatible with the design constraints of a 0.25 lm flash technology and the numerical values of the main technological parameters are indicated in Fig. 2. As can be readily seen from Eq. (5), the fraction of the emitter current that is useful for hot-electron injection is ðEMÞ Ih and, furthermore, the flux of holes must be mostly directed toward the depletion region below the channel of the cell to become effective for the cell programming. ðEMÞ In order to increase the useful fraction of Ih it is ad-
Fig. 2. Sketch of the equivalent transistor used for the simulations of the BipFlash cell and numerical values of the technological parameters. Tox is the tunnel oxide thickness (between floating-gate and silicon), xjnþ , xjn and xjpþ are the depths of the nþ , n and pþ diffusion, respectively, and Lmet is the metallurgical channel length.
vantageous to introduce an n diffusion, as illustrated in Figs. 1 and 2, that is able to increase the hole current density directed toward the channel with respect to the current density toward the nþ portion of the drain. Fig. 3(b) reports the simulated integral of the emitter hole current density (normalized to IEM ) along a curved perimeter of the emitter junction as indicated in Fig. 3(a). These simulations account for the variations of the intrinsic carrier concentration in the pþ , n and nþ regions due to the effective band-gap narrowing [23–25]. A large fraction (>80%) of IEM is injected in the pþ /n portion of the emitter junction (hence toward the channel) if the n doping concentration is an order of magnitude lower than the nþ one. These results confirm the effectiveness of the doping gradient in enhancing lateral hole injection. We also verified that, according to simulations, the decrease of drain doping in the n region does not cause an excessive increase of the series resistance, hence degradation of the read current. Leakage across the pþ /nþ part of the emitter junction is not necessarily a problem because the cell can be operated avoiding reverse bias conditions on this junction. Another possible issue in the design of the BipFlash is that a parasitic p-MOS transistor is formed by the n region when this latter is fully overlapped by the gate as illustrated in Fig. 4(a). If VD is large enough with respect to VFG then the parasitic p-MOSFET can turn on and short-circuit the BJT transistor. In order to prevent the p-MOSFET from turning on it is sufficient that the pþ emitter does not reach the thin oxide region diffusing below the spacer. In fact, whenever the n is not fully overlapped by the gate then the p-MOSFET cannot be turned on. This is readily confirmed by the numerical simulations in Fig. 4(b) showing the onset of the
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Fig. 3. (a) Curve around the emitter used for hole current density calculations. (b) Simulated integral of the hole current density (normalized to the total IEM ) along the emitter perimeter for different values of the peak doping concentration of the N extension. The peak concentration of the N extension is approximately 7 1018 cm3 . A large fraction (>80%) of IEM is injected in the pþ /n portion of the emitter junction.
parasitic current when the n is fully overlapped and its complete suppression when the n is not fully overlapped. In the latter case the length of the n extension which is not overlapped by the gate is slightly shorter than 0.1 lm. The introduction of the n extension and the constraint to avoid a complete overlap between the floatinggate and the n region finally explain the structure of the cell proposed in Fig. 1.
4. Numerical simulations of the injection efficiency The gate current characteristics and injection efficiency of the BipFlash have been numerically calculated
Fig. 4. (a) Sketch showing the parasitic p-MOSFET when the N extension is fully overlapped by the floating-gate. (b) Emitter current IEM versus the floating-gate voltage for a given VD . When no overlap is present the parasitic conduction is fully suppressed whereas IEM increases at low VFG for the fully overlapped N extension because of the parasitic p-MOSFET. In the non-fully overlapped case the length of the N extension which is not overlapped by the gate is slightly shorter than 0.1 lm.
using a full-band Monte Carlo simulator extensively described in previous papers [26]. The impact-ionization scattering rates have been validated both on MOS and BJT transistors [27], the high-energy electron transport and oxide injection models have been calibrated in [6] and a quantitatively adequate description of the CHISEL mechanism is documented in [20]. In order to achieve an efficient simulation procedure a current boundary condition is imposed during Monte Carlo simulations where holes are injected along the perimeter of the pþ emitter according to the hole current density profile obtained by drift–diffusion simulations
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(see Fig. 3). Then a complete simulation including both holes and electrons generated by impact ionization is performed. The impact ionization of both holes and electrons is considered for the calculation of the overall substrate current IB whereas those electrons that are accelerated back toward the interface and eventually injected through the oxide contribute to the gate current IG . Fig. 5(a) illustrates typical results for the electron generation rates due to hole impact ionization within the
Fig. 6. BipFlash injection efficiency IG /IB versus VD ¼ VS and jVB j. For a given VFG > VD , IG /IB is essentially a function of VDB ¼ VD VB as confirmed by the two curves at jVB j ¼ 0 and 2.0 V.
Fig. 5. (a) Simulated electron generation rate Ge (cm3 s1 ) due to hole impact ionization in the BipFlash cell. The drain junction (i.e. the junction between p-type channel and N extension) is at X ¼ 0:58 lm. The Si–SiO2 interface is at y ¼ 0. VD ¼ 3 V, jVB j ¼ 2 V, VFG ¼ 5 V. (b) Gate current density at the Si–SiO2 interface for two possible programming bias conditions with either VB ¼ 0 V or jVB j ¼ 2 V.
depletion region of the cell. The maximum of the generation rate takes place relatively close to the drain-bulk junction and Fig. 5(b) shows that the maximum density of the gate current is injected at the Si–SiO2 right above the region of electron generation. In the simulated device the condition Mp > h1 FB is always verified so that in the following of the paper the injection efficiency of the BipFlash is always calculated according to Eq. (6) as IG /IB . Fig. 6 illustrates the BipFlash efficiency versus the drain voltage (that is equal to the source voltage) and for two different substrate voltages. As can be seen, a large efficiency (approximately 5 104 ) with respect to conventional CHE can be achieved with VD ’ 3:3 V even with no substrate bias. Furthermore, when a jVB j ¼ 2 V is used a very remarkable IG =IB ’ 3 103 is predicted by simulations. It is worth noting that in the programming mechanism employed by the BipFlash the most important bias governing the injection efficiency is the drain to substrate voltage (VDB ), provided VFG is large enough to induce strong inversion in the channel, and in fact Fig. 6 shows that approximately the same IG /IB value is obtained either for VD ¼ 1:5 V and jVB j ¼ 2 V or for VD ¼ 3:5 V and jVB j ¼ 0 V that give the same VDB ¼ 3:5 V. Fig. 7 reports IG /IB versus the floating-gate voltage and shows how, for given values of VD ¼ VS and VB , hotelectron injection can be suppressed by reducing VFG . The IG /IB drop at low VFG can be explained as follows. If VFG becomes smaller than VD þ VT , where VT is the threshold voltage possibly increased by the body-effect when VD > VB , then the potential at the Si–SiO2 interface starts decreasing thus reducing the total bulk-to-interface voltage drop that is crucial for electron injection. At this regard, we can also add that a larger available
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As for the values of gate current that can be obtained by the BipFlash, it is apparent from Eqs. (2), (3) and (5) that both IG and IB are simply proportional to IEM in any IEM range where hFB is fairly constant and the hole current density does not significantly change the electric field configuration so that Mp and PB are also approximately constant. This fact is confirmed by the results of Fig. 8 showing the IG versus IB curve that is obtained by changing the emitter current for given VFG , VD and VB values. As can be seen IG is essentially proportional to IB so that, for a fixed injection efficiency, IG can be easily varied to achieve different programming speeds. 5. Calculation of the programming characteristics
Fig. 7. BipFlash injection efficiency, IG /IB , as a function of floating gate voltage VFG . The IG decrease at low VFG demonstrates the possibility to suppress injection in unselected cells by enforcing a low VFG value through the control-gate bias (i.e. the word-line voltage).
voltage budget is provided by applying a negative VB and this explains why in Fig. 7 the IG /IB drop with decreasing VFG is stronger for the two curves having VB ¼ 0 V. Furthermore, when VFG becomes lower than VD , then the oxide field is reversed close to source and drain junctions thus suppressing the electron injection (at least in the periphery of the channel) because of an increased energy barrier. The IG suppression at low VFG is an essential feature for a memory cell in order to inhibit programming of unselected cells connected to a given bit-line by grounding the corresponding ‘wordline’.
Once the IG versus VFG characteristics have been obtained using Monte Carlo simulations, the corresponding programming characteristics can also be simulated as follows. During a programming operation where VCG , VD and VB are constant and the emitter current IEM is also fixed, the equation governing the floating-gate voltage transient is given by [28,29]: dVFG IG ½VFG ðtÞ ¼ aCG ; Cpp dt
ð8Þ
where Cpp is the inter-poly capacitance and aCG is the control to floating-gate capacitive coupling ratio [30]. Eq. (8) is a differential equation that can be solved for using the Runge–Kutta method [31] with an initial value for the floating-gate voltage: VFG0 ¼ VT-FG þ aCG ðVCG VT0 Þ þ aD VD þ aS VS :
ð9Þ
In Eq. (9) VT-FG is the threshold voltage at the floating-gate, aD (aS ) is the control-gate to drain (source) coupling ratio and, if we denote with QFG0 the initial value of the floating-gate charge (QFG0 ¼ 0 for a neutral floating-gate), then the initial threshold voltage is VT0 ¼ VT-FG =aCG QFG0 =Cpp . The solution of Eq. (8) readily provides also the time dependent gate current IG [VFG (t)]. Then the threshold voltage can be calculated as: QFG ðtÞ Cpp Z t 1 ¼ VT0 þ IG ½VFG ðgÞ dg: Cpp 0
VT ðtÞ ¼ VT0
Fig. 8. BipFlash gate current versus substrate current. IG is approximately proportional to IB . A relatively large range of IG values can be obtained for a given efficiency (g ’ 103 in this figure).
ð10Þ
Figs. 9 and 10 show the VT versus time evolution for different programming conditions where the values used for parameters aCG , aD , aS and Cpp are reported in the figure captions and are realistic for the device structure used for simulations [4]. With VD ¼ 3:0 V, jVB j ¼ 2:0 V and IB ¼ 10 lA, the BipFlash can achieve a 4-V shift of VT in only 300 ns (high speed programming––Fig. 9) while the same VT shift can be obtained with VD ¼ 3:3
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achieve different tradeoffs between programming time and power consumption. This flexibility in the programming conditions is an advantageous feature of the BipFlash that is inherently related to its hot-electron programming mechanism. 6. Array organization and biasing scheme
Fig. 9. High-speed programming characteristics of the BipFlash for VD ¼ 3:0 V and jVB j ¼ 2:0 V. aCG ¼ 0:6, aD ¼ 0:1, Cpp ¼ 1 fF.
In order to maintain at the array level the low power dissipation characteristics of the BipFlash and to achieve a selective programming, it is mandatory that no other emitters than those of the cells being programmed is forward biased during the program operation. This result is easily accomplished by providing separate bit-lines for the source and drain, running the pþ emitter lines parallel to the word-lines and keeping the emitter junction of the unselected cells at equilibrium by biasing the un-selected bit-lines at the emitter potential. Fig. 11 presents a possible array organization and a biasing scheme for the programming operation that fulfill these requirements. The pþ emitter lines can be fabricated in metal 1 and run horizontally across the array on top of the control
Fig. 10. Low-voltage programming characteristics of the BipFlash for VD ¼ 3:3 V and VB ¼ 0 V. aCG ¼ 0:6, aD ¼ 0:1, Cpp ¼ 1 fF.
but no substrate bias in approximately 2 ls (Fig. 10). The results of Fig. 10 are particularly promising in the viewpoint of an elimination of charge pumping circuits in embedded memory applications to be used in 3.3 V single supply systems. In the above programming characteristics we deliberately used an IB ¼ 10 lA value which is much smaller than typical drain currents absorbed during channel hotelectron programming in conventional stacked-gate flash cells. Since Fig. 8 demonstrates that IG is proportional to IB (through IEM ) in a relatively large IB range, then the programming time is approximately inversely proportional to the maximum current absorption (IB ) so that the emitter current IEM represents a useful knob to
Fig. 11. Schematic drawing of a possible array organization for the BipFlash. emitter and word-lines run in the horizontal direction whereas each column has both independent bit and source lines that run in the vertical direction. A possible bias scheme for the Array during the program operation is also indicated in the Table.
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gate word-lines whereas two separate metal 2 bit-lines (main source and bit-lines) can run in the vertical direction. A preliminary study of the cell layout indicates that the implementation of an optimized BipFlash results in a cell size that is approximately six times larger than a standard stacked-gate flash cell in a NOR array. This area penalty is not so severe and makes the BipFlash a promising device especially for embedded applications in very low power systems. 7. Conclusions We demonstrated a new NVM cell concept, BipFlash, suitable to attain efficient carrier injection in the floating gate at low voltage. Numerical simulations suggest that properly optimized BipFlash cells could attain an injection efficiency up to two orders of magnitude higher than a conventional stacked-gate flash cell in a NOR array that is programmed by CHEs. The cell size, although larger than that of the conventional stacked-gate cell, is expected to be still adequate for embedded applications especially where low density but very low voltage, low power consumption are required. Two independent quantities, the pþ emitter current and the drain to substrate voltage, can be separately adjusted to attain the desired performance in terms of programming speed and power consumption. These features of the BipFlash cell open a wide range of possibilities to tailor its programming characteristics to the needs of specific applications. In particular, simulations suggest that it might be possible to program the cell with adequate speed while driving the main programming current directly from a 3.3-V power supply line, thus eliminating the need for the area consuming charge pumping circuits. As a result, the BipFlash appears to be an extremely promising approach to scale floating-gate NVM cells towards significantly lower operating voltages than those currently in use.
Acknowledgements The authors would like to thank P. Palestri (DIEGM, University of Udine) for support with Monte Carlo simulations and P. Cappelletti (ST Microelectronics, Italy) for helpful discussions.
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