- Email: [email protected]
A new SIMPLORER model for single-electron transistors
ARTICLE IN PRESS
Microelectronics Journal 38 (2007) 894–899 www.elsevier.com/locate/mejo
A new SIMPLORER model for single-electron transistors A. Boubakera,, Na. Sghaierb,c, M. Troudia, A. Kalboussia, N. Babouxc, A. Souific a
Laboratoire de Microe´lectronique et Instrumentation (UR/03/13-04), Faculte´ des Sciences de Monastir, Avenue de l’environnement, 5000 Monastir, Tunisia Equipe composants e´lectroniques, (UR/99/13-22), Institut Pre´paratoire aux Etudes d’Inge´nieurs de Nabeu l (IPE IN), 8000 Merazka, Nabeul, Tunisia c Institut de Nanotechnologies de Lyon (site INSA), Institut National des Sciences Applique´es de Lyon, Baˆt. Blaise Pascal, 7 Avenue Jean Capelle, 69621 Villeurbanne, Cedex, France
b
Received 19 April 2007; accepted 3 June 2007 Available online 9 August 2007
Abstract In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I–V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog–digital converter. r 2007 Elsevier Ltd. All rights reserved. Keywords: Single-electron transistor; Coulomb blockade oscillations; Quantum effects; Orthodox theory; SIMPLORER
1. Introduction Single-electron transistors (SETs) hold great promise for future nanoelectronic circuits due to their small size, low power consumption, and ability to perform fast and sensitive charge measurements [1]. SET is a highly charge-sensitive device, capable of detecting charges far less than that of one electron. This remarkable property makes SET a very useful tool in experiments where very high charge sensitivity is required. They are increasingly being used and proposed as measurement devices for quantum systems, including quantum computers and quantum dot, cellular automata, and as logic elements in their own right as replacements for MOSFETs. An SET consists of two small tunnel junctions and an ‘‘island’’ between them, usually with a third gate electrode capacitively coupled to the island [2]. When the island of the SET is metallic (usually Al), it contains billions of electrons. The current between the source and drain contacts can be controlled through the gate Corresponding author. Tel.: +216 98226408; fax: +216 72220181.
E-mail address: [email protected] (A. Boubaker). 0026-2692/$ - see front matter r 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2007.06.004
contact, making it possible to use the transistor as an amplifier; a small change in the gate signal induces a large change in the source-drain current [3]. The functioning of the SET is based on the Coulomb blockade theory, which is a direct consequence of the discreteness of the electron charge. When an electron is added to the metallic island, this will create a difference in charge between the island and its environment, meaning that the capacitance between the island and the environment will be charged with a charge e. In what follows, we assume that the following two conditions are satisfied. First, we assume the island is small enough and the temperature is low enough that the Coulomb energy corresponds to one excess electron Ec is large compared to the ambient thermal energy KB T. Second, we assume the lifetime due to tunnelling t ¼ Rt.C is much larger than the uncertainty time Dth/ 2Ec associated with the Coulomb energy Ec. In this paper, we present simulations of typical SET characteristics (I–V and energy charge curves). The original point of our work consists in the proposition of a new SET model. In this model, we propose a new bloc developed using SIMPLORER to modulate quantum effect in the SET island.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
2. Set simulations 2.1. The orthodox theory The orthodox theory of single electronics is a model describing the basic physics of single-electron devices based on the free (electrostatic) energy of the system under consideration. In the orthodox theory, an adequate measure of the strength of this effect is the ‘‘charging’’ energy Ec ¼ e2/C, where C is the capacitance of the island. The orthodox theory, now, makes the following three major assumptions [4]:
The electron energy quantization inside the conducting island is ignored. The time tt of electron tunnelling through the barrier is assumed to be negligibly small, that is, tt ¼ 0 in computations. Cotunnelling is ignored.
The tunnelling of a single electron is always a random event, with a certain rate G (i.e., probability per unit time), which depends on the reduction of the free (electrostatic) energy DF of the system as a result of a tunnel event, the tunnel resistance Rt, and the temperature. If there is no reduction of free energy possible as a result of a tunnel event, the system is in Coulomb blockade. In general, this reduction of the free energy is defined as the reduction of the energy stored on the junction capacitances minus the energy delivered by the source during a tunnel event. From this definition of the free energy we find that during tunnelling of a single electron, in case of a SET junction excited by an ideal voltage source with the value us, the energy delivered by the source is e us, the change in energy stored on the junction capacitance is zero (the charge on the junction capacitance is fixed), and thus: DF ¼ e us. In addition, in the case of a SET junction excited by an ideal current source, is, the energy delivered by the source, is zero due to the assumed zero time of electron tunnelling. The change in the stored energy on the junction capacitance is also zero (the charge on the junction capacitance changes from e/2 to e/2), and thus DF ¼ 0. If we consider both sources as special cases of nonlinear resistors, then the different treatment of the sources already indicate that including resistors in the orthodox theory will be difficult, if not impossible. In most papers on the orthodox theory, where resistors are included, they are included by considering either a low impedance environment R5RK, or a high impedance environment RcRK (RK ¼ h e2). Electron transport within nanoelectronic devices can best be described by quantum mechanics; nanoelectronic circuits can best be described by Kirchhoff voltage and current laws, which have a firm basis in classical physics. This creates an area of tension. As quantum mechanics is described in terms of energy, it seems an obvious starting
895
point to describe the behaviour of SET devices and SET circuits using energy considerations. This is what the orthodox theory does. A circuit theory based on free energies, however, does not exist and a circuit theory based on energy differences is not obvious because the Kirchhoff laws ensure energy conservation in circuits; any energy dissipated in the circuit is delivered to it by sources [5]. The tunnel current for single electrons through the junction is (Fig. 1) I¼
DQ ¼ e¯ G, Dt
(1)
where G is the tunnelling rate and DQ is the differences in charge [6]. The Ohm law is U ¼ Rt I ¼ e¯ Rt G; G¼
(2)
Dz . e¯ 2 Rt
(3)
The rate of tunnelling events is given by the orthodox theory G¼
e2 Rt
DW , 1 exp DW =KT
(4)
! e DW ¼ e U c , 2C P
(5)
where DW is the drop of electrostatic energy, K is the Boltzmann constant and CS is the total capacitance. Because current conservation I(V) can be calculated on any junction according to the following equation: ! þ1 X ~ IðV Þ ¼ e pn G1ðnÞ G 1ðnÞ n¼1 þ1 X
¼e
! pn ~ G2ðnÞ G 2ðnÞ ,
ð6Þ
n¼1
where is pn ¼ p 0
n1 Y Gmþ1;m m¼0
Gm;mþ1
,
(7)
→
→
Γ1
Γ2
C1
C2
Q
J1
J2 Γ1
Cg
Γ2
I
VD Vg
Fig. 1. SET equivalent circuit using the orthodox theory.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
896
Gk,I is the rate for a transition from the state K to state I, and ~ Gi and ~ Gi are the electron tunnelling rates. 2.2. Maple simulations 2.2.1. Ids–Vds characteristics In this section, we present I–V characteristics after using the theory, and they we get for expression Ids current. The following equations are inspired from Fig. 2. The tunnelling rates and state probabilities can then be used to calculate the total current through the junction according to [8]: X I ¼e pn ðGn1;n Gnþ1;n Þ, (8) n Gln;nþ1 þGln;nþ1 GS
pn ¼ pnþ1 ¼ GS ¼
Glnþ1;n
þ
9 > > =
;
1 pn ; r Gnþ1;n Gln;nþ1
þ
(9)
>
> Grn;nþ1 ; ;
Fig. 3. Simulated Ids–Vds characteristics of the SET using Maple.
and with Eq. (8) the source–drain current amounts to I ds;n ¼ e
Glnþ1;n Grn;nþ1 Grnþ1;n Grn;nþ1 . GS
(10)
In the limit of identical tunnel junctions (i.e. Rl ¼ Rr ¼ Rt ¼ 1 MO and Cl ¼ C2 ¼ Cr ¼ 1 aF, zero temperature and with the sum of the junction resistances, RSom ¼ Rl+ Rr) the current equation is reduces to ! CgV g 1 4e2 1 2 n I ds;n ðV g ; V ds Þ ¼ V ds 2 . 2RSom 2 e C S V ds (11) Using Maple simulator, we get the corresponding Fig. 3. Fig. 3 shows the source–drain I–V at 0 K at different values of Vg (Vg ¼ 0, 0.5, 1 V). Comparing the Ids–Vds characteristic at Vg ¼ 0.5, 1 V, we remark that the current suppression region increases, respectively, from Vds ¼ 0.6 to 1.314 V. Fig. 4 shows the source-gate I–V at 0 K at different values of Vds (Vds ¼ 0.5, 1, 1.5, 2 V). From these results we have normalized the Ids current for the SET circuit. The normalized characteristic is presented in Fig. 5. If we apply a fixed bias voltage, and C1, R1
SET island
Fig. 4. Simulated Ids–Vgs characteristics of the SET using Maple.
Cr, Rr
source
drain
½ Vds
-½ Vds gate Vg
Fig. 2. Detailed SET equivalent circuit.
Fig. 5. Typical simulated Coulomb oscillations.
change the offset charge on the island by sweeping the gate voltage Vg monotonically, periodic current peaks corresponding to the island charge moves from one stable
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
897
region to another will be observed. This phenomena gives rise to the well-known ‘‘Coulomb blockade oscillations’’ as illustrated in Fig. 5. 2.3. Charge energy characteristic The charging energy of a SET is formulated as (12) [7]: E ch ¼
ðni e C g V g ðC 1 C r ÞV ds =2Þ eV ds ðn1 nr Þ, þ 2C S 2 (12)
where CS ¼ Cl+Cg+Cr is the total capacitance of the island. Some special cases of last equation already reveal typical characteristics of SETs. For Vds ¼ 0 and under consideration of symmetrical junctions (Cl ¼ Cr), zero gate bias and, on average, zero occupation of the island (ni ¼ 0), the charging energy [8] ðni e C g V g Þ2 CgV g 2 ¼ E C ni . (13) E ch ðn; V g Þ ¼ 2C S e Fig. 6a, plotted with Maple simulator, shows the electrostatic energies for different island occupations n as a function of gate voltage are parabolae, with adjacent parabolae (e.g. n and n+1) intersecting at CgVg/e ¼ n+1/2. Hence, it is energetically favourable for the island occupation to change by one with a period of DVg ¼ e/ Cg, as shown schematically in Fig. 6b.
Fig. 7. Application of the superposition theorem to propose a new SET model without quantum effects consideration.
Fig. 6. Simulation of typical output SET characteristics: (a) charge energy curve and (b) energies levels staircase of the SET.
ARTICLE IN PRESS 898
A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
3. Schematic set modelling 3.1. Electrical modelling of set without quantum effects If we neglect the quantum effect in the SET, we obtain this electrical model based on the superposition theorem as shown in Fig. 7. Our idea consists on the determination, in the first part, the current Ids1 (for Vg ¼ 0 V) coming from the Vd and, in
the second part, the current Ids2 (for Vd ¼ 0 V) coming from the gate. So, the total current is the addition of Ids1 and Ids2. Using Laplace transformer, we replace the SET elements with their transfer functions. After that, we apply the superposition theorem and we determine the temporal current I ds ðtÞ ¼ I ds1 ðtÞ þ I ds2 ðtÞ. The Ids–Vds characteristic is the straight line, which passes from the axis origin (see Fig. 8). Unfortunately, this model is clearly insufficient to explain quantum effects on the SET. For this reason, we propose a new bloc to modulate the island in the SET. 3.2. Electrical model of set with quantum effects
Fig. 8. Simulated Ids–Vds characteristics of the SET without considering quantum effects.
In this section, we present a new bloc that takes account of quantum effects considered in the SET island. This proposition introduces a direct impact in the output characteristic of SET. Results obtained with our suggestion show a strong correlation with experimental curves described elsewhere in the literature [9,10]. The idea of this bloc is to introduce an I–V characteristic which has a staircase form. To reach that we, use in the X channel the ‘‘4 bits analog–digital converter (ADC)’’ alimented with a specified periodic triangular signal, which converts the analog signal to the digital one using 241 amplifiers and 24 resistors. ‘‘ADC’’ compares the input value signal with the reference voltage in every edge of
Fig. 9. The new SIMPLORER model for SET taking account of quantum effects.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
clock. The outputs bits-values are amplified consecutively with 1, 2, 3 and 4. The X channel output is achieved summing these values. The Y channel may be a ramp obtained from a triangular signal because in SIMPLORER it is impossible to implement the ramp directly. A SIMPLORER model is shown in Fig. 9. 4. Conclusion Nanoelectronic is, relatively, a new area of research where many breakthroughs still lie ahead. Following results of simulation, we showed an I–V characteristic using an orthodox theory of single electronics. Besides, we illustrated the coulomb blockade oscillations. In addition, we showed an electrical modelling of SET without considering the quantum effects. To put in value the last effect, a description of a new SIMPLORER model to simulate an island of SET circuit with quantum effect, is proposed.
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References [1] M.H. Devoret, R.J. Schoelkopf, Nature 406 (2000) 1039. [2] Shih, PatrioChiu, An overview of nanoelectronic devices with emphasis on the single-electron transistor, 2004. [3] S. Gustavsson, Properties of structures with parallel coupled single electron transistors. [4] B.L. Altshuler, P.A. Lee, R.A. Webb (Eds.), Mesoscopic Phenomena in Solids, Elsevier, Amsterdam, 1991. [5] J. Hoekstra, in: Proceedings of European Conference on Circuit Theory and Design, ECCTD, Poland, 2003. [6] J. Gautier, Single Electronics, Vietnam School of Physics, 2005. [7] R. Brenner, Single electron transistors for detection of charge motion in the on solid state, Thesis, The University of New South Wales, 2004. [8] Scho¨n, Single-electron tunneling, in: Quantum Transport and Dissipation, Dittrich, T., et al. (Eds.), Wiley-VCH, Weinheim, Germany, 1998. [9] J. See, The´orie du blocage du coulomb applique´e aux nanostructures semiconductrices: modelisations des dispositifs a` nanocristaux de silicium,’’ Thesis, Universite´ Paris Xi Ufr Scientifique D’orsay, 2003. [10] F. Fuso, Coulomb blockade and single electron devices, topics in anotechnology–part 5, Scuola di Dottorato in Fisica Applicata ‘‘G. Galilei,’’ 2005.
Microelectronics Journal 38 (2007) 894–899 www.elsevier.com/locate/mejo
A new SIMPLORER model for single-electron transistors A. Boubakera,, Na. Sghaierb,c, M. Troudia, A. Kalboussia, N. Babouxc, A. Souific a
Laboratoire de Microe´lectronique et Instrumentation (UR/03/13-04), Faculte´ des Sciences de Monastir, Avenue de l’environnement, 5000 Monastir, Tunisia Equipe composants e´lectroniques, (UR/99/13-22), Institut Pre´paratoire aux Etudes d’Inge´nieurs de Nabeu l (IPE IN), 8000 Merazka, Nabeul, Tunisia c Institut de Nanotechnologies de Lyon (site INSA), Institut National des Sciences Applique´es de Lyon, Baˆt. Blaise Pascal, 7 Avenue Jean Capelle, 69621 Villeurbanne, Cedex, France
b
Received 19 April 2007; accepted 3 June 2007 Available online 9 August 2007
Abstract In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I–V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog–digital converter. r 2007 Elsevier Ltd. All rights reserved. Keywords: Single-electron transistor; Coulomb blockade oscillations; Quantum effects; Orthodox theory; SIMPLORER
1. Introduction Single-electron transistors (SETs) hold great promise for future nanoelectronic circuits due to their small size, low power consumption, and ability to perform fast and sensitive charge measurements [1]. SET is a highly charge-sensitive device, capable of detecting charges far less than that of one electron. This remarkable property makes SET a very useful tool in experiments where very high charge sensitivity is required. They are increasingly being used and proposed as measurement devices for quantum systems, including quantum computers and quantum dot, cellular automata, and as logic elements in their own right as replacements for MOSFETs. An SET consists of two small tunnel junctions and an ‘‘island’’ between them, usually with a third gate electrode capacitively coupled to the island [2]. When the island of the SET is metallic (usually Al), it contains billions of electrons. The current between the source and drain contacts can be controlled through the gate Corresponding author. Tel.: +216 98226408; fax: +216 72220181.
E-mail address: [email protected] (A. Boubaker). 0026-2692/$ - see front matter r 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2007.06.004
contact, making it possible to use the transistor as an amplifier; a small change in the gate signal induces a large change in the source-drain current [3]. The functioning of the SET is based on the Coulomb blockade theory, which is a direct consequence of the discreteness of the electron charge. When an electron is added to the metallic island, this will create a difference in charge between the island and its environment, meaning that the capacitance between the island and the environment will be charged with a charge e. In what follows, we assume that the following two conditions are satisfied. First, we assume the island is small enough and the temperature is low enough that the Coulomb energy corresponds to one excess electron Ec is large compared to the ambient thermal energy KB T. Second, we assume the lifetime due to tunnelling t ¼ Rt.C is much larger than the uncertainty time Dth/ 2Ec associated with the Coulomb energy Ec. In this paper, we present simulations of typical SET characteristics (I–V and energy charge curves). The original point of our work consists in the proposition of a new SET model. In this model, we propose a new bloc developed using SIMPLORER to modulate quantum effect in the SET island.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
2. Set simulations 2.1. The orthodox theory The orthodox theory of single electronics is a model describing the basic physics of single-electron devices based on the free (electrostatic) energy of the system under consideration. In the orthodox theory, an adequate measure of the strength of this effect is the ‘‘charging’’ energy Ec ¼ e2/C, where C is the capacitance of the island. The orthodox theory, now, makes the following three major assumptions [4]:
The electron energy quantization inside the conducting island is ignored. The time tt of electron tunnelling through the barrier is assumed to be negligibly small, that is, tt ¼ 0 in computations. Cotunnelling is ignored.
The tunnelling of a single electron is always a random event, with a certain rate G (i.e., probability per unit time), which depends on the reduction of the free (electrostatic) energy DF of the system as a result of a tunnel event, the tunnel resistance Rt, and the temperature. If there is no reduction of free energy possible as a result of a tunnel event, the system is in Coulomb blockade. In general, this reduction of the free energy is defined as the reduction of the energy stored on the junction capacitances minus the energy delivered by the source during a tunnel event. From this definition of the free energy we find that during tunnelling of a single electron, in case of a SET junction excited by an ideal voltage source with the value us, the energy delivered by the source is e us, the change in energy stored on the junction capacitance is zero (the charge on the junction capacitance is fixed), and thus: DF ¼ e us. In addition, in the case of a SET junction excited by an ideal current source, is, the energy delivered by the source, is zero due to the assumed zero time of electron tunnelling. The change in the stored energy on the junction capacitance is also zero (the charge on the junction capacitance changes from e/2 to e/2), and thus DF ¼ 0. If we consider both sources as special cases of nonlinear resistors, then the different treatment of the sources already indicate that including resistors in the orthodox theory will be difficult, if not impossible. In most papers on the orthodox theory, where resistors are included, they are included by considering either a low impedance environment R5RK, or a high impedance environment RcRK (RK ¼ h e2). Electron transport within nanoelectronic devices can best be described by quantum mechanics; nanoelectronic circuits can best be described by Kirchhoff voltage and current laws, which have a firm basis in classical physics. This creates an area of tension. As quantum mechanics is described in terms of energy, it seems an obvious starting
895
point to describe the behaviour of SET devices and SET circuits using energy considerations. This is what the orthodox theory does. A circuit theory based on free energies, however, does not exist and a circuit theory based on energy differences is not obvious because the Kirchhoff laws ensure energy conservation in circuits; any energy dissipated in the circuit is delivered to it by sources [5]. The tunnel current for single electrons through the junction is (Fig. 1) I¼
DQ ¼ e¯ G, Dt
(1)
where G is the tunnelling rate and DQ is the differences in charge [6]. The Ohm law is U ¼ Rt I ¼ e¯ Rt G; G¼
(2)
Dz . e¯ 2 Rt
(3)
The rate of tunnelling events is given by the orthodox theory G¼
e2 Rt
DW , 1 exp DW =KT
(4)
! e DW ¼ e U c , 2C P
(5)
where DW is the drop of electrostatic energy, K is the Boltzmann constant and CS is the total capacitance. Because current conservation I(V) can be calculated on any junction according to the following equation: ! þ1 X ~ IðV Þ ¼ e pn G1ðnÞ G 1ðnÞ n¼1 þ1 X
¼e
! pn ~ G2ðnÞ G 2ðnÞ ,
ð6Þ
n¼1
where is pn ¼ p 0
n1 Y Gmþ1;m m¼0
Gm;mþ1
,
(7)
→
→
Γ1
Γ2
C1
C2
Q
J1
J2 Γ1
Cg
Γ2
I
VD Vg
Fig. 1. SET equivalent circuit using the orthodox theory.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
896
Gk,I is the rate for a transition from the state K to state I, and ~ Gi and ~ Gi are the electron tunnelling rates. 2.2. Maple simulations 2.2.1. Ids–Vds characteristics In this section, we present I–V characteristics after using the theory, and they we get for expression Ids current. The following equations are inspired from Fig. 2. The tunnelling rates and state probabilities can then be used to calculate the total current through the junction according to [8]: X I ¼e pn ðGn1;n Gnþ1;n Þ, (8) n Gln;nþ1 þGln;nþ1 GS
pn ¼ pnþ1 ¼ GS ¼
Glnþ1;n
þ
9 > > =
;
1 pn ; r Gnþ1;n Gln;nþ1
þ
(9)
>
> Grn;nþ1 ; ;
Fig. 3. Simulated Ids–Vds characteristics of the SET using Maple.
and with Eq. (8) the source–drain current amounts to I ds;n ¼ e
Glnþ1;n Grn;nþ1 Grnþ1;n Grn;nþ1 . GS
(10)
In the limit of identical tunnel junctions (i.e. Rl ¼ Rr ¼ Rt ¼ 1 MO and Cl ¼ C2 ¼ Cr ¼ 1 aF, zero temperature and with the sum of the junction resistances, RSom ¼ Rl+ Rr) the current equation is reduces to ! CgV g 1 4e2 1 2 n I ds;n ðV g ; V ds Þ ¼ V ds 2 . 2RSom 2 e C S V ds (11) Using Maple simulator, we get the corresponding Fig. 3. Fig. 3 shows the source–drain I–V at 0 K at different values of Vg (Vg ¼ 0, 0.5, 1 V). Comparing the Ids–Vds characteristic at Vg ¼ 0.5, 1 V, we remark that the current suppression region increases, respectively, from Vds ¼ 0.6 to 1.314 V. Fig. 4 shows the source-gate I–V at 0 K at different values of Vds (Vds ¼ 0.5, 1, 1.5, 2 V). From these results we have normalized the Ids current for the SET circuit. The normalized characteristic is presented in Fig. 5. If we apply a fixed bias voltage, and C1, R1
SET island
Fig. 4. Simulated Ids–Vgs characteristics of the SET using Maple.
Cr, Rr
source
drain
½ Vds
-½ Vds gate Vg
Fig. 2. Detailed SET equivalent circuit.
Fig. 5. Typical simulated Coulomb oscillations.
change the offset charge on the island by sweeping the gate voltage Vg monotonically, periodic current peaks corresponding to the island charge moves from one stable
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
897
region to another will be observed. This phenomena gives rise to the well-known ‘‘Coulomb blockade oscillations’’ as illustrated in Fig. 5. 2.3. Charge energy characteristic The charging energy of a SET is formulated as (12) [7]: E ch ¼
ðni e C g V g ðC 1 C r ÞV ds =2Þ eV ds ðn1 nr Þ, þ 2C S 2 (12)
where CS ¼ Cl+Cg+Cr is the total capacitance of the island. Some special cases of last equation already reveal typical characteristics of SETs. For Vds ¼ 0 and under consideration of symmetrical junctions (Cl ¼ Cr), zero gate bias and, on average, zero occupation of the island (ni ¼ 0), the charging energy [8] ðni e C g V g Þ2 CgV g 2 ¼ E C ni . (13) E ch ðn; V g Þ ¼ 2C S e Fig. 6a, plotted with Maple simulator, shows the electrostatic energies for different island occupations n as a function of gate voltage are parabolae, with adjacent parabolae (e.g. n and n+1) intersecting at CgVg/e ¼ n+1/2. Hence, it is energetically favourable for the island occupation to change by one with a period of DVg ¼ e/ Cg, as shown schematically in Fig. 6b.
Fig. 7. Application of the superposition theorem to propose a new SET model without quantum effects consideration.
Fig. 6. Simulation of typical output SET characteristics: (a) charge energy curve and (b) energies levels staircase of the SET.
ARTICLE IN PRESS 898
A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
3. Schematic set modelling 3.1. Electrical modelling of set without quantum effects If we neglect the quantum effect in the SET, we obtain this electrical model based on the superposition theorem as shown in Fig. 7. Our idea consists on the determination, in the first part, the current Ids1 (for Vg ¼ 0 V) coming from the Vd and, in
the second part, the current Ids2 (for Vd ¼ 0 V) coming from the gate. So, the total current is the addition of Ids1 and Ids2. Using Laplace transformer, we replace the SET elements with their transfer functions. After that, we apply the superposition theorem and we determine the temporal current I ds ðtÞ ¼ I ds1 ðtÞ þ I ds2 ðtÞ. The Ids–Vds characteristic is the straight line, which passes from the axis origin (see Fig. 8). Unfortunately, this model is clearly insufficient to explain quantum effects on the SET. For this reason, we propose a new bloc to modulate the island in the SET. 3.2. Electrical model of set with quantum effects
Fig. 8. Simulated Ids–Vds characteristics of the SET without considering quantum effects.
In this section, we present a new bloc that takes account of quantum effects considered in the SET island. This proposition introduces a direct impact in the output characteristic of SET. Results obtained with our suggestion show a strong correlation with experimental curves described elsewhere in the literature [9,10]. The idea of this bloc is to introduce an I–V characteristic which has a staircase form. To reach that we, use in the X channel the ‘‘4 bits analog–digital converter (ADC)’’ alimented with a specified periodic triangular signal, which converts the analog signal to the digital one using 241 amplifiers and 24 resistors. ‘‘ADC’’ compares the input value signal with the reference voltage in every edge of
Fig. 9. The new SIMPLORER model for SET taking account of quantum effects.
ARTICLE IN PRESS A. Boubaker et al. / Microelectronics Journal 38 (2007) 894–899
clock. The outputs bits-values are amplified consecutively with 1, 2, 3 and 4. The X channel output is achieved summing these values. The Y channel may be a ramp obtained from a triangular signal because in SIMPLORER it is impossible to implement the ramp directly. A SIMPLORER model is shown in Fig. 9. 4. Conclusion Nanoelectronic is, relatively, a new area of research where many breakthroughs still lie ahead. Following results of simulation, we showed an I–V characteristic using an orthodox theory of single electronics. Besides, we illustrated the coulomb blockade oscillations. In addition, we showed an electrical modelling of SET without considering the quantum effects. To put in value the last effect, a description of a new SIMPLORER model to simulate an island of SET circuit with quantum effect, is proposed.
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