RF applications

Journal Pre-proofs Regular paper A New Trench Double Gate Junctionless FET: A Device for Switching and Analog/RF Applications Aanchal Garg, Balraj Singh, Yashvir Singh PII: DOI: Reference:

S1434-8411(19)32674-3 https://doi.org/10.1016/j.aeue.2020.153140 AEUE 153140

To appear in:

International Journal of Electronics and Communications

Received Date: Accepted Date:

24 October 2019 22 February 2020

Please cite this article as: A. Garg, B. Singh, Y. Singh, A New Trench Double Gate Junctionless FET: A Device for Switching and Analog/RF Applications, International Journal of Electronics and Communications (2020), doi: https://doi.org/10.1016/j.aeue.2020.153140

This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

© 2020 Published by Elsevier GmbH.

A New Trench Double Gate Junctionless FET: A Device for Switching and Analog/RF Applications Aanchal Garg, Balraj Singh∗, Yashvir Singh∗ Department of Electronics and Communication Engineering G. B. Pant Institute of Engineering and Technology, Pauri, Uttarakhand, India

Abstract In this work, a trench double-gate junctionless FET (TDG-JLFET) is proposed for switching and analog/RF applications. In TDG-JLFET, the gates are placed vertically in separate trenches for better control over the channel electrostatics. The performance of proposed structure is assessed using two dimensional (2D) numerical simulations in TCAD tool (ATLAS). At optimized device structural parameters, TDG-JLFET demonstrates subthreshold swing (SS), drain induced barrier lowering (DIBL) and ON-to-OFF current ratio (ION /IOF F ) of 69 mV/dec, 27 mV/V and 3.5× 1013 , respectively. Further, TDG-JLFET exhibits peak transconductance (gm ) of 1478 µS/µm and unity gain cut-off frequency (fT ) of 423 GHz at channel length of 20 nm. Keywords: Junctionless FET, subthreshold swing, drain induced barrier lowering, transconductance, cut-off frequency.

∗

Corresponding author Email address: [email protected] (Balraj Singh)

Preprint submitted to AEU - International Journal of Electronics and CommunicationsFebruary 4, 2020

1. Introduction The junctionless field-effect transistors (JLFETs) allow downscaling of device dimensions in nanometre regime with easier fabrication steps due to absence of any p-n junctions [1–4]. The JLFETs work on the principle of bulk conduction in partial depletion or in flatband mode of operation unlike the surface inversion in bulk MOSFETs [5]. The JLFETs are suitable for digital as well as analog applications due to superior ON-state current, lower drain induced barrier lowering (DIBL), smaller subthreshold swing (SS) and lower surface scattering as compared to undoped bulk MOSFETs [1–3, 5–9]. Moreover, the conduction in JLFETs is due to majority carriers which make them suitable for high frequency applications [3, 5]. Therefore, JLFETs are considered as attractive devices for system-on-chip (SoC) applications [10– 12]. Double-gate JLFETs have drawn the attention of researchers in the last decade because these devices deplete the channel region more effectively and hence provide better performance than the single gate (SG) JLFETs [1]. In the literature, several research efforts have been made to improve subthreshold characteristics of DG-JLFETs [7, 13–18]. Singh et al. [13] reported subthreshold parameters of a dielectric pocket (DP) DG-JLFET. The authors have obtained SS of 68 mV/dec, DIBL of 68 mV/V and ON-to-OFF current ratio (ION /IOF F ) of 8×105 at channel length (LG ) of 20 nm. Subthreshold characteristics of DG-JLFETs with vertical Gaussian profile have been studied by different groups [7, 14, 15]. Kumari et al. [15] obtained ION /IOF F of ∼ 109 , DIBL of ∼ 80 mV/V and SS of 74 mV/dec at LG of 32 nm while Singh et al. [7] achieved ION /IOF F of 1010 and SS of 85 mV/dec at LG of 20 nm. 2

Parihar and Kranti [16] have analysed the variation of doping concentration (Nd ) of a junctionless accumulation mode (JAM) DG-JLFET. They have shown that the SS, ION /IOF F , total capacitance (CGG ) and intrinsic delay of JAM DG-JLFET depends on Nd . Jaiswal and Kranti [17] have studied short channel effects (SCEs) of an underlap DG-JLFET and obtained a DIBL of 40 mV, SS of 65 mV/dec and ION /IOF F of ∼ 1011 at LG of 25 nm. They have also reported the dependence of subthreshold parameters on underlap length and Nd . Kumari et al. [18] have proposed a dual material (DM) DG-JLFET and achieved ION /IOF F of ∼ 108 , SS of 62 mV/dec, DIBL of 22 mV/V. On the other hand, few studies have been reported in the literature on DG-JLFETs which demonstrate their suitability of these devices for analog applications [11, 12, 18, 19]. Ghosh et al. [11] have presented a DG-JLFET for ultra-low power (ULP) analog/RF circuits. This structure provides 200% higher cut-off frequency (fT ), 65% improvement in intrinsic voltage gain (AV ) as compared to DG-MOSFETs. Further, the authors have reported a transconductance (gm ) of 197 µS/µm and fT of 92 GHz at LG of 20 nm. Ghosh and Kranti [19] have analysed the effect of channel doping and spacer length on RF parameters of the JAM DG-JLFET and achieved 15% higher AV and 40-50% enhancement in fT as compared to the conventional DGJLFET. Baruah and Paily [12] have reported a DM DG-JLFET with high-k spacer and reported improvement in gm and AV over single material DGJLFET. In this study, we have proposed a new trench double-gate JLFET (TDGJLFET) structure on SOI for switching and analog/RF applications. The performance of TDG-JLFET is analyzed using 2D TCAD simulations in AT-

3

Figure 1: Schematic view of TDG-JLFET.

LAS [20]. Section II explains the device structure and simulation setup. The results and discussion are presented in section III. Subsequently, conclusion is drawn in section IV. 2. Device Structure and Simulation Setup Fig. 1 shows 2D cross-sectional view of TDG-JLFET on SOI. The gate and drain contacts of the device are symmetrically placed on both sides of the source contact. The gates (work function = 5.2 eV) of the device are placed in separate trenches vertically. The gate oxide thickness is represented by tox . The channel region of TDG-JLFET is extended laterally to get the drain contacts which are placed vertically on both sides. The gate and drain electrodes are separated by a thick oxide (tox1 ). Similarly, thick oxide (tox2 ) at the bottom of gates is taken to isolate the gate electrodes from drain Si region. The values of tox1 and tox2 are large enough to minimize the gate 4

Table 1: Structural parameters of TDG-JLFET used in this study

Parameters

Unit

Values

Channel length (LG )

nm

20-100

Gate Oxide thickness (tox )

nm

1-2

Gate width (tgate )

nm

5

Channel thickness (tg )

nm

10-20

Silicon layer thickness (ts )

nm

10

Extended drain region length (LD )

nm

26

Length of drain electrode (tD )

nm

8

Gate work function (φm )

eV

5.2

BOX thickness (tbox )

nm

500

Channel doping (Nd )

cm−3

1017 - 1019

Oxide between drain and gate (tox1 )

nm

20

Oxide below the gate (tox2 )

nm

10

5

capacitances. The values of channel thickness (tg ) and doping concentration (Nd ) are chosen in such a way that the channel is fully depleted under OFFstate and allow a decent amount of current flow under ON-state. All the device parameters are listed in Table 1. Some of these parameters are varied in order to study their impact on the device performance. Fig 2 shows 3D schematic view of the proposed device for better visualization. The proposed TDG-JLFET structure can be miniaturized by considering drain at one side only. The resulting structure will be of L-shape as reported by Kim et al. [21–23]. For accurate simulation of the proposed device, Fermi-Dirac model is activated to include the effect of high doping concentration. The Lombardi mobility (CVT) model is chosen for concentration and field dependent mobility. Concentration dependent Shockley-Read-Hall and Auger models are invoked for carrier recombination. Using these models, the simulation setup for TDG-JLFET is calibrated with the experimental data of a pre-fabricated device [3] as shown in Fig. 3. 3. Results and Discussion 3.1. Electrostatic Analysis JLFET is a voltage controlled resistor whose resistance depends on the work function difference between the gate electrode and semiconductor. Therefore, a sufficiently large work function of gate metal is required to make the channel fully depleted in OFF-state. In n-channel JLFET, positive gate voltage is applied to make the channel partially depleted or fully neutral [3]. In addition to gate voltage (VGS ), the drain voltage (VDS ) also affects the 6

Figure 2: 3D schematic view of TDG-JLFET

Drain Current, I

DS

(A)

1E-7 1E-8 1E-9

Simulation Experimental

1E-10 1E-11 1E-12 1E-13 0.0

0.1

0.2

0.3

0.4

0.5

Gate Voltage, V

GS

0.6

0.7

(V)

Figure 3: Calibration of simulation models with pre-fabricated non-planar JLFET [3].

7

channel electrostatics [5]. Therefore, the length of drain electrode (tD ) and extended drain region length (LD ) play significant role in determining the potential in the channel region particularly at high VDS . In order to understand the depletion condition of TDG-JLFET, the electric field contours in the channel region of device are shown in Fig. 4 at different values of VGS and VDS . It is observed from Fig. 4(a) that the channel is fully depleted in OFFstate due to the presence of high electric field. Further, the gate electrode also has an effect in the drain region through tox2 . It is to be noted from Fig. 4(b) that at VGS = 1 V, the electric field in the centre of channel and in drain region is reduced to zero which reveals that the channel is partially depleted. Fig. 4(c) illustrates that the electric field in drain region increases with VDS . The channel is partially neutral for VDS = 1 V and VGS = 1 V as observed in Fig. 4(d). It is deduced from Fig. 4 that the device is fully depleted in OFF-state, whereas in ON-state, the carriers flow from source to drain in neutral channel for which there is no electric field perpendicular to carrier flow. For better elucidation of depletion of the channel under OFF and ON conditions, the energy band diagram along the cutline C1 (shown in Fig 4) is plotted in Fig. 5. In OFF-state, the presence of gate electric field causes the energy band bending across the channel thickness. On the other hand, the flat-band condition is achieved in ON-state. In JLFETs, under OFF-state, the electrostatic squeezing [5] effectuates the distance between the non-depleted source and drain regions to be larger than the physical gate length. Therefore, the effective channel length (Lef f ) is always longer than LG , which is an advantage to reduce the SCEs [24, 25]. In order to observe Lef f , the potential contours in the Si region of TDG-

8

S

G

D

G

S

G

D

D

G

D

C

1

V

DS

=0 V

V

GS

V

=0 V

DS

=0 V

V

GS

(a) D

G

S

Electric

=1 V

Field

(b) S

G

D

D

G

(MV/cm) G

D

6 3

C

1

0

V

DS

=1 V

V

GS

=0 V

V

DS

V

=1 V

(c)

GS

=1 V

(d)

Figure 4: Electric field distribution at different values of VGS and VDS .

0.8

Energy (eV)

0.4 0.0 -0.4

18

N = 1x10 d

-0.8

L

CB

V

VB

V

=0 V, V

CB

V

=1 V, V

=1 V

VB

V

=1 V, V

=1 V

DS

=0 V

GS

=0 V, V

DS

=0 V

GS

DS

GS

DS

-3

GS

t

cm

= 1 nm

ox

t = 10 nm

= 20 nm

G

g

-1.2 0

2

4

6

8

10

Distance (nm)

Figure 5: Energy band diagram along cutline C1 at different values of VGS and VDS .

9

Figure 6: Potential contours in TDG-JLFET at (a) VDS = 0 V and VGS = 0 V (b) VDS = 0 V and VGS = 1 V.

JLFET are shown in Fig. 6 at VGS = 0 V and 1 V. It is apparent from Fig. 6(a) that the potential varies from source to drain contacts. It may be noted that the potential in the channel is lower than the ungated Si region. On the other hand, at VGS = 1 V (Fig. 6(b)), the potential is constant in most of the channel region including center of channel and ungated Si area due to flatband condition. For cutline C2 (as shown in Fig. 6), the variation of electrostatic potential from source to drain is plotted in Fig. 7. This figure shows that a sharp drop of potential occurs in the channel and reaches its minima at a distance of 12 nm from the source contact. The potential again increases rapidly up to 35 nm and thereafter, it rises slowly towards the drain contact. Further, the electron concentration along cutline C2 is plotted in Fig. 8. This figure demonstrates the variation of electron 10

0.6

V

DS

Potential (V)

0.4

= 0 V

V

= 1 V

GS

=20 nm

G

V

GS

0.2

L

= 0 V

t

ox

0.0

=1 nm

t =10 nm g

18

-0.2 -0.4

N =1x10 d

0

10

20

30

40

50

-3

cm

60

Distance (nm)

Figure 7: Potential variation along cutline C2 for different values of VGS .

concentration in the structure which is identical to the potential variation. This is due to the fact that the reduction in electron concentration from its maximum value indicates the increase in depletion of Si region. It is inferred from Fig. 7 and 8 that Lef f of the proposed TDG-JLFET is larger than LG due to additional control of gates in Si region through tox2 which improves the SCEs of TDG-JLFET. However, this restricts the scaling capability of the proposed device. 3.2. Switching Analysis The switching performance of the proposed device is evaluated by determining the transfer characteristics, ION /IOF F , threshold voltage (Vt ), SS and DIBL. Fig. 9 demonstrates the transfer characteristics of TDG-JLFET for different values of Nd . It is seen from the figure that both ION and IOF F in11

Electron Conc. (10^x cm

-3

)

25 V

DS

20

V

= 0 V

V

= 1 V

GS

15

L

= 0 V

GS

=20 nm

G

t

ox

10

=1 nm

t =10 nm g

18

N =1x10 d

5 0

10

20

30

40

50

-3

cm

60

Distance (nm)

Figure 8: Electron concentration variation along cutline C2 for different values of VGS .

crease with Nd . The increase in IOF F is larger than ION due to the reduction in source-channel barrier height. IOF F and ION are calculated at VGS = 0 V and VGS =1 V, respectively. Fig. 10 depicts the variation in ION and ION /IOF F with LG at VDS = 0.1 V and VDS = 1.1 V for VGS > Vt . As seen from the figure, ION decreases with LG due to increase in channel resistance in linear region. For VDS = 0.1 V, ION /IOF F increases with LG upto 70 nm. Thereafter, the ratio is almost constant due to insignificant change in IOF F of the device. For VDS = 1.1 V, ION /IOF F improves with LG upto 30 nm and thereafter becomes constant. It is to be noted that ION /IOF F reduces significantly for higher VDS due to larger increase in IOF F as compared to ION . This is because of reduction in source-channel barrier height with increase in VDS . The variation in Vt with LG is plotted in Fig. 11. Vt of TDG-JLFET is 12

-3

10 m)

V

DS

(A/

10

L

G

DS

Drain current, I

= 1.1 V

-6

-9

= 20 nm

t = 10 nm

10

g

t

= 1 nm

ox

-12

10

18

N = 1x10 d

18

N = 5x10

-15

d

10

19

N = 1x10 d

-3

cm

-3

cm

-3

cm

-18

10

0.0

0.2

0.4

0.6

0.8

Gate Voltage, V

GS

1.0

(V)

Figure 9: Transfer characteristics of TDG-JLFET for different values of Nd .

t

t = 10 nm

2

for V

=0.1 V

I

for V

=1.1 V

ON

60

ON

DS

DS

1

/I

I

ON

(

10

40 20 0 20

13

m)

I

)

10

g

80

A/

= 1 nm

ox

I

/I

for V

=0.1 V

I

/I

for V

=1.1 V

ON

ON

30

40

50

OFF

OFF

60

DS

DS

70

Channel Length, L

G

80

ON

100

-3

cm

(x 10

d

OFF

18

N = 1x10

0

I

120

10

90 100

(nm)

Figure 10: ION and ION /IOF F as a function of channel length

13

Threshold Voltage, V

t

(V)

1.0 18

N = 1x10 d

-3

cm

0.9

0.8 V

for V

=0.1 V

V

for V

=1.1 V

t

0.7

t

DS

DS

t

= 1 nm

ox

0.6

t = 10 nm g

0.5 20

30

40

50

60

70

Channel Length, L

G

80

90

100

(nm)

Figure 11: Variation of threshold voltage with channel length

evaluated using constant current method. In this method, the threshold voltage is that gate voltage at which the drain current (IDS ) is 10−7 × (W/LG ) [13]. The channel width and channel length are represented by W and LG , respectively. It is observed from the figure that the variation in Vt is very small as LG changes from 20 nm to 100 nm at VDS = 0.1 V. Further, for VDS = 1.1 V, larger variation in Vt is observed at lower LG in comparison to VDS = 0.1 V due to DIBL effect. Vt is found to be 0.828 V at LG of 20 nm corresponding to VDS of 1.1 V. In addition to ION /IOF F , other important SCE parameters are SS and DIBL for evaluating the switching performance of the device. SS is defined as the change in gate voltage for a decade change in the drain current, which

14

is written as [7]: SS =



dlogIDS dVGS

−1

(1)

DIBL is expressed as [26]: DIBL =

Vt|VDS =0.1 − Vt|VDS =1.1 VDS=1.1 − VDS=0.1

(2)

Fig. 12 shows the impact of LG on SS and DIBL of TDG-JLFET. The device exhibits small reduction in SS with increase in LG due to decrease in subthreshold current. At LG of 20 nm, SS is obtained as 69 mV/dec. On the other hand, the TDG-JLFET shows significant decrease in DIBL with increase in LG from 20 nm to 60 nm and thereafter, DIBL is almost unaffected due to negligible variation in minimum channel potential with VDS . The value of DIBL is found to be 26.8 mV/V at LG of 20 nm. Fig. 13 gives the variation of ION and ION /IOF F as a function of Nd . ION increases with Nd due to increase in carrier concentration and width of neutral region in the channel. Further, ION enhances more rapidly at higher VDS due to decrease in barrier height and increase in carrier velocity. On the other hand, ION /IOF F improves upto Nd of 1018 cm−3 and thereafter, degrades due to rapid increase in IOF F . For higher VDS , ION /IOF F deteriorates due to larger increase in IOF F as compared to ION . The device attains a maximum ION /IOF F of 3.5× 1013 at Nd = 1018 cm−3 for VDS = 0.1 V. Therefore, Nd of 1018 cm−3 is taken as optimum value for evaluating the switching performance of the TDG-JLFET. Fig. 14 presents the variation of Vt as a function of Nd for the proposed device. Vt decreases with increase in Nd due to improvement in IDS . Fig. 15 15

30

100 SS for V

=0.1 V

SS for V

=1.1 V

DIBL

DS

25

DS

20 18

N = 1x10

80

d

t

-3

cm

15

= 1 nm

ox

10

t = 10 nm

70

g

5 60 20

30

40

50

60

70

Channel Length, L

G

80

DIBL (mV/V)

SS (mV/decade)

90

0 90 100

(nm)

Figure 12: Variation of SS and DIBL for different values of channel length

7

g

6

10

= 1 nm

t

ox

600

I

/I

for V

=1.1 V

400

I

for V

=1.1 V

I

for V

=0.1 V

ON

ON

ON

OFF

OFF

4

DS

DS

10

3

10

2

DS

10

200 0 17 10

ON

DS

7

=0.1 V

OFF

for V

/I

/I

( x10 )

5

10 I

I

ON

(

A/

m)

1000 800

10

t = 10 nm

= 20 nm

G

ON

L

I

1200

1

10

0

18

10

19

10

Channel Doping, N

-3

d

(cm

10

)

Figure 13: ION and ION /IOF F as a function of channel doping

16

0.9

Threshold Voltage, V

t

(V)

1.0

0.8 V

for V

=0.1 V

V

for V

=1.1 V

t

0.7

t

DS

DS

L

0.6

= 20 nm

G

t

= 1 nm

ox

0.5

t = 10 nm g

0.4 17

10

18

19

10

Channel Doping, N

-3

d

(cm

10

)

Figure 14: Impact of channel doping on threshold voltage

demonstrates the variations of SS and DIBL with Nd . SS and DIBL increase with Nd due to increase in leakage current. The variation of ION and ION /IOF F with channel thickness is plotted in Fig. 16. ION improves with tg due to increase in width of neutral region. Further, ION increases more rapidly at higher VDS due to decrease in barrier height and increase in carrier velocity. Conversely, the device shows degradation in ION /IOF F with increase in tg because IOF F increases more rapidly as compared to ION . The highest ION /IOF F is obtained for tg of 10 nm which is taken as optimum value. Fig. 17 demonstrates the impact of tg on Vt of TDG-JLFET. Vt decreases with tg since a negative gate bias is needed to achieve volume depletion. Fig. 18 shows the variation of SS and DIBL with respect to tg . SS and DIBL increase with tg due to increase in leakage current

17

100 =0.1 V

SS for V

=1.1 V

SS (mV/decade)

90

60

DIBL

DS

50

DS

L

= 20 nm

40

G

80

t

= 1 nm

ox

30

t = 10 nm g

70

20

60 17 10

18

DIBL (mV/V)

SS for V

10

19

10

10

-3

Channel Doping, N

d

(cm

)

Figure 15: Variation of SS and DIBL with channel doping

/I

for V

=1.1 V

5

DS

120

N = 1x10

100

L

I

ON

(

m)

10

A/

OFF

80 60 40 20 10

18

d

= 20 nm

G

t

= 1 nm

ox

-3

cm

4

10

3

10

2 1

10 I

for V

=0.1 V

I

for V

=1.1 V

ON

ON

12

DS

10

DS

14

OFF

I

ON

140

6

10

ON

=0.1 V

DS

8

for V

OFF

(x 10 )

/I

/I

I

ON

160

I

180

0

16

Channel thickness, t

18 g

10 20

(nm)

Figure 16: Impact of channel thickness on ION and ION /IOF F

18

1.0

Threshold Voltage, V

t

(V)

18

N = 1x10 d

-3

cm

0.8

0.6 L

= 20 nm

G

0.4

t V

for V

= 0.1 V

V

for V

= 1.1 V

t

0.2

10

t

12

DS

DS

14

= 1 nm

ox

16

Channel thickness, t

18 g

20

(nm)

Figure 17: Effect of channel thickness on threshold voltage

resulted from reduced control of gates over the channel. Fig. 19 shows the effect of gate oxide thickness on ION and ION /IOF F of the proposed structure. It is observed from the figure that ION remains almost constant with tox . However, ION is higher for larger VDS due to decrease in barrier height and increase in carrier velocity. On the other hand, ION /IOF F degrades with increase in tox due to reduction of gate control over the channel charges which increases IOF F . The value of tox is kept 1 nm for other simulations to obtain maximum value of ION /IOF F . Fig. 20 shows the variation in Vt with tox . Vt decreases with increase in tox due to reduced potential barrier height between source and channel. Fig. 21 exhibits the impact of tox on SS and DIBL of the TDG-JLFET. SS increases with tox due to reduction of gate control over channel electrostatics which results in

19

100

100 =0.1 V

SS for V

=1.1 V

DIBL

DS

SS (mV/decade)

90

80

DS

80

DIBL (mV/V)

SS for V

60 18

N = 1x10 d

70

t

-3

cm

40

=1 nm

ox

L

= 20 nm

G

60 10

12

14

16

Channel thickness, t

20 20

18 g

(nm)

Figure 18: Variation of SS and DIBL with channel thickness

100 18

N = 1x10 d

-3

cm

I

for V

=0.1 V

I

for V

=1.1 V

ON

90

ON

DS

DS

t =10 nm g

70

50

/I

for V

=0.1 V

I

/I

for V

=1.1 V

ON

ON

OFF

OFF

DS

DS

0

10

40 1.0

) ON

I

I

ON

I

1

10

60

11

(x 10

10

OFF

=20 nm

/I

G

(

A/

m)

2

L

80

1.5

2.0

Gate Oxide Thickness, t

ox

(nm)

Figure 19: Effect of gate oxide thickness on ION and ION /IOF F

20

1.0 18

(V)

N = 1x10

Threshold Voltage, V

t

d

0.9

L

-3

cm

= 20 nm

G

0.8

t = 10 nm

0.7

g

V

for V

= 0.1 V

V

for V

= 1.1 V

t

0.6

t

DS

DS

0.5 1.0

1.5

2.0

Gate Oxide Thickness, t

ox

(nm)

Figure 20: Effect of gate oxide thickness on threshold voltage

higher subthreshold current. DIBL also increases with tox due to enhanced threshold voltage roll-off at higher VDS (as seen in Fig. 20). A comparison of switching performance parameters of proposed TDGJLFET with other reported JLFETs in literature is given in Table 2. It is observed that the TDG-JLFET exhibits four orders of magnitude higher ION /IOF F , which indicates better switching performance of the proposed device in comparison to the previously reported JLFETs. However, SS and DIBL of TDG-JLFET are comparable to other JLFETs indicating the proposed structure has good control over the short channel effects. 3.3. Analog/RF Analysis The analog/RF performance of TDG-JLFET is evaluated by determining gm , transconductance generation efficiency (gm /IDS ), output conductance 21

100 =0.1 V

SS for V

=1.1 V

45

DS

90 SS (mV/decade)

50

DIBL

DS

18

N = 1x10 d

-3

cm

40

80 35

70

t = 10 nm g

DIBL (mV/V)

SS for V

30

L

= 20 nm

G

60

25

1.0

1.5

2.0

Gate Oxide Thickness, t

ox

(nm)

Figure 21: Effect of gate oxide thickness on SS and DIBL

800 L

= 20 nm

G

t = 10 nm g

m)

600

t

19

N = 1x10

= 1 nm

d

-3

cm

A/

ox

DS

(

400 V

=0.9 V

V

=1.0 V

V

=1.1 V

V

=1.2 V

I

GS

GS

200

GS

GS

0 0.0

0.2

0.4

0.6

0.8

Drain Voltage, V

DS

1.0

(V)

Figure 22: Drain characteristics of TDG-JLFET for different VGS

22

Table 2: Comparison of switching performance of different JLFETs

Parameter

DP-DG JL

NU-DG JL

NU-DG JL

DM-JL-DG

TDG-JL

FET [13]

FET [15]

FET [15]

FET [18]

FET (This work)

LG

20

32

50

50

20

105

109

109

108

1013

68

74

64

66

69

0.3

0.2

0.3

0.11

0.85

68

80

30

22

27

(nm) ION /IOF F (∼) (@ VDS =1.1 V, VGS =1 V ) SS (mV/dec) (@ VDS =0.1 V ) Vt (V) DIBL (mV/V)

23

1600 18

N = 1x10 d

18

N = 5x10 d

1200

19

d

800

L

-3

cm

-3

cm

= 20 nm

G

m

(

S/

m)

N = 1x10

-3

cm

V

g

DS

400

= 1.1 V

t = 10 nm g

t

= 1 nm

ox

0 0.0

0.2

0.4

0.6

0.8

Gate Voltage, V

GS

1.0

1.2

(V)

Figure 23: Variation of transconductance with VGS for different values of Nd

(gd ), intrinsic voltage gain (AV = gm /gd ), total capacitance (CGG ) and fT . Fig. 22 gives the output characteristics of proposed TDG-JLFET. IDS increases with VGS due to increase in neutral channel width. Further, IDS becomes constant at higher VDS due to induced depletion near the drain contact resulting in channel pinch-off. Fig. 23 shows the variation of gm with VGS for different values of Nd . This figure demonstrates that the value of gm enhances with Nd due to increase in IDS and better control of two gates over IDS . The peak value of gm is observed as 1478 µS/µm at Nd of 1019 cm−3 , which is taken as optimum value for analog/RF performance.

The

impact of LG on gm is plotted in Fig. 24. TDG-JLFET exhibits increase in peak gm for smaller values of LG due to increased control of gate over channel electrostatics. It is to be noted that the peak of gm shifts towards

24

1600

19

N = 1x10

t = 10 nm

d

g

V

DS

1200

t

-3

cm

= 1.1 V = 1 nm

800 L

=20 nm

L

=30 nm

L

=40 nm

L

=50 nm

G

m

(

S/

m)

ox

g

G

400

G

G

0 0.6

0.8

1.0

1.2

Gate Voltage, V

GS

1.4

1.6

(V)

Figure 24: Variation of transconductance with VGS for different values of LG

higher VGS for longer LG as compared to short channel TDG-JLFET. Fig. 25 depicts the variation of peak gm and Vt with LG . The device gives improvement in gm and reduction in Vt with decrease in LG . The roll-off of Vt is faster at smaller LG due to increase in subthreshold conduction. The proposed structure attains Vt of 0.42 V at LG = 20 nm with Nd = 1019 cm−3 . Fig. 26 plots the transconductance generation efficiency with respect to VGS for different values of LG . The highest value of gm /IDS is 16.4 V−1 at LG = 50 nm. The gm /IDS reduces for shorter LG due to larger increase in IDS as compared to gm . Fig. 27 demonstrates the change in output conductance with drain bias for different values of VGS . The reduction in gd with increase in VDS is due to induced depletion near the drain terminal leading to lower mobile charge

25

0.56

1500 N = 1x10

m

d

-3

cm

(V)

19

g

V

0.52 V

= 1 nm

ox

1300

0.48

t = 10 nm g

g

m

(

S/

m)

DS

t

= 1.1 V

0.44

1200

0.40

1100 20

Threshold Voltage, V

t

t

1400

30

40

50

60

70

Channel Length, L

G

80

90

100

(nm)

Figure 25: Variation of transconductance and threshold voltage with LG

density at high drain bias. Further, it is observed from the figure that gd is higher for large values of VGS due to increase in IDS with VGS . Fig. 28 gives the change in gd with VDS for different values of LG . Output conductance gd is higher at shorter LG as compared to longer LG . It is due to enhanced effect of VDS over channel electrostatics at short LG leading to higher IDS . Further, at lower VDS , the depletion at drain side decreases leading to increase in gd . Fig. 29 shows the variation of AV with VGS for different values of LG . AV decreases with VGS due to reduction in gm of the device. Moreover, AV reduces for short LG because increase in gd dominates over improvement in gm . The proposed device yields AV = 30 and 300 at LG = 20 nm and 50 nm, respectively. The variation of total capacitance (CGG =CGS +CGD ) as a function of VGS

26

18 19

=20 nm

L

=30 nm

= 1 nm

L

=40 nm

t = 10 nm

L

=50 nm

d

15

V

DS

t

12

-3

L

N = 1x10

cm

G

= 1.1 V

G

G

(V

-1

)

ox

G

g

6

g

m

/I

DS

9

3

0 0.6

0.8

1.0

1.2

Gate Voltage, V

GS

1.4

1.6

(V)

Figure 26: Variation of transconductance generation efficiency with VGS for different values of LG

2400 19

= 20 nm N = 1x10

L

G

2000

t

d

= 1 nm

t = 10 nm g

1600

V

1200

GS

(

S/

m)

ox

=0.9 V

V

=1.0 V

V

=1.1 V

V

=1.2 V

GS

d

g

-3

cm

800

GS

400

GS

0 0.0

0.2

0.4

0.6

0.8

Drain Voltage, V

DS

1.0

(V)

Figure 27: Variation of output conductance with VDS for different values of VGS

27

2400 19

N = 1x10 d

2000

t

= 1 nm

ox

-3

cm

V

=1 V

GS

t = 10 nm g

L

=20 nm

L

=30 nm

L

=40 nm

L

=50 nm

G

1200

G

800

g

d

(

S/

m)

1600

G

400

G

0 0.0

0.2

0.4

0.6

0.8

Drain Voltage, V

1.0

(V)

DS

Figure 28: Variation of output conductance with VDS for different values of LG

300

L

=20 nm

L

=30 nm

L

=40 nm

L

=50 nm

G

t = 10 nm g

t

G

= 1 nm

ox

G

200 AV

G

19

N = 1x10 d

V

100

DS

-3

cm

= 1.1 V

0 0.3

0.6

0.9

Gate Voltage, V

GS

1.2

(V)

Figure 29: Variation of intrinsic voltage gain with VGS

28

1.6 L

G

=30 nm

L

cm

=40 nm

t

t = 10 nm

L

=50 nm

= 1 nm

ox

1.2

G

g

0.8

C

GG

(fF/

m)

G

-3

N = 1x10 d

L

G

19

=20 nm

0.4

V

DS

0.6

= 1.1 V

0.8

1.0

1.2

Gate Voltage, V

GS

1.4

1.6

(V)

Figure 30: Variation of total gate capacitance with VGS for different values of LG

500 t

= 1 nm

L

t = 10 nm

ox

g

L

400

f

T

(GHz)

L L

300

=20 nm

G

=30 nm

G

=40 nm

G

=50 nm

G

200

V

100

DS

= 1.1 V 19

N = 1x10 d

-3

cm

0 0.6

0.8

1.0

1.2

Gate Voltage, V

GS

1.4

1.6

(V)

Figure 31: Variation of cut-off frequency with VGS for different values of LG

29

for different values of LG is shown in Fig. 30. At smaller VGS , CGG is lower as compared to that at higher VGS due to partial depletion of channel region. At higher VGS , the depletion in the channel reduces which increases CGG . With further increase in VGS , TDG-JLFET is driven into accumulation mode leading to drop in CGG with VGS . For evaluation of analog/RF performance of a JLFET, fT is an important parameter which should be as high as possible for high frequency applications. For JLFET, fT is written as [27]: fT =

gm 2πCGG

(3)

In order to achieve large fT , a better designed JLFET must have higher gm and lower CGG . Fig. 31 demonstrates the variation of fT as a function of VGS for different values of LG . For TDG-JLFET, fT increases with VGS because the improvement in gm dominates over increase in CGG . At high gate bias, fT decreases due to reduction in gm and increase in CGG . For a shorter LG , fT is higher in comparison to that of longer channel due to enhancement in gm and reduction in CGG . The proposed TDG-JLFET achieves a maximum fT of 423 GHz at LG = 20 nm. Table 3 gives a comparison of analog/RF parameters of proposed TDGJLFET with other JLFET structures. The simultaneous control of drain current by two gates and optimized device dimensions lead to substantial improvement in gm of proposed device. The TDG-JLFET exhibits maximum gm of 1478 µS/µm which is 2.8 times higher as compared to JLFET reported by Ghosh et al [19]. Further, the proposed device achieves fT of 423 GHz which is 2.5 times higher than the reported JLFET [19]. A large improvement in gm and fT make the proposed structure a superior choice for analog/RF applications. 30

Table 3: Comparison of RF performance of different JLFETs

Parameter

LG

ULP JL

JL

JL-DGFET

TDG-JLFET

FET [11]

FET [19]

FET [28]

(This work)

20

20

20

20

197

530

162

1478

92

170

51

423

(nm) gm (µS/µm) fT (GHz)

4. Conclusion A new TDG-JLFET having vertical parallel double-gate structure is presented. The electrostatic analysis of TDG-JLFET is carried out to understand the variation of electric field, potential and electron concentration in the silicon region of the device. The switching and analog/RF performance parameters of the proposed device are evaluated using 2D numerical simulations. The device structural parameters are varied to study their impact on various performance parameters like ION /IOF F , Vt , SS, DIBL, gm , gm /IDS , gd , gm /gd , CGG , and fT . TDG-JLFET provides four orders of magnitude higher ION /IOF F while exhibits SS and DIBL comparable to the reported JLFETs. In addition, TDG-JLFET achieves peak gm of 1478 µS/µm and fT of 423 GHz which are substantially higher as compared to reported JLFETs. The results of this work reveal that the proposed structure is suitable for switching as well as analog/RF applications.

31

[1] Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Colinge, J.P.. Junctionless multigate field-effect transistor. Applied Physics Letters 2009;94(5):053511. doi:10.1063/1.3079411. [2] Lee,

C.W., Ferain,

N.D., Razavi,

I., Afzalian,

P., et al.

A., Yan,

R., Akhavan,

Performance estimation of junction-

less multigate transistors. Solid-State Electronics 2010;54(2):97–103. doi:10.1016/j.sse.2009.12.003. [3] Colinge, J.P., Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., et al. Nanowire transistors without junctions. Nature nanotechnology 2010;5:225–229. doi:10.1038/nnano.2010.15. [4] Kumar, A., Gupta, A., Rai, S.. Reduction of self-heating effect using selective buried oxide (SELBOX) charge plasma based junctionless transistor. AEU - International Journal of Electronics and Communications 2018;95:162 – 169. doi:10.1016/j.aeue.2018.08.023. [5] Colinge, Yu,

J.P., Kranti,

R., et al.

A., Yan,

R., Lee,

C.W., Ferain,

I.,

Junctionless nanowire transistor (JNT): Proper-

ties and design guidelines. Solid-State Electronics 2011;65-66:33–37. doi:10.1016/j.sse.2011.06.004. [6] Singh,

B., Gola,

D., Goel,

E., Kumar,

S., Singh,

K., Jit,

S..

Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications. Journal of Computational Electronics 2016;15:502–507. doi:10.1007/s10825-016-0808-3. 32

[7] Singh,

B., Gola,

Jit,

S..

D., Singh,

K., Goel,

E., Kumar,

S.,

Analytical modeling of subthreshold characteristics of

ion-implanted symmetric double gate junctionless field effect transistors.

Materials Science in Semiconductor Processing 2017;58:82–88.

doi:10.1016/j.mssp.2016.10.051. [8] Garg, N., Pratap, Y., Gupta, M., Kabra, S.. Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and ring oscillator circuit. AEU International Journal of Electronics and Communications 2019;108:251 – 261. doi:10.1016/j.aeue.2019.06.014. [9] Bousari, N.B., K. Anvarifard, M., Haji-Nasiri, S.. Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering. AEU - International Journal of Electronics and Communications 2019;108:226 – 234. doi:10.1016/j.aeue.2019.06.017. [10] Doria, R.T., Pavanello, M.A., Trevisoli, R.D., de Souza, M., Lee, C., Ferain, I., et al. Junctionless multiple-gate transistors for analog applications. IEEE Transactions on Electron Devices 2011;58(8):2511 – 2519. doi:10.1109/TED.2011.2157826. [11] Ghosh,

D., Parihar,

M.S., Armstrong,

G.A., Kranti,

A.. High-

performance junctionless MOSFETs for ultralow-power analog/RF applications.

IEEE Electron Device Letters 2012;33(10):1477–1479.

doi:10.1109/LED.2012.2210535. [12] Baruah,

R.K., Paily,

R.P.. 33

A dual-material gate junction-

less transistor with high-k spacer for enhanced analog performance. IEEE Transactions on Electron Devices 2014;61(1):123–128. doi:10.1109/TED.2013.2292852. [13] Singh, S..

B., Gola,

D., Singh,

K., Goel,

E., Kumar,

S., Jit,

2-D analytical threshold voltage model for dielectric pocket

double-gate junctionless FETs by considering source/drain depletion effect.

IEEE Transactions on Electron Devices 2017;64(3):901–908.

doi:10.1109/TED.2016.2646460. [14] Singh, S..

B., Gola,

D., Singh,

K., Goel,

E., Kumar,

S., Jit,

Analytical modeling of channel potential and threshold voltage

of double-gate junctionless FETs with a vertical Gaussian-like doping profile. IEEE Transactions on Electron Devices 2016;63(6):2299–2305. doi:10.1109/TED.2016.2556227. [15] Kumari,

V., Kumar,

A., Saxena,

M., Gupta,

M..

Empirical

model for nonuniformly doped symmetric double-gate junctionless transistor.

IEEE Transactions on Electron Devices 2018;65(1):314–321.

doi:10.1109/TED.2017.2776607. [16] Parihar, M.S., Kranti, A.. Revisiting the doping requirement for low power junctionless MOSFETs. Semiconductor Science and Technology 2014;29(7):075006. doi:10.1088/0268-1242/29/7/075006. [17] Jaiswal, N., Kranti, A.. A model for gate-underlap-dependent shortchannel effects in junctionless MOSFET. IEEE Transactions on Electron Devices 2018;65(3):881–887. doi:10.1109/TED.2018.2796602. 34

[18] Kumari, V., Modi, N., Saxena,

M., Gupta, M.. Theoretical in-

vestigation of dual material junctionless double gate transistor for analog and digital performance. IEEE Transactions on Electron Devices 2015;62(7):2098–2105. doi:10.1109/TED.2015.2433951. [19] Ghosh, D., Kranti, A.. Impact of channel doping and spacer architecture on analog/RF performance of low power junctionless MOSFETs. Semiconductor Science and Technology 2015;30.

doi:10.1088/0268-

1242/30/1/015002. [20] ATLAS user’s manual: Device simulation software, Silvaco Int., Santa Clara, CA 2015;. [21] Kim, B.G..

S., Kim,

J., King Liu,

T.J., Choi,

W., Park,

Demonstration of L-Shaped tunnel field-effect transis-

tors. IEEE Transactions on Electron Devices 2016;63(5):1774–1778. doi:10.1109/TED.2015.2472496. [22] Singh,

Y., Badiyari,

M..

Performance optimization of InGaAs

power LDMOSFET. Microelectronics Journal 2015;46(5):404 – 409. doi:10.1016/j.mejo.2015.02.007. [23] Adhikari,

M.S., Patel,

R., Singh,

Y..

High performance dual-

gate SiGe MOSFET for radio-frequency applications. AEU - International Journal of Electronics and Communications 2019;110:152838. doi:10.1016/j.aeue.2019.152838. [24] Gola, D., Singh, B., Tiwari, P.. Subthreshold modeling of tri-gate junctionless transistors with variable channel edges and substrate bias 35

effects. IEEE Transactions on Electron Devices 2018;65(5):1663–1671. doi:10.1109/TED.2018.2809865. [25] Gnudi, A., Reggiani, S., Gnani, E., Baccarani, G.. Semianalytical model of the subthreshold current in short-channel junctionless symmetric double-gate field-effect transistors. IEEE Transactions on Electron Devices 2013;60(4):1342–1348. doi:10.1109/TED.2013.2247765. [26] Gola,

D., Singh,

B., Tiwari,

P..

A threshold voltage model of

tri-gate junctionless field-effect transistors including substrate bias effects. IEEE Transactions on Electron Devices 2017;64(9):3534–3540. doi:10.1109/TED.2017.2722044. [27] Singh, B., Rai, T., Gola, D., Singh, K., Goel, E., Kumar, S., et al. Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure. Materials Science in Semiconductor Processing 2017;71:161–165. doi:10.1016/j.mssp.2017.07.014. [28] Sirohi, A., Sahu, C., Singh, J.. Analog/RF performance investigation of dopingless FET for ultra-low power applications. IEEE Access 2019;7:141810–141816. doi:10.1109/ACCESS.2019.2937444.

36