A new unified control strategy for inverter-based micro-grid using hybrid droop scheme

Alexandria Engineering Journal (2019) xxx, xxx–xxx

H O S T E D BY

Alexandria University

Alexandria Engineering Journal www.elsevier.com/locate/aej www.sciencedirect.com

ORIGINAL ARTICLE

A new unified control strategy for inverter-based micro-grid using hybrid droop scheme M.A. Aboushal a,*, Mohamed M. Zakaria Moustafa b a b

Middle East Oil Refinery Co., Department of Electrical and Automation, Amreya Free zone, Alexandria 23511, Egypt Alexandria University, Department of Electrical Engineering, Lotfy El-Sied st., Alexandria 21526, Egypt

Received 18 August 2019; revised 17 October 2019; accepted 20 October 2019

KEYWORDS Universal current droop; Robust droop control; Proportional resonant controller; Parallel inverters; Unified control; Micro-grid; Smart grids

Abstract Micro-grid (MG) operation using voltage control methods (VCMs) has been widely recommended for parallel operation of three phase voltage source inverters, especially during islanded mode to maintain the voltage level in the MG. In contrast, this paper presents a new unified control strategy for MG parallel operation using a current control method (CCM). A hybrid control scheme which combines a universal robust droop controller (URDC) and quasi-proportional resonant (QPR) regulator is introduced. It ensures equal power sharing among parallel operated inverters during all MG’s operating modes. Moreover, an improved adaptive estimator for the reference current magnitude is integrated to meet dynamic load variations. Furthermore, the scheme is enhanced with a self-synchronized capability using a simple synchronous reference frame phase locked loop (SRF-PLL). This obviates the necessity of communication links and external synchronous clocks required for synchronization process. In addition, a decentralized control action is locally managed to restore the inverter’s frequency upon any reactive load change. Modeling and simulation results using MATLAB/SIMULINK software are presented to show the effectiveness of the proposed strategy. Ó 2019 Faculty of Engineering, Alexandria University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).

1. Introduction Power electronic converters are used as the interfacing media for incorporating different types of renewable energy resources (RES) into micro-grids (MGs) [1–3]. Generally, all the used control strategies for MG operation should satisfy common principal roles [4–6]. Primarily, the MG is operated in either * Corresponding author at: In front of 52, Al Sag Mohamed AbdelSalam St., Alexandria, Egypt. E-mail address: [email protected] (M.A. Aboushal). Peer review under responsibility of Faculty of Engineering, Alexandria University.

islanded mode (ISM) or grid-connected mode (GCM). To ensure seamless transition between the two modes, islanding detection (ID) as well as safe resynchronization with the main grid should be considered. Furthermore, the control system must ensure proper load sharing while maintaining strict regulation of the output voltage and frequency during ISM. On the other hand, in GCM, the main grid maintains the voltage level and frequency of the network, while the MG directly controls the injected power with the main grid. According to the hierarchical control structure which is reported in [4], the inner control loops are referred as ‘‘zero-level” which are further categorized by two main types, namely current controlled methods (CCMs) and voltage controlled methods (VCMs).

https://doi.org/10.1016/j.aej.2019.10.006 1110-0168 Ó 2019 Faculty of Engineering, Alexandria University. Production and hosting by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

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M.A. Aboushal, Mohamed M. Zakaria Moustafa

Nomenclature BW bandwidth CCMs current controlled methods CCVSIs current controlled voltage source inverters CRUDC current regulated universal droop controller DGs distributed generators DM droop mode EFLI effective line impedance FFRES fast frequency restoration FFT fast Fourier transform GCM grid-connected mode GSVS grid-supporting voltage source ID islanding detection ISM Islanded mode LV low voltage MGs micro-grids OLTF open loop transfer function PCC point of common coupling PF power factor PM phase margin PR proportional resonant PWM pulse width modulation QPR quasi-proportional resonant RCDC robust current droop controller RES renewable energy resources SCD sampling control delay SGs synchronous generators SM set mode SRF synchronous reference frame SRF-PLL synchronous reference frame phase locked loop UDC universal droop controller kr resonant gain of the PR current regulator Vratio voltage variation ratio N total number of VSIs in the MG eabc input voltage of the LC filter iLabc inductor current of the LC filter voabc grid side output voltage ioabc grid side output current Zload load impedance at the PCC Zline coupling line impedance Vdc DC link voltage Lf filter inductance Cf filter capacitance Vod Voltage direct axis component Voq voltage quadrature axis component E* nominal value of voltage magnitude IrefPK[n
1] previous current magnitude IrefPK[n] new reference current magnitude n sampling control delay measurement sampling time Ts mP active droop coefficient nq reactive droop coefficients Prated rated active power

Meanwhile, a higher primary level is incorporated in the outer loop to regulate the active and reactive power flows. It uses either virtual synchronous generator (VSG) or droop-based structures. It has been demonstrated that current-controlled

URDC VCMs VSG VSIs ab-STF Srefpk Sref,mag Sset* SDG Vopk Iopk Irefpk Iref,mag Iset* Ke xPR xnom hv xerr fpr kpL kiL fvDG xc xvDG hiref Vdrop fboost Ioq kp Qrated DVmax Dxmax x* P* Q* Eref xref P Q kpr kir Eref_ab Eref_abc xc(max) Td Um Ibase Vline tsl xm f

universal robust droop controller voltage controlled methods virtual synchronous generator voltage source inverters ab-stationary frame reference apparent power magnitude reference apparent power drooped magnitude setpoint of the shared apparent power measured output apparent power per phase measured output voltage magnitude measured output current magnitude reference current magnitude reference current drooped magnitude active current setpoint integral gain for the voltage error angular resonant frequency of the controller nominal angular frequency of the MG phase angle of inverter’s output voltage angular frequency error generated by SRF-PLL resonant frequency of the controller proportional gain of the loop filter of SRF-PLL integral gain of the loop filter of SRF-PLL. output frequency obtained from SRF-PLL. cut-off frequency of the QPR regulator output angular frequency extracted by SRF-PLL commanded current phase angle voltage drop ratio frequency boost ratio quadrature axis of the inductor output current proportional gain of the PR current regulator rated reactive power maximum voltage deviation maximum frequency deviation Nominal value of fundamental frequency active power set-point reactive power set-point reference voltage magnitude angular frequency reference measured output active power measured output reactive power proportional gain of the FFRES loop integral gain of the FFRES loop reference voltage vector in ab-STF reference voltage vector in abc natural frame maximum angular cut-off frequency sampling control delay phase margin current base value line to line voltage settling time cross-over frequency of the loop filter damping ratio of the PLL

voltage source inverters (CCVSIs) cannot be operated in parallel during ISM due to the absence of grid-supporting voltage source (GSVS) [4–11]. Hence, CCMs have been exclusively used during GCM in most of prior researches [12–17].

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

Hybrid droop scheme Conversely, droop based VCMs have been employed suitably with dual-mode of operation including both grid-connected and islanded modes. Furthermore, they ensure proportional sharing of real and reactive power among parallel distributed generators (DGs) without the necessity of communication links, besides regulating the output voltage and frequency. Therefore, VCMs have been found to be more suitable for the design of zero-level architecture compared to CCMs due to their flexibility of ’plug and play’ operation during all modes of MG applications. Nevertheless, droop based VCM is flawed by many shortcomings [7–10,18–21]. Firstly, the dual voltage loop configuration produces slow dynamic response. This occurs due to that the outer voltage control loop is normally tuned to be slower than the inner current loop in order to avoid oscillatory response. Thus, the high bandwidth (BW) capability of the inner current regulator is reduced leading to slower response. Similar delay is subjected by the outer droop controllers, including the sampling time, transport delay and signal conditioning for the calculated output active and reactive power. Another factor which limits the system dynamic response is resulted from the inertia-less nature of voltage source inverters (VSIs). Besides, the usage of pre-defined setpoints by the droop controllers does not actually provide natural response against load variations in contrary with speed governed synchronous generators (SGs). Furthermore, the control system necessitates higher droop gains to enhance the power sharing accuracy. However, the larger the droop gains, the larger deviations emerged with the output frequency and voltage amplitude. Hence, unavoidable compromise between desired dynamic response and system stability is imposed which in turn complicates the controller design. Moreover, the uncertainties of inverters’ output impedance significantly affect the power sharing accuracy and contribute in the design complexity. Various methods have been presented to deal with the uncertain effective line impedance (EFLI), e.g. transformations in orthogonal PQ and virtual v-x frames [22], online evaluation of the line decoupling matrix [23], active cancellation for the EFLI [24], in addition to numerous approaches which are based on virtual impedance [4,7,8,10]. Nonetheless, even if EFLI is correctly estimated, the inverters’ parallel operation cannot be implemented unless having the same per unit value of EFLI per each parallel DG. Interestingly, a universal droop formula has been presented in [18–21] which complies with various angles of output impedance ranged from – p/2 to p/2. This approach overcomes the need of complex transformations which are used to estimate the line impedance angle. Furthermore, it avoids the required change of the droop formula pursuant to different types of EFLIs. Notwithstanding, despite of these improvements, VCMs still have no direct control of output current. Therefore, they are less immune to the common power quality issues which are normally manifested in the presence of load transients, current harmonics, voltage unbalances, and disturbances at the point of common coupling (PCC). In contrast, CCMs are more efficient in addressing the microgrid power quality as they hold significant advantages compared to VCMs, such as direct control over output current and faster dynamic performance [12,16,17]. Accordingly, alternative solutions have been posed to avail the merits of VCM and CCM alongside together for higher flexibility and seamless operation in the MG [9,25– 29]. However, most of these methods need accurate islanding

3 detection to suitably switch between VCM and CCM according to the MG’s operating mode. Moreover, switching events may not be quick enough to mitigate the transient condition jeopardizing the system stability. Therefore, for improving the power quality, a unified current controller can be sought as an effective solution that ensures seamless transitions among the MG’s operating modes while obviating the need to switch between different controllers. In this essence, this paper introduces a new unified currentcontrolled strategy implemented in ab-stationary frame (abSTF) as an alternative solution for the droop based VCMs which are commonly executed in dq synchronous reference frame (SRF). To achieve this goal, certain objectives have been followed to extend the concept of droop based VCMs to the proposed CCM. Firstly, on the contrary to previous researches [4–10], the drawback of the inertial-less nature of CCVSIs during ISM has been considered through an improved adjustable current estimator. The latter updates the reference current magnitude through a scaling multiplier pursuant to any voltage sag or swell caused by load variations. This enables direct control of output current while maintaining the voltage level during dynamic load changes. Thereby, the proposed CCM can adaptively operate during both ISM and GCM without the necessity of dual voltage loop architecture as opposed to earlier methods [4–10]. Furthermore, the proposed control scheme has a unique feature that no requirement for either islanding detection or switching between VCM and CCM in matching with the MG’s operating mode is needed. Accordingly, the consequent switching events between different controllers are totally avoided which facilitates seamless transitions and maintains system stability during transients in contrast to prior researches [25–29]. Additionally, the proposed predictive current estimator depends only one voltage transformation which provides simpler design, less oscillatory response, and higher accuracy compared with other inaccurate approximations which encounter division over zero-crossings and inductor current differentiation [9,30,31]. Secondly, a strategy for proportional load sharing has been addressed between parallel DGs through a hybrid structure which comprises a universal robust droop controller (URDC) embedded with an inner quasi-proportional resonant (QPR) regulator. The hybrid URDC-QPR scheme is newly presented in this paper replacing the conventional droop based VCMs reported in the literature [18–21]. The introduced structure depends only on one droop function used in the outer loop for regulating the active current. Meanwhile, the reactive current is intrinsically controlled by the adopted QPR inner regulator. In comparison with the URDC presented in [18–21], the proposed scheme offers better simplicity by reducing the total number of control loops, where the inner voltage regulator as well as the outer reactive droop controller have been eliminated. Moreover, as opposed to droop based VCMs, the real and reactive power flows are no longer considered as the primary controlled variables, whereas the current is directly controlled instead. This results in better dynamic response by obviating the respective power measurements, computation burdens, and elimination of imposed delays by the outer real and reactive power controllers. Thus, the proposed hybrid scheme yields a robust current droop controller (RCDC) that holds all the advantage of the original VCM based universal droop controller, but with less complexity and direct control

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

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M.A. Aboushal, Mohamed M. Zakaria Moustafa

of output currents. Hence, the proposed system provides accurate power sharing and robust voltage regulation without knowing the MG uncertainties, e.g. EFLIs. Furthermore, thanks to the adoption of QPR current regulator within the inner control loop, the proposed controller becomes less sensitive to frequency variations emerged in the MG resulted by transients and voltage fluctuations at the PCC. Accordingly, the system stability and power quality is significantly enhanced compared with similar approaches which utilize ideal PR current regulator [9,13,14]. Additionally, improvements and comparative results are elaboratively discussed in contrast to the unified controlled presented in [9] which was mainly presented for single phase systems. Comparatively, the advantages of the proposed system have been investigated with respect to better robustness, improved output power quality and sharing accuracy, and strict voltage regulation. Thirdly, further enhancements have been implemented by introducing a local self-synchronized approach for embedding parallel inverters with the MG. It uses synchronous reference frame phase locked loop (SRF-PLL) through which the reference current angle is made in phase with the output voltage ensuring power generation at unity power factor (PF). Moreover, a secondary decentralized control action is addressed locally by each DG to enhance the reactive power sharing accuracy through fast frequency restoration which complies with the standard limits of EMC- (EN 61000) [32,33]. The rest of this paper is organized as follows. Section 2 describes the architecture of the MG under study alongside with definition of the used system parameters. Section 3 elaborates the proposed methodology for the parallel operation of CCVSIs. This section is sub-divided into three parts, including the generation of the reference current magnitude using the proposed URDC-QPR hybrid scheme, generation of the reference current angle, and frequency restoration to the nominal value per each DG. Section 4 demonstrates the overall URDC-QPR hybrid control scheme, besides the criteria of selection for the control system parameters. Section 5 presents

Fig. 1

different simulations using MATLAB/SIMULINK software with detailed discussions to validate the competency of the proposed strategy. Finally, the concluding remarks describing the significance of this research are presented in Section 6. 2. Micro-grid case study A low voltage (LV) MG is considered for the case study in this paper [9,10], as shown in Fig. 1. Two DGs are incorporated in parallel through distribution lines which are connected to the PCC. Each DG unit consists of an ideal DC source, three leg pulse width modulated voltage source inverter (VSI), and an LC output filter. For j = 1,2,..N, where N is the total number of VSIs in the MG, then ejabc is the LC filter input voltage, iLjabc is the inductor current of the LC filter, vojabc is the grid side output voltage, iojabc is the grid side output current, Zload is the load impedance at the PCC, Zlinej is the coupling line impedance, Vdc is the DC link voltage, Lf and Cf are the filter inductance and capacitance respectively. 3. Proposed methodology for parallel operation of CCVSIs 3.1. Generation of the reference current magnitude As explained, the current-controlled operation has few limitations during ISM, as the load voltage magnitude is not governed by any GSVS. Hence, any sudden load increase exceeding the reference current setpoint would normally reduce the output voltage by the same ratio and vice versa due to the inertia-less nature of VSIs. Accordingly, a careful attention should be paid when CCMs are used to maintain the voltage magnitude regulation. Therefore, an adjustable reference current estimator is introduced to meet continuous load variations. The key philosophy of the proposed estimator is to monitor the output voltage variations compared with its nominal value in order to automatically adjust the reference current

Small scale MG comprising two inverters connected in parallel.

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

Hybrid droop scheme

5

magnitude accordingly. In this context, a simple voltage transformation from ab-STF to dq-SRF is adopted as described below in (1).
   
Voa Vod cosðhv Þ sinðhv Þ ¼ ð1Þ  Voq Vob
sinðhv Þ cosðhv Þ where Vod and Voq are the transformed direct and quadrature axes of the three phase output voltages, respectively. Basically, Vod represents the DC envelope of the AC output voltage waveform, hence it directly benefits in obtaining the output voltage magnitude with less computational burdens. Thus, the voltage variation ratio (Vratio) can be calculated as given in (2). Vratio ¼

E Vod

ð2Þ

where E* is the nominal value of voltage magnitude. Hence, the new reference current magnitude can be scaled through multiplication by Vratio as defined below; IrefPK ½n ¼ Vratio  IrefPK ½n
1

ð3Þ

where IrefPK [n], IrefPK [n
1] are the new and previous magnitudes of the reference current signal, respectively. n is the sampling control delay (SCD). This delay should be carefully considered as an important parameter affecting the system dynamic performance. Therefore, it must be higher than the summation of the measurements’ sampling time (Ts) in addition to the feedback transport delay to avoid any oscillations in the updated reference current that may lead to system instability. Therefore, SCD is conventionally estimated by one and half sampling time, i.e. SCD or [n] = 1.5  Ts [15]. Note that the proposed current magnitude estimator avoids the unnecessary approximations, e.g. division over zerocrossings and inductor current differentiation as witnessed in some voltage estimating techniques presented in [9,30,31]. For instance, approximate phase angles equivalent to (±20°) have been considered in nearby to zero angle (0°) as reported by [9] in order to avoid division over the zero-crossings of the voltage sine waveform. However, such assumptions badly affect the accuracy of the measured peak voltage per each cycle and further lead to oscillations in the commanded reference current. In contrast, as described in (1) the voltage peak value is calculated according to a simple transformation resulting in higher accuracy and less-complications. Besides, no remarkable oscillations are emerged in the scaled reference current. To proportionally share the load between parallel DGs without using communication links, the droop control is commonly employed for such purposes. Thus, the adjustable reference current magnitude Iref,pk[n] calculated in (3) is further modified to produce a new reference value according to the load sharing philosophy. However, two main issues are generally encountered by droop control. First, parallel DGs should have the same per unit value of EFLI to equally share the output power, but practically this differs from one DG to another [18,21]. Second, different ratings belonged to parallel inverters form an additional issue, where the power sharing should be proportionally addressed. In this case, the droop coefficient of each DG should be scaled as follows. mp1 Prated1 ¼    ¼ mpj Pratedj ¼ DVmax

ð4Þ

nq1 Qrated1 ¼    ¼ nqj Qratedj ¼ Dxmax

ð5Þ

where mPj and nqj are the active and reactive droop coefficients of the jth DG, respectively. Pratedj and Qratedj are the rated values of real and reactive powers of the jth DG, respectively. DVmax and Dxmax are the maximum voltage and frequency deviations per each DG. However, if MG extension is in progress, then the droop coefficients of other interconnected DGs may be unknown. Therefore, to overcome the above-mentioned limitations, an improved current droop controller is introduced hereinafter instead of its original voltage regulated form. The main advantage of droop based CCM over VCM is that it enables direct control over output current providing better dynamic response and power quality. Accordingly, a hybrid structure is derived encompassing a robust current droop controller (RCDC) embedded with an inner QPR regulator. 3.1.1. Robust Current Droop Controller used in the outer loop As delineated in [18,21], a universal droop controller (UDC) has been presented for suitability to any inverter type having an impedance angle (h) ranged between (
p/2 and p/2) as given by (6) and (7). Eref ¼ E
mp  ðP
P Þ

ð6Þ

xref ¼ x þ nq  ðQ
Q Þ

ð7Þ

where E*and x*, are the nominal values of voltage magnitude and frequency, respectively. Meanwhile, P* and Q* are the active and reactive power set-points, respectively. Eref is the reference voltage magnitude and xref is the angular frequency reference. P and Q are the measured output active and reactive powers respectively. However, since this paper mainly focuses on presenting a unified CCM instead of the original VCM based droop control. Then, it alternatively deals with the current regulated universal droop controller (CRUDC) which is presented by [9]. Thus, an updated version of this controller is introduced herein with a more robust form. If the inverter’s output is maintained at unity PF, then the reference apparent power magnitude can be calculated as per the following expression.   Sref;mag ¼ Srefpk
mp  SDG
Sset ð8Þ where Sref,mag and Srefpk are the reference apparent power magnitude with and without applying the power sharing algorithm, respectively. Sset* is the setpoint of the shared apparent power. Meanwhile, SDG is the output apparent power measured per phase which can be calculated as follows; Vopk Iopk SDG ¼ pffiffiffi  pffiffiffi 2 2

ð9Þ

where Vopk and Iopk are the measured output voltage and current magnitudes, respectively. Then, from (8) and (9), (6) can be rewritten as given in (10);
 E Iref;mag E IrefPK Vopk Iopk E Iset ¼
mp 
ð10Þ 2 2 2 2 where Iref,mag is the new reference current magnitude, Irefpk is the reference current magnitude without applying the power sharing algorithm, and Iset* is the active current setpoint. Assuming that the output voltage Vopk is regulated at the nominal value during all times, then (Vopk = E*). By substitution

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

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M.A. Aboushal, Mohamed M. Zakaria Moustafa

in (10), it yields the following current droop relation as defined in (11).   Iref;mag ¼ IrefPK
mp  Iopk
Iset ð11Þ

the power terms. Accordingly, it offers higher simplicity, better robustness against disturbances and load transients, and faster dynamic response in contrast to VCMs.

However, the control robustness must be enhanced to ensure that the voltage is strictly regulated as assumed above. Therefore, the structure of voltage controlled URDC introduced by [18,21] has been manipulated to extend the same concept to the proposed RCDC as shown in Fig. 2. Thus, a parallel branch has been added through which the integrated voltage error is always aggregated with the reference current magnitude ensuring voltage regulation at all times. Hence, (11) is manipulated as per (12). Z   Iref;mag ½n ¼ IrefPK ½n þ ½
m  Iopk
Iset þ Ke

3.1.2. Current regulator used in the inner control loop.

   E
Vopk dt

p

ð12Þ

where Ke is the integral gain for the voltage error. The current error can be expressed as given in (13).     ð13Þ Iref _error ¼
mp Iopk
Iset þ Ke E
Vopk At the steady state, Iref _error ¼ 0 which yields;     mp  Iopk
Iset ¼ Ke E
Vopk

ð14Þ

Thereby, once the output voltage is regulated at the steady state, then the active current term (mp  [Iopk
Iset*]) is maintained constant for all parallel inverters. This ensures proportional sharing of output active current without pre-knowledge of the EFLIs and regardless of their per unit output values. Consequently, the controller presented in (12) goes in the same line with the original VCM based UDC. The only difference is that the former is current regulated replacing the (P vs. E) droop equation defined by (6). Moreover, it holds the same universal droop characteristics complying with different types of EFLIs, including L-, R-, RL-, C-, and RC-inverters. Furthermore, for better voltage regulation, the proposed method takes advantage of the droop controlled strategies presented in [9,18] for introducing a robust current droop controller as presented in Fig. 2. Thus, the active current is controlled directly instead of using the power term (P) while the voltage regulation is maintained. Hence, unlike droop based VCMs, the introduced strategy obviates the unnecessary delays belonged to the measuring process and signal conditioning of

Fig. 2

On the other side, the reactive current sharing is fulfilled by passing the reference current magnitude calculated by (12) to a proportional resonant (PR) controller implemented in abSTF as depicted in Fig. 3. The key idea beyond selection of PR current regulator is that it holds many advantages over other similar approaches like those reported in [18] using PI regulators. First, it offers a precise reference current tracking for AC signals with almost null steady state error opposed to PI regulator owing to the high gain around the resonance frequency [9,13,14]. More importantly, it holds an intrinsic characteristics forming a reactive droop controller by itself, thus it naturally manipulates the frequency in matching with any reactive load change [9]. This way, only one droop function can be implemented in the outer loop just for the active current as per (12), while the output reactive current is controlled intrinsically through the inner QPR regulator. This obviates the employment of two droop function in case of using PI regulators [18]. Besides, natural droop response is supported corresponding to any reactive load variation contrary to PI controllers implemented in dq-SRF which require an external reactive droop function with a pre-defined reactive power setpoint as per (6). Additionally, PR regulators do not necessitate voltage feedforward cross-coupling terms like PI controllers for power decoupled control [9,12–14]. Furthermore, PR controllers are immune to low order harmonics nearby to zero frequency in contrary with PI regulators. An ideal PR regulator can be defined by the transfer function given in (15) as follows;
 2ki s Gc ðsÞ ¼ kp 1 þ 2 ð15Þ s þ xPR 2 where xPR is the resonant frequency of the controller. kp and ki are the proportional and resonant gains of the regulator, respectively. Note that since the PR current controller achieves close to zero current tracking error, then Iopk in (12) can approximately be substituted by Iref,mag [n
1] as depicted later in Fig. 6. Additionally, it has been highlighted in [13,14] that undesired harmonics may appear close to the resonant frequencies according to the closed loop frequency response of ideal PR

The proposed RCDC for updating the reference current magnitude according to the load sharing strategy.

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

Hybrid droop scheme

7

Fig. 3

Block diagram of the implemented QPR current regulator.

regulator. This results in high sensitivity of the PR controller pursuant to any slight frequency variation which may cause a significant loss of performance. Therefore, a non-ideal or so-called quasi-PR controller is adopted instead as given below.
 2ki xc s G c ð s Þ ¼ kp 1 þ 2 ð16Þ s þ 2xc s þ xPR 2 where xc is the cut-off frequency of the QPR regulator. Note that the converter-side current (ILabc) exposed in Fig. 1 has been chosen as the controlled variable instead of the grid/load side current (Ioabc). This selection is based on that the control of the inductor current ILabc usually results in stable operation over wide range of selected controller gains. Moreover, feeding-back the converter side current adds an inherent damping effect for the resonance introduced by the LC filters [34]. The block diagram of the adopted QPR regulator is depicted in Fig. 3. The reference current vector Irefab (t) is compared with the converter-side current ILabc (t). Thus, the error is continuously addressed by the QPR current regulator. The latter is implemented through the structure of second order generalized integrator [13,14,16], as defined in (16). Hence, the QPR regulator yields the reference voltage vector (Eref_ab) which is transformed back to the three phase abc-natural frame using inverse Clarke transformation [11,14,35]. Accordingly, the generated reference voltage vector (Eref_abc) is processed through a pulse width modulator (PWM) as shown in Fig. 3 creating the duty cycles of the driving patterns (Mabc) for the inverter’s gating signals. 3.2. Generation of the reference current angle (hiref) The current phase angle is generally commanded through two main approaches. The first approach depends on a common external frequency clock which shares the nominal operating frequency as per (17) through an external low BW communication link [4,7,8]. Z hiref ðtÞ ¼ xnom dt ð17Þ where hiref is the commanded current phase angle, xnom is the MG nominal angular frequency. However, this approach raises reliability concerns, where the communication links limit the decentralized controllability, besides the need of a perfect synchronous clock to ensure synchronism. Furthermore, power generation at unity PF cannot be maintained as the current phase angle is shared by the synchronous clock irrelevantly of the corresponding output voltage. This

detrimentally affects the reactive power sharing accuracy among CCVSIs [9]. For more adequacy, another communication-less based approach has been adopted within the proposed control scheme to offer better plug and play operation. Using SRFPLL, each CCVSI is rendered to follow the phase angle of its output voltage. The basic concept is that the frequency of the output voltage is a global variable in the MG. Hence, by controlling the reference current angle to be the same as the output voltage waveform according to (18) and (19), then each DG become self-synchronized with the MG’s network. Z hiref ðtÞ ¼ hv ðtÞ ¼ ðxnom
xerr Þdt ð18Þ where hv is the phase angle of the DG output voltage. xerr is the angular frequency error generated by the loop filter of the SRF-PLL and can be calculated as defined below in (19).
 Z xerr ¼
kpL  Voq þ kiL Voq dt ð19Þ where kpL and kiL are the proportional and integral gains of the loop filter. Note that SRF-PLL has been selected among different types of PLLs, as it holds the simplest form while sufficiently supports the requirements of the proposed control system [35]. Therefore, through only one transformation as given in (1), Voq is employed to easily measure the output voltage phase angle. Accordingly, the implemented method enables parallel inverters to become self-synchronized with the MG network during ISM using local parameters. On the other side, upon resynchronization with the main grid, any small voltage deviation between the inverter’s output voltage and the main grid voltage will lead to high inrush currents. Therefore, hiref should be synchronized with the main grid voltages (Vgab) instead of the inverter’s output voltage sine waveform or sin (hv). Prominently, no additional PLL is required to measure the grid angle hg. Thanks to the implementation of the control system in ab-STF, then the per unit (pu) values of the filtered grid voltages Vgab could be used directly as a template for the reference currents [35,36]. Accordingly, an integrated synchronization method which considers both ISM and GCM, is implemented as shown in Fig. 4. The switch (Sg) waits for the trigger signal released by the detected zero-crossing of the grid voltage. Then, it toggles the output value such that reference currents follow the sine waveforms of the grid voltages as illustrated in Fig. 4. This simplifies the control scheme by obviating the need of further PLLs and enhances the system stability, especially that multiple PLLs tend to compete with each other when employed in one system leading to additional stability concerns. Accordingly, the proposed approach offers

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

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M.A. Aboushal, Mohamed M. Zakaria Moustafa

Fig. 4

Generation of the reference current angle (hiref) using SRF-PLL.

a self-synchronized local process during all modes with no need of communication links among parallel inverters for sharing the reference current angle. Besides, the output power is always generated at unity PF opposed to the external synchronous clock-based approaches. Comparing the proposed approach with the RCDC that discussed in [18]. The latter used one fast Fourier transform (FFT) to calculate the output voltage angle hv, which has been employed in further estimations for the output active and reactive currents Ip and Iq, respectively. This yields two drawbacks which are avoided through the proposed control scheme. First, FFT based PLL needs a buffer for one cycle to be locked to the measured signal after transient occurrence [37]. Second, the implemented approximations limit the current sharing accuracy offered by that approach. Thus, any incorrect phase information by FFT-PLL may deteriorate the quality of the shared current at the PCC resulting in unacceptable current distortion. In contrast, the adopted SRF-PLL is more adequate due to having no correlation to the measured AC output currents which are transformed to the ab-STF. Additionally, the proposed approach offers better simplicity as the reactive current is controlled intrinsically by the QPR inner regulator, thus only one droop controller is used instead of the two controllers for Ip and Iq.

within the allowable standard limits of EMC- (EN 61000) as demonstrated in Table 1 [32,33]. This objective is achieved through a decentralized secondary control action which is processed locally by each DG with no trade-off between quick dynamic response and system stability. A simple PI controller has been utilized to speed-up the frequency restoration as given below in (20). 
 kir fPR ðtÞ ¼ fnom þ ðfnom
fvDG ðtÞÞ  kpr þ ð20Þ s where fvDG is the output voltage frequency obtained from SRF-PLL. kpr and kir are the proportional and integral restoration gains of the decentralized controller. Consequently, the proposed hybrid controller regulates the output voltage and frequency, such that their rapid variations per each DG are restricted to ±3% and ±2, respectively. 4. Proposed overall RCDC-QPR hybrid structure and respective control parameters Based on the above-mentioned sections, the entire control system is implemented in ab-STF as shown below in Fig. 6. As

3.3. Fast frequency tracking for restoration Considering that the used QPR is intrinsically a reactive droop controller, then it essentially manipulates the frequency in matching with any reactive load change. Therefore, an additional improvement is addressed through a fast frequency restoration (FFRES) loop as shown in Fig. 5 in order to retrieve the output frequency as well as the reactive power flow

Fig. 5

Frequency restoration block diagram.

Table 1 Voltage characteristics of power distribution systems according to EMC- (EN 61000) standards [32,33]. Parameter

LV characteristics according to EN 61000

Power frequency variations* Voltage magnitude variations** Rapid voltage changes

2% 10% applied for 15 min 3% normal, 8% infrequently. Psta < 1.0, Pltb < 0.8

* For power frequency variations, the fundamental component is measured over 10 s to obtain mean value. ** Meanwhile, the voltage magnitude rms values are measured over 10 min to calculate the mean value for voltage magnitude variations. a Short-term severity (Pst) measured over a period of (10 min). b Long-term severity (Plt) obtained from a sequence of (12 Pst) measured over a period of two-hour interval, such that qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 P12 Psti 3 Plt¼ i¼1 12 .

Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006

Hybrid droop scheme

Fig. 6

9

Block diagram of the proposed overall control scheme using a hybrid RCDC-QPR arrangement.

explained in Section 3.1, only voltage transformations from ab to dq-SRF are used as given (1) for further calculations of the output voltage magnitude Vod. Then, the reference current magnitude is calculated according to (2) and (3) using the scaling multiplier, namely Vratio. Hence, the adjustable reference magnitude Iref,pk [n] is then passed to the RCDC which determines the shared active current by generating a new reference magnitude Iref,mag [n] as per Section 3.1.1. In turn, the updated magnitude Iref,mag [n] is multiplied by the reference current angle (hiref) which is calculated through the introduced synchronization method in Section 3.2. As explained, hiref is controlled to follow the locked value of the output voltage phase angle hv during ISM. Meanwhile, upon resynchronization with the main grid, Vgab are directly used as a template for hiref. This offers a self-synchronization capability for parallel inverters with plug and play operation, while maintaining the output power at unity PF. Then, the current reference vector [Irefab(t) = Iref,mag [n]  sin(hv)] is tracked through a QPR current controller as shown in Fig. 3 for elimination of the steady state error. Additionally, it drives the gating signals of the power switches with varying frequency pursuant to the intrinsic droop characteristics of the QPR controller itself in order to match with the shared reactive load. Upon any frequency change, the restoration block acts accordingly to retain the frequency at the nominal value by changing the resonant frequency fPR(t) of the QPR current regulator as demonstrated in Section 3.3. Thus, the accuracy of reactive power sharing is preserved which maintains the MG stability. Finally, PWM patterns (Mabc) are generated by the QPR regulator for the inverter’s gating signals as shown in Fig. 6. The criteria of selection for the control system parameters belonged to the proposed approach are elaboratively discussed in the following sub-sections.

age term [Ke  (E*
Vod)] in (12) compensates for any current increase making it impermissible for further current contribution. Meanwhile, during GCM, the reference current I*set is precisely tracked by the proposed controller for sharing the common loads while the excess power is injected to the main grid. On the contrary, the VCM based UDC which is given by (6) and (7) can be recognized by two modes, namely droop mode (DM) and set mode (SM) [18,21]. Switching between the two modes must be performed by adjusting the power setpoints P* and Q* corresponding to each mode as described in (22).

For GCM=SM : P ¼ Prated For ISM=DM : P ¼ 0:0

and and

Q ¼ Qrated Q ¼ 0:0

ð22Þ

Hence, SM is basically employed when the main grid is interconnected, where P* and Q* are adjusted according to the desired amount of power injection or absorption with the main grid. On the contrary, during MG islanding, DM is used such that P* and Q* are made equal to zero, thus the inverters share the load in proportion to their power ratings. However, the drawback of this perception is that it requires setpoint manipulations according to the MG operating modes which is avoided by the proposed RCDC-QPR hybrid scheme. 4.2. Tuning the gains of the inner current regulator The gains kp and ki for an ideal PR controller can be calculated as described in (23). Thus, for any given phase margin (PM), the maximum cross-over frequency is estimated for achieving the best possible transient response as discussed in [9,15,38]. p=2
Um ¼ ! Td

(

xcðmaxÞ Lf Vdc x ki ¼ cð10maxÞ

kp ¼

4.1. Peak current set point (Iset*)

With xcðmaxÞ

A good feature of the proposed structure is that a fixed value for the peak current set point can be adjusted during all modes. For instance, Iset* can be made equal to the inverter’s rated current Irated.

where xc(max) is the maximum angular cut-off frequency of the PR regulator, Td is the SCD, Vdc is the DC bus voltage, and Um is the PM. By applying the adopted QPR structure instead of ideal PR controller, the proportional gain kp has been maintained the same as given in (23), but the resonant gain ki should be manipulated as shown below in (24).

Iset ¼ Irated

ð21Þ

By substitution from (21) in (12), then during ISM all DGs will share the common loads in proportion to their rated currents. Once the output current matches with the load, the volt-

ki ¼

xcðmaxÞ 1  10 2xc

ð23Þ

ð24Þ

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10

M.A. Aboushal, Mohamed M. Zakaria Moustafa DG1 is assumed to be double rated as DG2. Hence, the gains of the unit DG2 will be calculated as follows;

4.3. The system synchronization limits To enhance the performance of the hybrid RCDC-QPR scheme, the system output voltage and frequency should be maintained within the standard synchronization limits. From (13), it yields; Vopk ¼ E
Vdrop E

ð25Þ

mp  Iopk Ke E 

ð26Þ

Similarly, the output frequency is subjected to linear boost droop characteristics supported by the QPR regulator [9], such that; x ¼ x þ fboost x

ð27Þ

where, fboost is the frequency boost ratio which is given as described below in (28). fboost ¼

kp  Ioq ki x 

ð30Þ

kp2 ¼

Ibase  kp Irated2

ð31Þ

mp ¼

Vdrop  Ke E Ibase

ð32Þ

Meanwhile, the reactive droop coefficient is determined by the gain kp of the QPR regulator as defined in (23). Since that (Irated2 = 0.5  Irated1), then (31) and (32) can be rewritten as follows. Ibase  mp ¼ 2  mp1 1=2  Irated1

ð33Þ

IIbase   kp ¼ 2  kp1 1=2  Irated1

ð34Þ

mp2 ¼ 

ð28Þ

Ioq is the quadrature axis of the inductor output current as defined by (29).
Ioq ¼ ½
sinðhv Þ cosðhv Þ  

Ibase  mp Irated2

In this context, the droop coefficient mp can be derived from (26) as follows.

where Vdrop is the voltage drop ratio as given below. Vdrop ¼

mp2 ¼

ILa



ILb

ð29Þ

Note that the reactive current is intrinsically controlled by the QPR regulator without a dedicated droop controller in the outer loop. From (25)–(29), the synchronization limits determined by the drop/boost ratios can be adjusted independently of the droop coefficients mp and kp, where the gains Ke and ki are used alternatively for this purpose as per (26) and (28). Thus, the higher the gains Ke and ki, the smaller voltage and frequency deviations can be achieved. Accordingly, the proposed controller regulates the output voltage and frequency within the acceptable limits, such that their rapid variations per each DG are restricted to ± 3% and ± 2%, respectively as per the EMC standard- (EN 61000) for LV distribution systems [32,33]. 4.4. Scaling the droop coefficients for proper load sharing However, to ensure proportional power sharing among parallel VSIs, different cases have been considered. In case of typically rated VSIs, the influencing gain parameters, namely mp and kp must be maintained the same for all DGs to obtain similar active and reactive droop characteristics. On the other side, in case of different power ratings, the gains must meet the conditions described earlier in (4) and (5), respectively. To achieve this objective independently of the MG network unknown parameters, a scaling approach is subjected to the hybrid RCDC-QPR control scheme in order to adjust the gains mp and kp with respect to a global base value. The latter can be made equivalent to the largest VSI’s rated current within the MG. For example, assuming that the unit DG1 shown in Fig. 1 has the largest nominal current Irated1, then the base value (Ibase) will be set equal to this value. In the following

kp2 ¼ 

From (33) and (34), the proposed approach essentially meets the conditions inferred from (4) and (5). Accordingly, depending on the rated current value which is a local known parameter, each DG unit can proportionally share the active and reactive load current pursuant to their power ratings without knowledge of the other DGs’ ratings as well as the MG uncertain parameters. Furthermore, the proposed scheme advantageously enables decoupled control for output active and reactive currents during both ISM and GCM. For instance, the active power contribution of jth DG can be set equal to 50% of the total active load demand, meanwhile the reactive power can be separately shared at a percentage 67% of total load. The former is adjusted through the droop gain mp of the RCDC independently of the latter which is regulated via the QPR current regulator’s gain kp. This is notably achieved even if the droop coefficients of other interconnected DGs are unknown. These advantages are clearly exhibited and discussed in the simulation results of the proposed case study. 4.5. Tuning the gains of the implemented SRF-PLL It is worth noting that the current magnitude estimator mentioned in section 3 uses the measured voltage phase angle as inferred from (1). Therefore, the measuring accuracy of hv using SRF-PLL has an impact on the controlled active and reactive currents. Hence, the gains of the loop filter must be tuned properly to ensure control precision and system stability [14,36]. Relying on the frequency response of the controlled system, a simple tuning method has been followed. Given the open loop transfer function (OLTF) as per (35) for the linear model of SRF-PLL in frequency domain [14], it yields; Vod HðsÞ ¼ LðsÞ  ¼ |ffl{zffl} s |{z} Loop filter


 kiL Vod kpL þ s s

ð35Þ

VCO

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Hybrid droop scheme

11

The settling time (tsl) of the PLL output within 2% of the reference in the steady state can be estimated as follows. tsl ¼

4 fxm

ð36Þ

where xm is the cross-over frequency of the loop filter. f is the damping ratio of the PLL which is determined by the PM as given below in (37).
 PM ð37Þ For PM < 70A ! f  100 From (36), increasing xm reduces the settling time and enhances the PLL transient response. However, higher BW determined by xm results in poor filtering in the steady state. Thus, PM must be increased as well to attenuate the overshoots emerged in the output via larger f as per (37). Therefore, the frequency response of OLTF defined in (35) has been addressed as demonstrated in Fig. 7 by setting the PM to 90° at (xm = 1 kHz). This provides enough PM suitable for attenuation, while the selected value for xm is still limited within 5% of the measurement sampling frequency in order to avoid system oscillatory response at the steady state. Consequently, the gains kPL and kiL have been tuned, such that the overshoots emerged by the PLL are efficiently attenuated without compromising the system quick dynamics. 5. Simulation results and discussion The network and control system parameters are listed in Table 2. Note that the MG architecture shown before in Fig. 1 for the case study is resistively coupled, where the ratio (R/X) belonged to the tie-line impedance is generally adopted around (’7.7) for low voltage power networks as indicated in [9,10]. As illustrated in Table 2, high PM (Um = 80°) has been selected for good damping capability and small frequency deviations by the QPR current regulator. Moreover, the processing capacity used in simulation is set equal to 20 kHz, hence the SCD has been evaluated by one and a half measurement sampling time, i.e. Td or [n] = 1.5  Ts. Accordingly, Td has been

Fig. 7

Table 2

Network and control system parameters.

Parameter

Value

Zline1/Zline2 Srated1/Srated2 Vline/fnom Vdc Lf1,2/Cf1,2 Td Um xc kp1,2 Ki1,2 Ke1,2 mp1,2 KpL1,2/KiL1,2 Kpr1,2/Kir1,2

0.5 + j0.0658/0.25 + j 0.0329 X 12.0/6.0 kVA 380 Vrms/50 Hz 400 V 4 mH/5 lF 75  10
6 80° 2p  2 rad/sec 0.0233 3.7037 0.5 0.1815 20/200 5/500

set to 75  10
6, such that the modulated frequency is made slower than the measurement sampling frequency (20 kHz) in order to avoid system oscillatory response as well as mitigating the need of higher processing speed. This ensures good system dynamics as mentioned in pervious publications in the same field [9,15]. The rest of control parameters listed in Table 2 follow the criteria of selection which is elaboratively discussed in Section 4. To reveal the effectiveness of the proposed hybrid control scheme, different simulations have been performed using the elaborated scenario in Table 3. First, the performance of the hybrid control system using the adopted QPR regulator is analyzed showing its merits over the conventional ideal PR arrangement as depicted in Figs. 8 and 9. As delineated in Table 3, the simulation starts in ISM, hence the common loads are shared through only two parallel DG units as per Fig. 1. During the interval period (from 0.2 to 0.6 s), the main grid gets into service taking over the supply of the reactive loads in the MG. Whilst, the active

Frequency response used in tuning the gains of the adopted SRF-PLL.

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12

M.A. Aboushal, Mohamed M. Zakaria Moustafa

Table 3

The simulation scenario.

Parameter

Value

Simulation time (s)

Pload/Qload

6.0 + j2.0 kVA 12.0 + j4.0 kVA
6.0 + j2.0 kVA 6.0 + j2.0 kVA 50/50% 66.6/33.3%

From 0.6 From 1.0 From 0.4 From 0.6 From From 1.0

Pgrid/Qgrid

Power sharing percentage between DG1/DG2

0.0 to 0.6 to 0.2 to 0.4 to 0 to 0.8 0.8 to

load currents are shared equally between the two parallel inverters while injecting the excess active current to the main grid. After (0.4 s), the common loads become entirely supplied by the main grid. Thereafter, the MG returns to ISM at (0.6 s) while having the common loads doubled at the same time in order to validate the system performance under such heavy transient condition plus verifying seamless transition between

Fig. 8

GCM and ISM. Finally, the proportional load sharing is verified by varying the sharing percentage between the two parallel inverters. With reference to Fig. 8(a) and (c) the transient response is remarkably enhanced with the use of QPR regulator. It exhibits damped overshoots and null steady state error for both the output active and reactive powers shared by the two parallel DGs. Additionally, although different impedances are connected to DG1 and DG2 per each tie cable, however the output active and reactive power is equally shared between the two units without overloading the nearest inverter to the PCC, which belongs to DG2. This proves the provision of regulated voltage and high accuracy of power sharing through the presented robust current droop controller. Upon grid penetration at (0.2 s), the current controller directly injects the excess active current into the main grid. In the meantime, the output active and reactive powers are not disturbed during transition from ISM to GCM showing minimal distortion with no remarkable overshoots at the coupling instance. After that, the inverters stopped power injection to the main grid, as the active current setpoint is brought back to zero (from 0.4 to 0.6 s). Then, the grid outage simultaneously occurs with the common load doubled at (0.6 s) forming a heavy transient condition according to

Shared output active and reactive power of DG1/DG2, respectively. (a), (c): using QPR regulator. (b), (d): using conventional PR.

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Hybrid droop scheme

13

Fig. 9 Comparing the system performance using QPR vs. ideal PR regulator with respect to the output frequency and output inductor’s phase current belonged to DG1/DG2, respectively. (a), (c): using QPR regulator. (b), (d): using ideal PR regulator.

the simulation scenario listed in Table 3. It is shown that the output active and reactive powers automatically respond increasing from zero to (12.0 + j4.0 kVA) in matching with the common loads during the interval period (from 0.6 to 0.8 s). Additionally, it is noted that seamless transition from GCM to ISM has been achieved without exposure to high output overshoots or large oscillations. This emphasizes that the proposed current controller offers a unified strategy that efficiently operates during both ISM and GCM yielding almost null steady state error, small rising time, mitigated transients, and damped overshoots. Thereafter, the proposed hybrid RCDC-QPR structure seamlessly varies the sharing response between DG1 and DG2 from equal sharing percentage (50– 50%) to proportional sharing (67–33%) matching with the power rating of each DG. Hence, a decoupled control between active and reactive current has been successfully achieved by scaling the corresponding droop gains as explained in Section 4.4. In contrast, by embedding an ideal PR regulator to the proposed control scheme, it generates larger settling time, higher overshoots, in addition to undamped oscillations emerged within both the output active and reactive powers as shown in Fig. 8(b) and (d). Furthermore, the system response using ideal PR controller is more vulnerable during transition to GCM producing intolerable reactive power overshoots that may lead to entire system instability.

Further comparisons have been performed showing the output frequency and output phase current passing through the filter’s inductor as presented in Fig. 9. Obviously, the obtained results reflect the same performance similar to Fig. 8 indicating equally shared currents between DG1 and DG2 with a percentage (50–50%) in the time interval (from 0 to 0.8 s). Following the simulation scenario, the currents have been proportionally shared with a percentage (67–33%) validation the system controllability in matching with the power rating of each DG during the interval (from 0.8 to 1 s). It was noticed that upon reactive load transients, high oscillations appear in the output frequency regulated by the PR controller as shown in Fig. 9 (b). As ideal PR controller is very sensitive to any frequency variations, then it further generates an oscillatory output phase current as demonstrated in Fig. 9 (d) imposing higher limitations on the system stability. In contrast, this side effect is less significant for both the output frequency and inductors’ currents using the QPR configuration as demonstrated by Fig. 9 (a) and (c). The QPR regulator has efficiently limited the output currents resulting in less oscillatory response upon load transient contrary to ideal PR current regulator. Note that frequency variations are normally manifested during load transients, resonant harmonics and disturbances at the point of common coupling (PCC), thus they can be rather mitigated. However, they cannot be totally avoided. Addition-

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14

M.A. Aboushal, Mohamed M. Zakaria Moustafa

ally, although the intrinsic droop characteristic of the PR controller is a beneficial feature, however it adds to the system sensitivity. Considering that the PR controller itself disturbs the output frequency till meeting the reactive load requirement in the steady state. Hence, this feature makes the system performance even worse unless QPR structure is adopted instead to mitigate this backfire. The adopted estimation method for adjustable reference current magnitude is compared with that reported in [9]. From Fig. 10(a), it is clear that the predictive multiplier Vratio is precisely calculated showing no remarkable oscillations even under heavy load transients at 0.6 s. Note that the same has been already proven through Fig. 8(a) and (c), where the hybrid control system automatically updates the output active and reactive currents in matching with the supplied load during both ISM and GCM. Additionally, load matching and voltage regulation using the proposed CCM have been effectively addressed even during the absence of GSVS, in contrast to the general hypothesis that CCVSIs cannot be operated in

Fig. 10

parallel during ISM [4–11]. This way, the proposed approach represents a simple remedy for the inertia-less nature of three phase VSIs, where the reference current magnitude is automatically adapted according to the amount of load change, which is reflected by the predictive multiplier, namely Vratio. Accordingly, an approximate natural response could be achieved. On the contrary, the voltage estimation technique indicated in [9] results in higher oscillations within the value of Vratio as depicted in Fig. 10(b). This occurs due to the inaccurate assumption used, where approximate phase angles equal to (±20°) are adopted in nearby to zero angle (0°) for avoiding division over zero-crossings. As a result, distortions are emerged in the calculated voltage multiplier Vratio which in turn produces further oscillations in the commanded reference current magnitude. Moreover, as explained before as the output frequency is intrinsically changeable by the QPR regulator, then a secondary control action was required to restore the frequency to its nominal value. Hence, the proposed decentralized

Measured output voltage ratio: (a) using the adopted direct axis voltage Vod (b) using the approximation method indicated in [9].

Fig. 11 Output frequency using the proposed hybrid control structure: (a) with the FFRES loop embedded to the system (b) without using restoration block.

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Hybrid droop scheme FFRES has been compared with unrestored frequency-based system. As illustrated in Fig. 11(a), the output frequency restoration has been accomplished within two cycles (0.04 s) or less after each transient condition according to Table 3. Additionally, the frequency has been kept within the limits bounded by ±1 Hz as per EMC- (EN 61000) standards with no trade-off between quick dynamic response and system stability. Hence, the system avoids the high circulating reactive currents caused by large frequency deviations or slow restoration process which proves the robustness of the newly presented RCDC-QPR hybrid controller. On the contrary, when the restoration bock is unused, i.e. (xPR) is directly set equal to (xnom), then the output frequency is continuously changed by the QPR controller as indicated in Fig. 11 (b) for compliance with different reactive loading conditions as per Table 3.

15 Besides, it highly deviates from the allowable synchronization limits which must be respected as explained. The control system stability using the adopted SRF-PLL has been also investigated. Fig. 12 (a) and (b) depicts the instantaneous output phase voltage (vo1a) versus its output phase angle (xvDG t = hv), respectively. It is obvious that output phase angle extracted by the SRF-PLL is precisely locked to inverter’s output voltage. Moreover, the input and output signals of the SRF-PLL shown before in Fig. 4, namely
Voq,
xerr, and xvDG are demonstrated in Fig. 13 (a), (b), and (c), respectively. The results indicated that the input voltage error (
Voq) is finely filtered through the loop filter of the SRF-PLL yielding the angular frequency error (xerr) which is then subtracted from the nominal value. As long as xerr becomes closer to zero, the output angular frequency xvDG reaches the steady

Fig. 12 System response using SRF-PLL embedded to the proposed hybrid control structure. (a) Instantaneous output phase voltage vo1a, (b) Instantaneous phase angle of output voltage (xvDG t = hv).

Fig. 13 Input and output signals of the employed SRF-PLL. (a) Error signal of the quadrature axis voltage component (
Voq). (b) Angular frequency error (
xerr) generated by the loop filter of the PLL. (c) Output angular frequency (xvDG) extracted by the used SRFPLL.

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16

M.A. Aboushal, Mohamed M. Zakaria Moustafa

state value. It is obvious that the entire system exhibits good performance under the employment of the adopted SRFPLL. In addition, the MG stability is preserved during both transients and steady state as shown in Figs. 12 and 13, respectively. Additionally, the output voltage and frequency deviations are restricted to ± 3% and ± 2%, respectively from their nominal values which proves the compliance of the proposed approach with the standard limits of EMC- (EN 61000) [32,33]. In summary, the proposed RCDC-QPR hybrid scheme offers a unified control strategy which uses only a single current droop controller and single current regulator during all modes of the MG. Hence, it offers better system dynamics, stability, design simplicity, and less dependency on network parameters uncertainties as inferred from the presented simulation results. In addition, regulated voltage levels and frequency are dispersedly maintained per each DG without compromising the system quick response upon any change of the loading conditions at the PCC. 6. Conclusion A new current-controlled strategy has been introduced in this paper to overcome the limitations of the conventional droop based VCMs. The significance of this research has been characterized by four major contributions. Firstly, direct control over current has been supported during ISM in order to improve the output power quality and dynamic response without the need of dual-voltage loop architecture in contrast to the literature. Thus, the proposed CCM has efficiently operated during all modes showing no remarkable oscillations, overshoots, or circulating currents between parallel inverters during the transition from GCM to ISM and vice versa. This emphasises that MG transitions are handled seamlessly using the proposed unified architecture. Secondly, the reference currents have been scaled automatically in matching with heavy load transients during transition from GCM to ISM. Additionally, despite of having different coupling impedances, the power sharing accuracy between parallel inverters have been maintained while regulating the output voltage level. This proves the control robustness against the inertia-less nature of VSIs independently of the network parameters uncertainties. Thirdly, thanks to the adoption of QPR regulator instead of ideal PR structure used by prior approaches, the system immunity against the emerged frequency variations in the MG has been significantly improved. Fourthly, the design complexity has been remarkably reduced compared to the literature, where the proposed unified strategy avoids the need of fast islanding detection and switching events between different controllers according to the MG’s operating mode. Moreover, the total number of control loops is reduced, where the inner voltage regulator as well as the outer reactive droop controller have been eliminated in contrast to the voltage controlled URDC. Comparative simulation results have been presented using MATLAB/ SIMULINK showing the competency of the proposed method in satisfying the MG regulations. Declaration of Competing Interest The authors declared that there is no conflict of interest.

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Please cite this article in press as: M.A. Aboushal, M.M.Z. Moustafa, A new unified control strategy for inverter-based micro-grid using hybrid droop scheme, Alexandria Eng. J. (2019), https://doi.org/10.1016/j.aej.2019.10.006