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A note on the VLSI counter
Information Processing Letters 22 (1986) 193-195 North-Holland
17 April 1986
A N O T E O N T H E VLSI C O U N T E R B. C O D E N O T T I Istituto di Elaborazione dell'Informazione, Consiglio delle Ricerche, Via S. Maria 46, 56100 Pisa, Italy
G. L O T T I Dipartimento di Scienze dell'lnformazione, Unioersity of Pisa, Corso Italia 40, Pisa, Italy
Communicated by W.L. Van der Poel Received 8 May 1985
Keywords: VLSI model, area-time complexity, counter, lower bound
1. Introduction
of I n / q ] variables (see, for example, [1,2]). F r o m (1) and (2) we obtain
In this note, the area-time complexity of a VLSI c o u n t e r is studied. Both a lower and an upper b o u n d are derived which meet to within the exponent of the logarithmic factor. The proposed VLSI design derives from the parallel c o u n t e r presented by Muller and Preparata [3], which requires O(log n) delay time and O(n) n u m b e r of elements. A n area of order n l o g 2 n will be shown to suffice for the VLSI network and a lower b o u n d to A T 2 of order n log n will also be proved.
2. Lower bound
(1)
and T >t q - 1 + l o g [ n / q ] ,
+ 2n l o g ( n / q ) } ), that is, A T 2 = f~(n log n), since the m i n i m u m is attained for q = O(log n). N o t e that, in the case of m a x i m u m parallelism (q = 1), the lower b o u n d is of order n log 2 n.
3. VLSI design
In this section, a lower b o u n d is shown which meets the area × (time) 2 complexity of the design presented in the next section up to the exponent of the logarithmic factor. Indeed, if I n / q ] bits are sent at the same time, the following relations hold: A >t I n / q ]
A T 2 = fl( min {nq + n / q l o g 2 ( n / q ) q
(2)
since f ~ ( l o g [ n / q l) steps are required in any computational model to c o m p u t e a nontrivial function
Let x 1, x 2 , . . . , x n be a configuration of O's and l's. A parallel counter with input xa, x 2 xn gives as output the binary representation d o , d 1. . . . . d m o f the n u m b e r of l's in the input configuration. The basic element of the parallel counter is the adder element which has three inputs a~, b i, ci_~ and two outputs d~, c i, where . . . . .
d i = (aibiVaibi)c.i_lV(aibiVaibi)ci_l, c i --- (aiVbi)Ci_lVaib i. The connections a m o n g the basic elements are
0020-0190/86/$3.50 © 1986, Elsevier Science Publishers B.V. (North-Holland)
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17 April 1986
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Fig. 4.
Fig. 1.
not in a p l a n a r geometrical configuration and each element has five connections (see Fig. 1) [3]. In order to give the VLSI design for this parallel counter, we associate to any basic element (adder) a PE (processing element) requiring two units of area with five wires c o n n e c t e d as shown in Fig. 2, each sending the information in one direction only. It is easy to see that the network can be laid out by using the three PEs shown in Fig. 3, which differ from each other only for the wires' direction.,, Let us assume n = 2 m + l - I SO that the parallel
counter is composed of adders only. We want to study the behaviour of the area of the layout with respect to n. In Fig. 4 a recursive VLSI design is shown where modules of type I are counters of dimension 2 m - 1 and a module of type II performs the final stages as specified in [3]. With the aid of Fig. 5, in which the case n = 15 is illustrated, it is easy to see that m o d u l e II can be laid out in a rectangle of O(m) width and O(m) height. Assuming that at every stage all the input (output) nodes lie on the b o u n d a r y of the chip, we obtain an upper b o u n d of order n log 2 n for the area of the chip. Let wm and h m be respectively the width and
Fig. 2.
Fig. 3. 194
Fig. 5.
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the height r e q u i r e d to l a y o u t the c o u n t e r o f dim e n s i o n n = 2 m+l - l ; f r o m the r e l a t i o n s w m = wm_l + O ( m ) , hm = m a x { 2 h ~ _ l
+ O(1), O(m)},
it follows t h a t A = O ( n log 2 n), f r o m w h i c h A T 2 = O ( n log 4 n). T h e design is t h e n o p t i m a l u p to the e x p o n e n t o f the l o g a r i t h m i c term.
17 April 1986
References [1] L. Csanky, Fast parallel matrix inversion algorithms, SIAM J. Comput. 5 (1976) 618-623. [2] R.B. Johnson, Jr., The complexity of a VLSI adder, Inform. Process. Lett. 11 (2) (1980) 92-93. [3] D.E. Muller and F. Preparata, Bounds to complexities of networks for sorting and for switching, J. ACM 22 (1975) 195-201. [4] C.D. Thompson, Area-time complexity for VLSI, Proc. llth Ann. ACM Symp. on the Theory of Computing (SIGACT) (1979) 81-88.
Acknowledgment T h e a u t h o r s w o u l d like to t h a n k Prof. F. Prep a r a t a for i n s p i r i n g this research.
195
17 April 1986
A N O T E O N T H E VLSI C O U N T E R B. C O D E N O T T I Istituto di Elaborazione dell'Informazione, Consiglio delle Ricerche, Via S. Maria 46, 56100 Pisa, Italy
G. L O T T I Dipartimento di Scienze dell'lnformazione, Unioersity of Pisa, Corso Italia 40, Pisa, Italy
Communicated by W.L. Van der Poel Received 8 May 1985
Keywords: VLSI model, area-time complexity, counter, lower bound
1. Introduction
of I n / q ] variables (see, for example, [1,2]). F r o m (1) and (2) we obtain
In this note, the area-time complexity of a VLSI c o u n t e r is studied. Both a lower and an upper b o u n d are derived which meet to within the exponent of the logarithmic factor. The proposed VLSI design derives from the parallel c o u n t e r presented by Muller and Preparata [3], which requires O(log n) delay time and O(n) n u m b e r of elements. A n area of order n l o g 2 n will be shown to suffice for the VLSI network and a lower b o u n d to A T 2 of order n log n will also be proved.
2. Lower bound
(1)
and T >t q - 1 + l o g [ n / q ] ,
+ 2n l o g ( n / q ) } ), that is, A T 2 = f~(n log n), since the m i n i m u m is attained for q = O(log n). N o t e that, in the case of m a x i m u m parallelism (q = 1), the lower b o u n d is of order n log 2 n.
3. VLSI design
In this section, a lower b o u n d is shown which meets the area × (time) 2 complexity of the design presented in the next section up to the exponent of the logarithmic factor. Indeed, if I n / q ] bits are sent at the same time, the following relations hold: A >t I n / q ]
A T 2 = fl( min {nq + n / q l o g 2 ( n / q ) q
(2)
since f ~ ( l o g [ n / q l) steps are required in any computational model to c o m p u t e a nontrivial function
Let x 1, x 2 , . . . , x n be a configuration of O's and l's. A parallel counter with input xa, x 2 xn gives as output the binary representation d o , d 1. . . . . d m o f the n u m b e r of l's in the input configuration. The basic element of the parallel counter is the adder element which has three inputs a~, b i, ci_~ and two outputs d~, c i, where . . . . .
d i = (aibiVaibi)c.i_lV(aibiVaibi)ci_l, c i --- (aiVbi)Ci_lVaib i. The connections a m o n g the basic elements are
0020-0190/86/$3.50 © 1986, Elsevier Science Publishers B.V. (North-Holland)
193
Volume 22, N u m b e r 4
INFORMATION PROCESSING LETTERS
17 April 1986
>
•
I
Fig. 4.
Fig. 1.
not in a p l a n a r geometrical configuration and each element has five connections (see Fig. 1) [3]. In order to give the VLSI design for this parallel counter, we associate to any basic element (adder) a PE (processing element) requiring two units of area with five wires c o n n e c t e d as shown in Fig. 2, each sending the information in one direction only. It is easy to see that the network can be laid out by using the three PEs shown in Fig. 3, which differ from each other only for the wires' direction.,, Let us assume n = 2 m + l - I SO that the parallel
counter is composed of adders only. We want to study the behaviour of the area of the layout with respect to n. In Fig. 4 a recursive VLSI design is shown where modules of type I are counters of dimension 2 m - 1 and a module of type II performs the final stages as specified in [3]. With the aid of Fig. 5, in which the case n = 15 is illustrated, it is easy to see that m o d u l e II can be laid out in a rectangle of O(m) width and O(m) height. Assuming that at every stage all the input (output) nodes lie on the b o u n d a r y of the chip, we obtain an upper b o u n d of order n log 2 n for the area of the chip. Let wm and h m be respectively the width and
Fig. 2.
Fig. 3. 194
Fig. 5.
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the height r e q u i r e d to l a y o u t the c o u n t e r o f dim e n s i o n n = 2 m+l - l ; f r o m the r e l a t i o n s w m = wm_l + O ( m ) , hm = m a x { 2 h ~ _ l
+ O(1), O(m)},
it follows t h a t A = O ( n log 2 n), f r o m w h i c h A T 2 = O ( n log 4 n). T h e design is t h e n o p t i m a l u p to the e x p o n e n t o f the l o g a r i t h m i c term.
17 April 1986
References [1] L. Csanky, Fast parallel matrix inversion algorithms, SIAM J. Comput. 5 (1976) 618-623. [2] R.B. Johnson, Jr., The complexity of a VLSI adder, Inform. Process. Lett. 11 (2) (1980) 92-93. [3] D.E. Muller and F. Preparata, Bounds to complexities of networks for sorting and for switching, J. ACM 22 (1975) 195-201. [4] C.D. Thompson, Area-time complexity for VLSI, Proc. llth Ann. ACM Symp. on the Theory of Computing (SIGACT) (1979) 81-88.
Acknowledgment T h e a u t h o r s w o u l d like to t h a n k Prof. F. Prep a r a t a for i n s p i r i n g this research.
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