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A Novel dynamically reconfigurable logic block based on CHAOS
Copyright.© If AC Programmable Devices and Embedded Systems Bmo, Czech Republic, 2006
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A NOVEL DYNAMICALLY RECONFIGURABLE LOGIC BLOCK BASED ON CHAOS Be/mam rua', Mohammad Reza Jahed-l\1odaghl
i Departmelll o/Compllter Engineerillg iroll Ulliversity o/Science and Techllology. Tehran, iron be/[email protected] 2 J)epartment a/Campllter t;ngineerillg. Iran University a/Science and Tecllllalagy. Tehran, Iran jahed,,,,(ii>illst. ac. ir
Abstract: Thc ncw idea of chaos based computation is studied and improved to obtain a novel logic block. In new prcscntcd schcme reconfigurability is produced through intrin,ic flexihility of chaotic ,)'Stcms. Handle for directing the logic hlock to simulate different kinds of digital functions is the offsets that one gives to the data inputs. A new form of dynamic reconfiguration that is beyond the conventional meaning of dynamic reconfiguration in rPGAs is introduced. Introduced scbeme could reconfigure itself by the arrival of new set of data and control inputs and no suspension in tbe operation of the system is needed. Copyright '1:: 2006 IFAC Keywords: Computing systems, Digital circuits, Dynamic systems, Chaos theory, Computer hardware.
I. INTRO[)UCTION
through intrinsic flcxi bility of chaotic systcms. Dvnamical sYstems are information generators or equivalently' information processors (Crutchfield, 1(94). Consider initial conditions of dynamical system as inputs and final state of the system as results of the processing. Dynamics of the system, maps these inputs. initial conditions. to outputs, final statc of the systcm. Newly a great amount of research has becn done to relatc thc dynamical properties of systcm to its computation power (Brarucky, 1995; Crutchlield, 19(4). For example which function is emulated with dynamical system? The richest and most complex dynamics belongs to chaotic systems (Afraimovich and Hsu 2002). Behavior of chaotic systems is unpredictable i.c . the dynamics of the systcm is sensitive to initial conditions. This property suggests the possihility of implementation of different function with a lixed hardware. The key point is addition of an offset to the data inputs which works as a handle to program the reconligurable computing system. Note that the chaotic system is sensitive to initial conditions and with addition of such ollset to it the behavior ur the system changes and as a result a new function is simulated. The
Hcre. chaos based computation (Munakata et aI., ~l a1.. 2002; Sinha and Di110. 1999) is introdu~ed and improved tu be used as a new lugi~ bluck. The last d~ade has experienced an increase interest on re~unligumble computing. This evulution W3' hoosted hy Ff'(iAs. FPGA architectures are divided into two constraints: logic block architecture and routing architecture (Rose et aI., 1993). Introduced scheme is a new paradigm for logic block architecture. Here the scope uf study is restricted to the introduction of a new logic block and the architccturc of intcrconncction of such logic blocks and CAD tools needed to program this s)'Stem are not mentioned and these field, need dedicated studies.
2002; Sinha
Programmability of conventional logic blocks is produced through SRAM technology, Antifuse technology and Huating gate tc~hnulugy (These techniques arc used fur progranlllllng the interconnections too) (Rose et al.. 1')1)3). In new presented scheme. Programmability is produced
372
previously introduced chaos-based flexihle computation model is as follows (Munakata et al .• 2002; Sinha et al .. 2002; Sinha and Ditto. 1999): The o~ective is to obtain N clearly defined logic gate response patterns from the N components characterizing the state of an N-dimensional system. This enables onc to implement N operations in parallel with a single N-dimensional chaotic element. Specifically the processor is an N-dimensional chaotic element. whose state IS characterized The
byx=(XI . X2 .... . XN ).
I:. I~ • .... I'u clement
M
inputs
to the i th variable of the chaotic
arc
encoded
X;, X~, .. , x'u where
through
X~ = 0
I;
if
values
=0
and
X~ =a>OifI~ =l.
2. IMPROVED CHAOS HASElJ RECONFIGURABLE COMPUTING SYSTEM
In this pari, the new improved scheme is introduced. Presented scheme is a mixed signal design, i.e. the chaotic core of the system is analog. but data inputs, control inputs and outputs are digital. Here the hardware consists of a chaotic core and two translation maps (Figure I). The whole states of the chaotic system are dedicated to emulate just one digital function. The m digital data inputs to the system
inputs to that state and an oll'sel X 10' which is produced by control input: (I)
wherei = 1,2 . ...,N. Then the system is let to evolve. The outputs from the chaotic elements arc ubtained by the simple threshold mechanism. Aner
X,~, x~,
input~
.." Xi: and
working
the n digital
a5
offset
are
.X :om",I')( :amrol ... ·')( :onlrol .
The relationship between m and n will be studied in part 3. Assume
X
Each state of the system is set to the summation of
are
control
conlml
is digital control inputs in decimal base:
X c:unlrvl = (X :()nlro'X c~ntrol ... X ;"nlrol ) d The operation of the system is done in three steps: 1- Each sct of data and control inputs is mapped to a point on the unstable directions in the state space of the chaotic core through forward translation map and this map. T . is defined hy T : R ~ fJ,
fJ c R"
time r • if the evolved state variable X,( r) is larger
Y = T(X rnnlrol + W IXln + .. . + W mX:)
than a prescribed threshold x; . i.e. x,(r) > XI"' the
Inside the parentheses there is an affine expression where is composed of m digital data inputs,
(2)
state variahle is reset to the threshold value x,"
X~, ,X;", ... ,X:.
emitting the excess amountX 10UI = {x i (r) - Xi"}'
bYull,W2,'''' W m , in order to he distinct and is
X
which
are
weighted
If the value of the variable is under the critical value.
biased with
i.e.x,(r) <::x; , there is no response from the
computation. Y represents the image of the inputs under forward translation map in the n-dimensional state space of the chaotic core and will be used as the initial condition of the chaotic core. The range of this map is unstable directions of the system, fJ . on
element and x ~UI =
X~,
:::;
8' encodes
O.
X ~UI
= 0 encodes 0 and
I. Setting the evolution time r •
threshold values and initial state of the system so that it directly gives the desired response (i.e .. outputs the desired
excesses X
L,.x !,. ... ,x::
l
)
constitutes
programming the gates. This computation model possesses a very interesting property. It could be reconfigured dynamically (Sinha et aI. , 2(02). It means the system could reconfigure itself to implement a new function without suspending its operation. Here this computation model is improved to obtain an efficient reconfigurable logic block. Then the subject of dynamic rcconiiguration is applied and studied on it. This form of dynamic rcconfiguration is beyond the conventional meaning of dynamic rconfiguration in FPGAs . The flow of paper is as follows; In part 2 improved chaos based scheme comes, in part 3 the universality of the system is discussed. in 4 robustness of the system is studied, in 5 timing of the introduced architecture is explained, in 6 the new kind of dynamic reeonfiguration is studied in 7 a simple example is presented and in 8 the paper is concluded.
conlrol that represents the type of
which is a subset of n-dimensional state space of chaotic core. i.e. fJ
eRn.
The distance between
images produced by this map depends on the Lyapunov exponent of the system, for the systems with larger values of Lyapunov exponent shorler distance between images is enough and for systems with smaller Lyapunov exponent longer distance is needed. The reason is that statistical independency of outputs of overall system is vital for universality of the model. This subject will be studied more in pari 3.
FIG. I . Schematics of the chaos based reconfigurable logic block 2- \Jnder these initial conditions the system start~ evolution for a fixed number of iteration in the case of maps or for a fixed time in the case of flows . The iteration number (or time interval in the case of flows) should be chosen so that orbits, starting from nearby initial conditions produced by forward translation Illap uncorrelate.
373
3- After a predefined number of iteration of the core (or a fixed time in the case of flows), the system stops working and the final state of the system is sampled. This final state is decoded to the outputs through bad:ward translation map. Strategy of decoding the outputs is: divide the state space of chaotic core to the partitions and assign to each partition one possihle comhinations of digital outputs (this a"igning is one to one). The output of the computation is the assigned value of the partition that sampled state settles in. Notice partitioning should preserve the topological properties of the system. especially topological entropy that 4uantifies chaotic nature of the system. Such partitioning is called generating (Bollt, 2(03). The reason for this requirement is that partitioning and suhstation of the trajectories with their symbolic representation should preserve the chaotic nature of the system that is the source of universality of the computation model. A complete study of topological entropy and generating partitions exists in (Bollt, 2003). The above statements represent the new scheme in a general 10rm. Detail s depend on the structure of the chaotic core. e.g.. the structure of its unstable manifold, the structure of its generating partitions and so on. A typical example is presented in part 7. In new introduced chaos based scheme some impruvcments arc made to the previous scheme: I-Previous method could only simulate commutative functions. hut the new method could simulate all the functions, commutative or non-commutative by thanks of wei~hts of the data inputs. 2-ln previous- computation model, each state of the chaotic ,'Vstems is modulated by di nerent sets of inputs independently and no special attention was paid to the whole dynamical properties of the system that shows itself in the form of interactions between states of the system. In presented scheme the whole states of the system is allocated to em ulate one digital functio~ according to its dvnamical properties. So instead of having different input' to different states, on set of inputs is fed to the system. By tltis improvement one is faced with orbits of the system and could use diffcrcnt tcc\miqucs of dynamical systems theory and symbolic dynamics to n;anipulate ihe introduced system (as here is done for making the system robust and universal). 3- Previous scheme could simulate the operation of N lugi" gates, simultaneousl y. This is some form of parallelism in computation. In new scheme this lacility is lost by dedicating the whule dynanlics of the system to simulate just one gate . But olle could ohtain allother foml of parallel processing here. To simulate w m-input, one-output digital functions simultaneously. divide the state space of chaotic
simulation of w m-input. one-output digital functions equals to simulatiun of une W X m -input, woutput digital function. 3. CAPABILITY OF THE SYSTEM IN SIMUI.A TION OF AI.I. FUNCTIONS In this part three questions are answered; First: Is the introduced scheme capable to simulate all types of the digital functiuns . Secund: What is the relationship between the number of data inputs and control inputs. i.e. m and n? Third: How could one find appropriate control inputs, producing desired function? Presented system is a quasi random number generator that different data inputs biased with control inputs stimulate the system to different initial conditions and hecause these initial conditions are laid on the unstahle directions of the system, hy iteration of the map the correlation between these trajectories decreases and produced outputs become pseudonllldom. By changing the cuntrol input one can hias the inputs to different points and as a result the produced outputs change. To be ahle to emulate all types of the digital functions. control inputs should cxist so that thc dynamics of the system leads in production of dcsired patterns. The used hypothesis in this paper is: hy enough number of control inputs. desirable digital functions become achievable . Without loss of generality of the problem, assume the goal is emulation of m-input, one-output combinational digital functions. The procedure 10r ubtaining digital [unctiuns with higher number of uutputs is similar to this method. A logic
block should be able to simulate all 22111 different minput. one-output combinational functions. The process of feeding different combinations of data inputs to the system and observing the output with a fixed control input is a random experiment. Random spacc of this random experimcnt is
SR ={a'a2 ...a2-lai E{O.1} ,i=1, 2, .. .. 2m}. (3) where
the output of computing sy,;iem when
00 ... 00 is fed to the ''Ystem as data input,
Q2
is the
output when 00 ... 01 is fed to the system ... and
a2m is the output when 11 ... 11 is fed to the system. Here back ward translation map works as random variahle and assign the final state of the system a sign. ' 0' or '\'. Each sample of this space represent, one digital function and vice versa. The effect of changing the control inputs equals to trying the experiment again and possibly obtaining another digital function . The probability uf ubtaining desired function, c.g. " 10 ... 10" at first try is
w
system to 2 partition and assign to each one, one combination of w outputs of these digital functions. Halting the system in each partition equals to production of assign string of outputs. Note that in this condition data input' to the system are the collection of all data inputs of w functions and control inputs are the collection of all control inputs to all w functions . Ay the other words simultaneous
a, is
P(X
= 10 .. .10) = p(lnOn ... mnO) =
P(l) x P(O) x .. . x P(l) X P(O)
(4) Here because of uncorrelation of nearby trajectories in chaotic systems the whole rundom experiment is broken to 2 m independent reduced experiments. Backward translation map divides the state space of chaotic system to twu cxelusive parts labelled '0' and
374
'I'. Therefore if P(O)
=q and
P(l)
=P
then
p + q = 1 and as a result previous equation changes
pr
toP(X = 10 ... 10) = pk x (1-
hy use of two or three e,.,tra control hits. all the desired combinational digital functions are simulated by the system.
where k is the number of'I' s and r is the number of '0' s in the desired random sample. It is obvious that the probability of obtaining desired function at lirst try could be very low and onc should continue trying the system hy otheT control inputs to ohtain the desiTcd function. These tries each time with 8 diffeTent contTol input are statistically independent. too (remember uncorrelation of nearby oTbits in chaotic systems). IIence the pTobability of obtaining desiTed function by maximum f trics become:
p(r
Tahle I. First CDlumn represents the number of inputs. the second and third column represent. the corresponding probabilities and Y is a random variablc. which Tepresents the maximum numbeT of tries.
m
5
(1- pk(1- p)')pk(1- pr + ... (5)
1-(1- pk(1- pY)f
P(Y
=i " +2)
0.9899 0.9839 0.9818 0.9816 0.9816
The whole scenario becomes in this way Add two or three ell.1ra control bits to the system, e.g. for simulation of m-input, one-output functions, use m
11 is detectable that fOT having an ellicient lugic block (i.e. all the functions are achievable at minimum tries) one should set the value of
1
= 2 2")
0.6836 0.6439 0.6328 06121 0.6121
I 2 3 4
= f) = pk(l_ pr +
+(1- pk(l_ p)')f-Ipk(l_ pr
P(Y
.
P to - (th,s should be consideTed as a rule during
2
design process and symbolizing the state space). I3y
I
selling the value of p to -
2
the new probability
function is ohtained: P(Y = f) =
1- (1- (f)2"l.
This function has a very interesting properly. I3y suhstitution of f with 2 ", one ohtain approximately equal probahility fOT diffeTent values of m. Second column of table I shows this fact fOT different values of inputs. This fact is also true for systems with higher numbeT of inputs. To study this case, the limit of introduced function when m, the numbeT of input., approaches to infinity is calculated: 2
lim m.... ro 1-(l-(f)2" /" ;: 1-11 e =0.6321 2
Note that 2 " has especial meaning. 11 TepTesents the numbeT of the possible m-input, onc-output digital functions. Therefore to ubtain all these functiuns, at 2
least 2 " tries is needed. I3ut this probability is not high enough (it is about 0.63) and more tries is needed. This is because of occurrence of repeated functions in trying the system.
2m digital
cuntrol bits
2
could direct the system to do 2 " tries and for increasing this value two extra control hits are added. Resulted probahilities are represented in thiTd column of tahle I . For large values of ' m' this 4
With quantity equals to 1-l/e =0.9817 additiun of three extra bits this probability lOT di fferent values of m equals to 'O')')')?, and with addition of four extra bit. it equals to '1' when the calculation fOT obtaining this probability is done in double precision. These statements make it clear that
2 +2
control hit• . Perform the experiment. with all the possible combinations of control inputs (in 2"' 12
this case 2 experiment) and record the association between conlrol inputs and their produced functions in a loo~'Up table . As was shown before, all Ihe possible functions will be produced. After this process. whenever a special function is needed, just refer 10 the records and use the control bits that produce the desiTed function. Note that these uperatiuns should be implementoo within CAD louls. One-inpu~ onc-output combinational digital function that ils output equals to its inpul cuuld be used as a memory clement and its operation looks like to i) flip flop. The delay between input and output equals to time elapsed for iteration of the chaotic core . Therefore one could simulate sequential circuits by use of two chaotic haTdv.-are. One simulates combinational part of the sequential circuit and the second onc is used as the memury clement. The oUlput from the combinatiunal circuit is fed back to its inputs through the second chaotic hardwaTe acting as memory element. As a result the introduced system is ahle to simulate all the comhinational OT sequential digital systems . 4. ROBUSTNESS OF THE SYSTEM Presented system, iterates fOT a fixed value. e.g. h times. This restricted iterations of the system. contributes the design. robustness. As was stated before the output is the symbol of the partition that the final state of the system falls in. This definition of the output. determine a symbolic cylindeT (Afraimovich and Hsu 2002) on which all the points in it symbolicall y behave the same under the iteTation of the map. and finall y produce the same output. For example for h iteration the cylinder is:
C"
0··
'1'
~
1
= \cv E 0 . : 0)0 =i 0,0), =i I ' _
where Q + is symbolic phase space:
375
. . , O)h-'
=i h) (6)
n = {O.I}7.· = {m = (m +
and
.
_
,m , .. .. m ,.. ,), m O.
I
.
n·
.
E
{O.l}} Data and control input. should he ready at the rising
k
mh _ 1 is the output. Until the noise kicks the
chosen initial condition to other points in the introduced set, or kicks the images of the chosen initial condition to the images of the seL no especial error occurs. This policy for robustness works well for initial conditions that are in middle of the se\. If one uses an initial condition that is near to the boundary of the partition or preimages of this boundary, a small noise could bring the trajectory to wrong partition. To solve this problem a new policy is introduced: never use the initial conditions that go near to the boundaries. By the other words deline a forbiddcn region around thc boundarics of the partitions. To implement this policy the following method is used: In trying the system with different control inputs to obtain all the digital functions. do not consider control inputs that their trajectories enter to forbidden region in h iterations where h is the iteration number of the chaotic core is. The remindcr of the chaotic attractor aftcr rcmoval of this group of trajectories is some kind of saddle (Bollt and Lai, 1998) by this ditference that saddles introduced in (Bollt and Lai. 1998) never enter to forbidden region but here they do not enter to forbidden region in h steps. The effect of second policy lor robustness is reduction in unprcdictability of the system (Hollt and I.ai, II)I)H) that is needed for flexible computation. Therefore one should look for a trade off between unpredictability of the system and the robustness. In (Bollt and Lai, 1998) topological entropy is used to measure the unpredictability of the system and a detailed study is done on thc rclationship bctwcen topological entropy and the size of forbidden region in saddles and finding a trade-off hetween them. 5. TIMING OF INTRODUCED LOGIC BLOCK Introduced system in part 2 is a three-step algorithm, hence three clocks are needed to direct the system to perfoffil these steps one by one and repeat this loop again and again. Figure 2 shows the condition of theses three clocks relative to each other. In figure 2 the first clock from top represents the initializing clock . It directs the process of initiali zation of chaotic core .
Fig. 2. Three clocks of the system is shown.
edge of this clock and should be hold fixed dunng this pulse. I1aving practical importance, the length of this pulse should be chosen so that the state of the chaotic core could be set to any desired value. The second clock directs the process of evolution of chaotic core. During this pulse the chaotic core is let to run freely. During this pulse the sy,;tem has no interaction with the bus and interconnectinns of the FPGA and hence they could be reconfigured for the next instruction cycle. The last clock directs the process of output production. At the beginning of this pulse the state of the ,ystem is sampled and held. According of its spltial positioning in state splce of the chaotic core and structurc of partitions of statc space the output produces. The union of these three pulses construct one instruction cycle. By the end of the output production clock pulse, the second pulse of initializing clock comes and a new cycle with new data inputs and even control inputs starts.
6. A NEW TYPE OF DYNAMICAL RECONFIGURATlON In conventional fPGAs, dynamic reconfiguration is defined as the selective updating of a subsection of an FPGA' s programmable logic and routing resources while the remainder of the device ' s programmable resources continue to function without interruption (Fcrrandi et al., 2005). Here this definition is enlarged to program the parts of the FP(iAs that are working without suspending the operation of them . /\t the first instruction cycle, one set of data inputs are processed according of control inputs. According of computation needs, one wants to changes the type of computation. i.e. simulates another digital function. The only thing that one should do is feeding the appropriate control inputs concurrently with new data inputs to the system at the beginning of the new instruction cycle. Such dynamic reconfiguration of logic block is impossible in conventional logic blocks because these devices are programmed through some memory elements, e.g. SRAMs. Antifuses and floating gates (Rose et al., 1993). These elements are used during the processing cycle. Hence to reconiigure such logic blocks. one should ,;top the operation of these blocks and do not give new data. reload the new programming elements and start the system again. It is so that in chaos based logic block the device is progmmmed through olfsets that one gives to the data inputs. Hence the programming could takc place concurrently with arrival of new corresponding data inputs and no interruption in opcmtion of the system is needed. llere dynamically reconfigure logic block is obtained in the expense of using two or three e}'"lra control bits introduced in part 3. In this paper dynamic reconliguration of logic blocks was introduced . To have a dynamic reconfigurable FP(iA, interconnections should be able to be reprogrammed dynamically. During evolution clock. logic blocks are disconnected from intemal wiring and interconnections of FPGA and theses parts are idle. During this pulse, interconnections could be
376
reconfigured to the new structure . Hut this suhject needs much more research. On the other hand, especial CAD tools are needed to support these facilities.
number of inputs the same procedure is applicable by this difference that the nUlllber of control inputs will be changed according of part 3. 8. CONCLUSION
7. A SIMPLE EXAMPLE A simple example is presented to visualize introduced concepts. Chosen chaotic core is logistic map. For holding simplicity. the simulation of twoinput, one-output combinational circuits is studied here. for one-dimensional, one-critical-point maps lik~ logistic map. a good binary partitioning could be defined through choosing critical point as the boundary of the two partitions (Bollt. 2003). This partitioning is generating and could preserve the chaotic nature of the system (Bollt. 2003). Figure 3 shows the logistic map. its critical point and the corresponding boundaries.
. .. ~ .
\ T
:; .
c.
•
,~
•
Here a new kind of reconfigurable logic block wa~ presented and a new form of dynamical reconfiguration was introduced. The reconfiguration is done through giving some offsets to the data inputs and hence no interruption in system operation is needed to reconfigure. There are efficient chaotic systems that could be used as the core of th~ system, c.g. Chua circuit and Lorenz system. Hardware implementation of these systems as IC chips have been reported. See (Cruz and Chua 1993) for Chua circuit IC chip and (Cuomo and Oppenheim. 1993) for Lorenz IC chip. At the end, chaos based logic block has interesting properties and deserves more anention and study.
.
REFERENCES
-
Al'raimovich, V . and S .B. Hsu . (2002). Leclures on American Chaotic DYllamical Syslems, Mathematics Society. Bolh, E. (2003). Review of chaos communication by feedback control of symbolic dynamics . IJBC, 13. 269-285. BoHt, E. and Y .C. Lai, (1998). Dynamics of coding in communicating with chaos. Phys. Rev. };. 58,
•
fig. 3. Logistic map, its critical point, c, and its binary partitioning According of the discussions of part 3 to obtain all the two-input, one-output combinational digital
1724-1736. Bronick-y. M.S. (1995). Universal computation and other capabilities of hybrid and continuous Theoretical computer dynamical systems.
functions, 2 2 , • .l try is enough. Hence 7 control inputs are needed. To weigh the inputs a simple trick is used just convert the binary data inputs 10 its equivalence in decimal base and divide it hy 4. As
science. I3R. 67- lOO. Crutchfidd, J. 1'. (1994). Th~ Calculi of emergence: computation, dynamics. and induction. Physica
was pointed out before, Xcomrol ' is digital control
D.75. 11-54.
inputs in decimal bas~ . For this example ("rward tnmslation is:
Cruz. l . M. and L.O. Chua (1993). An le chip of Chuu's circuit. IEEE Trrans. Circuits alld Systems. 40. 614-625. Cuomo. K. and A . V . Oppcnheim (1993). Circuit implementation of s~,11chronized chaos with applications to communications. Phys. Rev. Lell.
T : R~R
T : x = ~ x (Xconlrol + f j) where j
(7)
is the data inputs in decimal base. By the
other words the weight for the
ru. bit in data input is
71. 65-68.
f X 2 P- 1 (the direction for indexing is not important.
Ferrandi. F., M.D. Santambrogio and D . Seiuto (2005). A design methodology for dynamic reconfiguration : The Caronte Architecture. 19th
Just the goal is making the inputs distinct). Note that forward translation map is chosen so that distributes the combinations of control inputs and data inputs uniformly along the interval [0, I]. In above equations X ",mrol
IEEE 11llemaliollal Parallel mui Distributed Processing Symposium. 04"()8. Munakata. T, S. Sinha and W .L. Diuo (2002). Chaos computing: implementation of fundamental logical dates by chaotic elements.
changes from 0 to 127 and
j changes from 0 to 3. The iteration number of the
II:'H/"' Trmu. circuit alld sysle".,: fillldame1llal theorymldapplicalions, 49. 1629-1633. Rose, l .. A. El. Gamal. and A. Sangiovanni-
chaotic core, h, is set to IS . According of part 4 to make the system robust in front of noise a ("rbidden region is defined around partition boundary. This forbidden boundary here is l0.49, 0.5 I J. The control inputs that produce the orbits which fall in this boundary are not considered and are neglected. By trying the algorithm with different control inputs and each time evaluating the output of the system when different combinations of data inputs are fed to the system, all types of two-input, one-output functions are obtained. To simulate functions with higher
(1993). Architecture of fieldgate arrays. Proceedings of the lEl:1:.·. 81. 1013-1029. Sinha, S . and W.!.. Dino (1999) . Computing with distributed chaos. Plrys Rev E. GO, 363-377. Sinha. S .. T. Munakata and W.L. Ditto (2002). Parallel computing with e:-.1ended d)l1amical systems. Plrys. Rev. E, 65, 036214 [1-7]. VincenteHi
programmabl~
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[~
fer
l>
Publications
A NOVEL DYNAMICALLY RECONFIGURABLE LOGIC BLOCK BASED ON CHAOS Be/mam rua', Mohammad Reza Jahed-l\1odaghl
i Departmelll o/Compllter Engineerillg iroll Ulliversity o/Science and Techllology. Tehran, iron be/[email protected] 2 J)epartment a/Campllter t;ngineerillg. Iran University a/Science and Tecllllalagy. Tehran, Iran jahed,,,,(ii>illst. ac. ir
Abstract: Thc ncw idea of chaos based computation is studied and improved to obtain a novel logic block. In new prcscntcd schcme reconfigurability is produced through intrin,ic flexihility of chaotic ,)'Stcms. Handle for directing the logic hlock to simulate different kinds of digital functions is the offsets that one gives to the data inputs. A new form of dynamic reconfiguration that is beyond the conventional meaning of dynamic reconfiguration in rPGAs is introduced. Introduced scbeme could reconfigure itself by the arrival of new set of data and control inputs and no suspension in tbe operation of the system is needed. Copyright '1:: 2006 IFAC Keywords: Computing systems, Digital circuits, Dynamic systems, Chaos theory, Computer hardware.
I. INTRO[)UCTION
through intrinsic flcxi bility of chaotic systcms. Dvnamical sYstems are information generators or equivalently' information processors (Crutchfield, 1(94). Consider initial conditions of dynamical system as inputs and final state of the system as results of the processing. Dynamics of the system, maps these inputs. initial conditions. to outputs, final statc of the systcm. Newly a great amount of research has becn done to relatc thc dynamical properties of systcm to its computation power (Brarucky, 1995; Crutchlield, 19(4). For example which function is emulated with dynamical system? The richest and most complex dynamics belongs to chaotic systems (Afraimovich and Hsu 2002). Behavior of chaotic systems is unpredictable i.c . the dynamics of the systcm is sensitive to initial conditions. This property suggests the possihility of implementation of different function with a lixed hardware. The key point is addition of an offset to the data inputs which works as a handle to program the reconligurable computing system. Note that the chaotic system is sensitive to initial conditions and with addition of such ollset to it the behavior ur the system changes and as a result a new function is simulated. The
Hcre. chaos based computation (Munakata et aI., ~l a1.. 2002; Sinha and Di110. 1999) is introdu~ed and improved tu be used as a new lugi~ bluck. The last d~ade has experienced an increase interest on re~unligumble computing. This evulution W3' hoosted hy Ff'(iAs. FPGA architectures are divided into two constraints: logic block architecture and routing architecture (Rose et aI., 1993). Introduced scheme is a new paradigm for logic block architecture. Here the scope uf study is restricted to the introduction of a new logic block and the architccturc of intcrconncction of such logic blocks and CAD tools needed to program this s)'Stem are not mentioned and these field, need dedicated studies.
2002; Sinha
Programmability of conventional logic blocks is produced through SRAM technology, Antifuse technology and Huating gate tc~hnulugy (These techniques arc used fur progranlllllng the interconnections too) (Rose et al.. 1')1)3). In new presented scheme. Programmability is produced
372
previously introduced chaos-based flexihle computation model is as follows (Munakata et al .• 2002; Sinha et al .. 2002; Sinha and Ditto. 1999): The o~ective is to obtain N clearly defined logic gate response patterns from the N components characterizing the state of an N-dimensional system. This enables onc to implement N operations in parallel with a single N-dimensional chaotic element. Specifically the processor is an N-dimensional chaotic element. whose state IS characterized The
byx=(XI . X2 .... . XN ).
I:. I~ • .... I'u clement
M
inputs
to the i th variable of the chaotic
arc
encoded
X;, X~, .. , x'u where
through
X~ = 0
I;
if
values
=0
and
X~ =a>OifI~ =l.
2. IMPROVED CHAOS HASElJ RECONFIGURABLE COMPUTING SYSTEM
In this pari, the new improved scheme is introduced. Presented scheme is a mixed signal design, i.e. the chaotic core of the system is analog. but data inputs, control inputs and outputs are digital. Here the hardware consists of a chaotic core and two translation maps (Figure I). The whole states of the chaotic system are dedicated to emulate just one digital function. The m digital data inputs to the system
inputs to that state and an oll'sel X 10' which is produced by control input: (I)
wherei = 1,2 . ...,N. Then the system is let to evolve. The outputs from the chaotic elements arc ubtained by the simple threshold mechanism. Aner
X,~, x~,
input~
.." Xi: and
working
the n digital
a5
offset
are
.X :om",I')( :amrol ... ·')( :onlrol .
The relationship between m and n will be studied in part 3. Assume
X
Each state of the system is set to the summation of
are
control
conlml
is digital control inputs in decimal base:
X c:unlrvl = (X :()nlro'X c~ntrol ... X ;"nlrol ) d The operation of the system is done in three steps: 1- Each sct of data and control inputs is mapped to a point on the unstable directions in the state space of the chaotic core through forward translation map and this map. T . is defined hy T : R ~ fJ,
fJ c R"
time r • if the evolved state variable X,( r) is larger
Y = T(X rnnlrol + W IXln + .. . + W mX:)
than a prescribed threshold x; . i.e. x,(r) > XI"' the
Inside the parentheses there is an affine expression where is composed of m digital data inputs,
(2)
state variahle is reset to the threshold value x,"
X~, ,X;", ... ,X:.
emitting the excess amountX 10UI = {x i (r) - Xi"}'
bYull,W2,'''' W m , in order to he distinct and is
X
which
are
weighted
If the value of the variable is under the critical value.
biased with
i.e.x,(r) <::x; , there is no response from the
computation. Y represents the image of the inputs under forward translation map in the n-dimensional state space of the chaotic core and will be used as the initial condition of the chaotic core. The range of this map is unstable directions of the system, fJ . on
element and x ~UI =
X~,
:::;
8' encodes
O.
X ~UI
= 0 encodes 0 and
I. Setting the evolution time r •
threshold values and initial state of the system so that it directly gives the desired response (i.e .. outputs the desired
excesses X
L,.x !,. ... ,x::
l
)
constitutes
programming the gates. This computation model possesses a very interesting property. It could be reconfigured dynamically (Sinha et aI. , 2(02). It means the system could reconfigure itself to implement a new function without suspending its operation. Here this computation model is improved to obtain an efficient reconfigurable logic block. Then the subject of dynamic rcconiiguration is applied and studied on it. This form of dynamic rcconfiguration is beyond the conventional meaning of dynamic rconfiguration in FPGAs . The flow of paper is as follows; In part 2 improved chaos based scheme comes, in part 3 the universality of the system is discussed. in 4 robustness of the system is studied, in 5 timing of the introduced architecture is explained, in 6 the new kind of dynamic reeonfiguration is studied in 7 a simple example is presented and in 8 the paper is concluded.
conlrol that represents the type of
which is a subset of n-dimensional state space of chaotic core. i.e. fJ
eRn.
The distance between
images produced by this map depends on the Lyapunov exponent of the system, for the systems with larger values of Lyapunov exponent shorler distance between images is enough and for systems with smaller Lyapunov exponent longer distance is needed. The reason is that statistical independency of outputs of overall system is vital for universality of the model. This subject will be studied more in pari 3.
FIG. I . Schematics of the chaos based reconfigurable logic block 2- \Jnder these initial conditions the system start~ evolution for a fixed number of iteration in the case of maps or for a fixed time in the case of flows . The iteration number (or time interval in the case of flows) should be chosen so that orbits, starting from nearby initial conditions produced by forward translation Illap uncorrelate.
373
3- After a predefined number of iteration of the core (or a fixed time in the case of flows), the system stops working and the final state of the system is sampled. This final state is decoded to the outputs through bad:ward translation map. Strategy of decoding the outputs is: divide the state space of chaotic core to the partitions and assign to each partition one possihle comhinations of digital outputs (this a"igning is one to one). The output of the computation is the assigned value of the partition that sampled state settles in. Notice partitioning should preserve the topological properties of the system. especially topological entropy that 4uantifies chaotic nature of the system. Such partitioning is called generating (Bollt, 2(03). The reason for this requirement is that partitioning and suhstation of the trajectories with their symbolic representation should preserve the chaotic nature of the system that is the source of universality of the computation model. A complete study of topological entropy and generating partitions exists in (Bollt, 2003). The above statements represent the new scheme in a general 10rm. Detail s depend on the structure of the chaotic core. e.g.. the structure of its unstable manifold, the structure of its generating partitions and so on. A typical example is presented in part 7. In new introduced chaos based scheme some impruvcments arc made to the previous scheme: I-Previous method could only simulate commutative functions. hut the new method could simulate all the functions, commutative or non-commutative by thanks of wei~hts of the data inputs. 2-ln previous- computation model, each state of the chaotic ,'Vstems is modulated by di nerent sets of inputs independently and no special attention was paid to the whole dynamical properties of the system that shows itself in the form of interactions between states of the system. In presented scheme the whole states of the system is allocated to em ulate one digital functio~ according to its dvnamical properties. So instead of having different input' to different states, on set of inputs is fed to the system. By tltis improvement one is faced with orbits of the system and could use diffcrcnt tcc\miqucs of dynamical systems theory and symbolic dynamics to n;anipulate ihe introduced system (as here is done for making the system robust and universal). 3- Previous scheme could simulate the operation of N lugi" gates, simultaneousl y. This is some form of parallelism in computation. In new scheme this lacility is lost by dedicating the whule dynanlics of the system to simulate just one gate . But olle could ohtain allother foml of parallel processing here. To simulate w m-input, one-output digital functions simultaneously. divide the state space of chaotic
simulation of w m-input. one-output digital functions equals to simulatiun of une W X m -input, woutput digital function. 3. CAPABILITY OF THE SYSTEM IN SIMUI.A TION OF AI.I. FUNCTIONS In this part three questions are answered; First: Is the introduced scheme capable to simulate all types of the digital functiuns . Secund: What is the relationship between the number of data inputs and control inputs. i.e. m and n? Third: How could one find appropriate control inputs, producing desired function? Presented system is a quasi random number generator that different data inputs biased with control inputs stimulate the system to different initial conditions and hecause these initial conditions are laid on the unstahle directions of the system, hy iteration of the map the correlation between these trajectories decreases and produced outputs become pseudonllldom. By changing the cuntrol input one can hias the inputs to different points and as a result the produced outputs change. To be ahle to emulate all types of the digital functions. control inputs should cxist so that thc dynamics of the system leads in production of dcsired patterns. The used hypothesis in this paper is: hy enough number of control inputs. desirable digital functions become achievable . Without loss of generality of the problem, assume the goal is emulation of m-input, one-output combinational digital functions. The procedure 10r ubtaining digital [unctiuns with higher number of uutputs is similar to this method. A logic
block should be able to simulate all 22111 different minput. one-output combinational functions. The process of feeding different combinations of data inputs to the system and observing the output with a fixed control input is a random experiment. Random spacc of this random experimcnt is
SR ={a'a2 ...a2-lai E{O.1} ,i=1, 2, .. .. 2m}. (3) where
the output of computing sy,;iem when
00 ... 00 is fed to the ''Ystem as data input,
Q2
is the
output when 00 ... 01 is fed to the system ... and
a2m is the output when 11 ... 11 is fed to the system. Here back ward translation map works as random variahle and assign the final state of the system a sign. ' 0' or '\'. Each sample of this space represent, one digital function and vice versa. The effect of changing the control inputs equals to trying the experiment again and possibly obtaining another digital function . The probability uf ubtaining desired function, c.g. " 10 ... 10" at first try is
w
system to 2 partition and assign to each one, one combination of w outputs of these digital functions. Halting the system in each partition equals to production of assign string of outputs. Note that in this condition data input' to the system are the collection of all data inputs of w functions and control inputs are the collection of all control inputs to all w functions . Ay the other words simultaneous
a, is
P(X
= 10 .. .10) = p(lnOn ... mnO) =
P(l) x P(O) x .. . x P(l) X P(O)
(4) Here because of uncorrelation of nearby trajectories in chaotic systems the whole rundom experiment is broken to 2 m independent reduced experiments. Backward translation map divides the state space of chaotic system to twu cxelusive parts labelled '0' and
374
'I'. Therefore if P(O)
=q and
P(l)
=P
then
p + q = 1 and as a result previous equation changes
pr
toP(X = 10 ... 10) = pk x (1-
hy use of two or three e,.,tra control hits. all the desired combinational digital functions are simulated by the system.
where k is the number of'I' s and r is the number of '0' s in the desired random sample. It is obvious that the probability of obtaining desired function at lirst try could be very low and onc should continue trying the system hy otheT control inputs to ohtain the desiTcd function. These tries each time with 8 diffeTent contTol input are statistically independent. too (remember uncorrelation of nearby oTbits in chaotic systems). IIence the pTobability of obtaining desiTed function by maximum f trics become:
p(r
Tahle I. First CDlumn represents the number of inputs. the second and third column represent. the corresponding probabilities and Y is a random variablc. which Tepresents the maximum numbeT of tries.
m
5
(1- pk(1- p)')pk(1- pr + ... (5)
1-(1- pk(1- pY)f
P(Y
=i " +2)
0.9899 0.9839 0.9818 0.9816 0.9816
The whole scenario becomes in this way Add two or three ell.1ra control bits to the system, e.g. for simulation of m-input, one-output functions, use m
11 is detectable that fOT having an ellicient lugic block (i.e. all the functions are achievable at minimum tries) one should set the value of
1
= 2 2")
0.6836 0.6439 0.6328 06121 0.6121
I 2 3 4
= f) = pk(l_ pr +
+(1- pk(l_ p)')f-Ipk(l_ pr
P(Y
.
P to - (th,s should be consideTed as a rule during
2
design process and symbolizing the state space). I3y
I
selling the value of p to -
2
the new probability
function is ohtained: P(Y = f) =
1- (1- (f)2"l.
This function has a very interesting properly. I3y suhstitution of f with 2 ", one ohtain approximately equal probahility fOT diffeTent values of m. Second column of table I shows this fact fOT different values of inputs. This fact is also true for systems with higher numbeT of inputs. To study this case, the limit of introduced function when m, the numbeT of input., approaches to infinity is calculated: 2
lim m.... ro 1-(l-(f)2" /" ;: 1-11 e =0.6321 2
Note that 2 " has especial meaning. 11 TepTesents the numbeT of the possible m-input, onc-output digital functions. Therefore to ubtain all these functiuns, at 2
least 2 " tries is needed. I3ut this probability is not high enough (it is about 0.63) and more tries is needed. This is because of occurrence of repeated functions in trying the system.
2m digital
cuntrol bits
2
could direct the system to do 2 " tries and for increasing this value two extra control hits are added. Resulted probahilities are represented in thiTd column of tahle I . For large values of ' m' this 4
With quantity equals to 1-l/e =0.9817 additiun of three extra bits this probability lOT di fferent values of m equals to 'O')')')?, and with addition of four extra bit. it equals to '1' when the calculation fOT obtaining this probability is done in double precision. These statements make it clear that
2 +2
control hit• . Perform the experiment. with all the possible combinations of control inputs (in 2"' 12
this case 2 experiment) and record the association between conlrol inputs and their produced functions in a loo~'Up table . As was shown before, all Ihe possible functions will be produced. After this process. whenever a special function is needed, just refer 10 the records and use the control bits that produce the desiTed function. Note that these uperatiuns should be implementoo within CAD louls. One-inpu~ onc-output combinational digital function that ils output equals to its inpul cuuld be used as a memory clement and its operation looks like to i) flip flop. The delay between input and output equals to time elapsed for iteration of the chaotic core . Therefore one could simulate sequential circuits by use of two chaotic haTdv.-are. One simulates combinational part of the sequential circuit and the second onc is used as the memury clement. The oUlput from the combinatiunal circuit is fed back to its inputs through the second chaotic hardwaTe acting as memory element. As a result the introduced system is ahle to simulate all the comhinational OT sequential digital systems . 4. ROBUSTNESS OF THE SYSTEM Presented system, iterates fOT a fixed value. e.g. h times. This restricted iterations of the system. contributes the design. robustness. As was stated before the output is the symbol of the partition that the final state of the system falls in. This definition of the output. determine a symbolic cylindeT (Afraimovich and Hsu 2002) on which all the points in it symbolicall y behave the same under the iteTation of the map. and finall y produce the same output. For example for h iteration the cylinder is:
C"
0··
'1'
~
1
= \cv E 0 . : 0)0 =i 0,0), =i I ' _
where Q + is symbolic phase space:
375
. . , O)h-'
=i h) (6)
n = {O.I}7.· = {m = (m +
and
.
_
,m , .. .. m ,.. ,), m O.
I
.
n·
.
E
{O.l}} Data and control input. should he ready at the rising
k
mh _ 1 is the output. Until the noise kicks the
chosen initial condition to other points in the introduced set, or kicks the images of the chosen initial condition to the images of the seL no especial error occurs. This policy for robustness works well for initial conditions that are in middle of the se\. If one uses an initial condition that is near to the boundary of the partition or preimages of this boundary, a small noise could bring the trajectory to wrong partition. To solve this problem a new policy is introduced: never use the initial conditions that go near to the boundaries. By the other words deline a forbiddcn region around thc boundarics of the partitions. To implement this policy the following method is used: In trying the system with different control inputs to obtain all the digital functions. do not consider control inputs that their trajectories enter to forbidden region in h iterations where h is the iteration number of the chaotic core is. The remindcr of the chaotic attractor aftcr rcmoval of this group of trajectories is some kind of saddle (Bollt and Lai, 1998) by this ditference that saddles introduced in (Bollt and Lai. 1998) never enter to forbidden region but here they do not enter to forbidden region in h steps. The effect of second policy lor robustness is reduction in unprcdictability of the system (Hollt and I.ai, II)I)H) that is needed for flexible computation. Therefore one should look for a trade off between unpredictability of the system and the robustness. In (Bollt and Lai, 1998) topological entropy is used to measure the unpredictability of the system and a detailed study is done on thc rclationship bctwcen topological entropy and the size of forbidden region in saddles and finding a trade-off hetween them. 5. TIMING OF INTRODUCED LOGIC BLOCK Introduced system in part 2 is a three-step algorithm, hence three clocks are needed to direct the system to perfoffil these steps one by one and repeat this loop again and again. Figure 2 shows the condition of theses three clocks relative to each other. In figure 2 the first clock from top represents the initializing clock . It directs the process of initiali zation of chaotic core .
Fig. 2. Three clocks of the system is shown.
edge of this clock and should be hold fixed dunng this pulse. I1aving practical importance, the length of this pulse should be chosen so that the state of the chaotic core could be set to any desired value. The second clock directs the process of evolution of chaotic core. During this pulse the chaotic core is let to run freely. During this pulse the sy,;tem has no interaction with the bus and interconnectinns of the FPGA and hence they could be reconfigured for the next instruction cycle. The last clock directs the process of output production. At the beginning of this pulse the state of the ,ystem is sampled and held. According of its spltial positioning in state splce of the chaotic core and structurc of partitions of statc space the output produces. The union of these three pulses construct one instruction cycle. By the end of the output production clock pulse, the second pulse of initializing clock comes and a new cycle with new data inputs and even control inputs starts.
6. A NEW TYPE OF DYNAMICAL RECONFIGURATlON In conventional fPGAs, dynamic reconfiguration is defined as the selective updating of a subsection of an FPGA' s programmable logic and routing resources while the remainder of the device ' s programmable resources continue to function without interruption (Fcrrandi et al., 2005). Here this definition is enlarged to program the parts of the FP(iAs that are working without suspending the operation of them . /\t the first instruction cycle, one set of data inputs are processed according of control inputs. According of computation needs, one wants to changes the type of computation. i.e. simulates another digital function. The only thing that one should do is feeding the appropriate control inputs concurrently with new data inputs to the system at the beginning of the new instruction cycle. Such dynamic reconfiguration of logic block is impossible in conventional logic blocks because these devices are programmed through some memory elements, e.g. SRAMs. Antifuses and floating gates (Rose et al., 1993). These elements are used during the processing cycle. Hence to reconiigure such logic blocks. one should ,;top the operation of these blocks and do not give new data. reload the new programming elements and start the system again. It is so that in chaos based logic block the device is progmmmed through olfsets that one gives to the data inputs. Hence the programming could takc place concurrently with arrival of new corresponding data inputs and no interruption in opcmtion of the system is needed. llere dynamically reconfigure logic block is obtained in the expense of using two or three e}'"lra control bits introduced in part 3. In this paper dynamic reconliguration of logic blocks was introduced . To have a dynamic reconfigurable FP(iA, interconnections should be able to be reprogrammed dynamically. During evolution clock. logic blocks are disconnected from intemal wiring and interconnections of FPGA and theses parts are idle. During this pulse, interconnections could be
376
reconfigured to the new structure . Hut this suhject needs much more research. On the other hand, especial CAD tools are needed to support these facilities.
number of inputs the same procedure is applicable by this difference that the nUlllber of control inputs will be changed according of part 3. 8. CONCLUSION
7. A SIMPLE EXAMPLE A simple example is presented to visualize introduced concepts. Chosen chaotic core is logistic map. For holding simplicity. the simulation of twoinput, one-output combinational circuits is studied here. for one-dimensional, one-critical-point maps lik~ logistic map. a good binary partitioning could be defined through choosing critical point as the boundary of the two partitions (Bollt. 2003). This partitioning is generating and could preserve the chaotic nature of the system (Bollt. 2003). Figure 3 shows the logistic map. its critical point and the corresponding boundaries.
. .. ~ .
\ T
:; .
c.
•
,~
•
Here a new kind of reconfigurable logic block wa~ presented and a new form of dynamical reconfiguration was introduced. The reconfiguration is done through giving some offsets to the data inputs and hence no interruption in system operation is needed to reconfigure. There are efficient chaotic systems that could be used as the core of th~ system, c.g. Chua circuit and Lorenz system. Hardware implementation of these systems as IC chips have been reported. See (Cruz and Chua 1993) for Chua circuit IC chip and (Cuomo and Oppenheim. 1993) for Lorenz IC chip. At the end, chaos based logic block has interesting properties and deserves more anention and study.
.
REFERENCES
-
Al'raimovich, V . and S .B. Hsu . (2002). Leclures on American Chaotic DYllamical Syslems, Mathematics Society. Bolh, E. (2003). Review of chaos communication by feedback control of symbolic dynamics . IJBC, 13. 269-285. BoHt, E. and Y .C. Lai, (1998). Dynamics of coding in communicating with chaos. Phys. Rev. };. 58,
•
fig. 3. Logistic map, its critical point, c, and its binary partitioning According of the discussions of part 3 to obtain all the two-input, one-output combinational digital
1724-1736. Bronick-y. M.S. (1995). Universal computation and other capabilities of hybrid and continuous Theoretical computer dynamical systems.
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science. I3R. 67- lOO. Crutchfidd, J. 1'. (1994). Th~ Calculi of emergence: computation, dynamics. and induction. Physica
was pointed out before, Xcomrol ' is digital control
D.75. 11-54.
inputs in decimal bas~ . For this example ("rward tnmslation is:
Cruz. l . M. and L.O. Chua (1993). An le chip of Chuu's circuit. IEEE Trrans. Circuits alld Systems. 40. 614-625. Cuomo. K. and A . V . Oppcnheim (1993). Circuit implementation of s~,11chronized chaos with applications to communications. Phys. Rev. Lell.
T : R~R
T : x = ~ x (Xconlrol + f j) where j
(7)
is the data inputs in decimal base. By the
other words the weight for the
ru. bit in data input is
71. 65-68.
f X 2 P- 1 (the direction for indexing is not important.
Ferrandi. F., M.D. Santambrogio and D . Seiuto (2005). A design methodology for dynamic reconfiguration : The Caronte Architecture. 19th
Just the goal is making the inputs distinct). Note that forward translation map is chosen so that distributes the combinations of control inputs and data inputs uniformly along the interval [0, I]. In above equations X ",mrol
IEEE 11llemaliollal Parallel mui Distributed Processing Symposium. 04"()8. Munakata. T, S. Sinha and W .L. Diuo (2002). Chaos computing: implementation of fundamental logical dates by chaotic elements.
changes from 0 to 127 and
j changes from 0 to 3. The iteration number of the
II:'H/"' Trmu. circuit alld sysle".,: fillldame1llal theorymldapplicalions, 49. 1629-1633. Rose, l .. A. El. Gamal. and A. Sangiovanni-
chaotic core, h, is set to IS . According of part 4 to make the system robust in front of noise a ("rbidden region is defined around partition boundary. This forbidden boundary here is l0.49, 0.5 I J. The control inputs that produce the orbits which fall in this boundary are not considered and are neglected. By trying the algorithm with different control inputs and each time evaluating the output of the system when different combinations of data inputs are fed to the system, all types of two-input, one-output functions are obtained. To simulate functions with higher
(1993). Architecture of fieldgate arrays. Proceedings of the lEl:1:.·. 81. 1013-1029. Sinha, S . and W.!.. Dino (1999) . Computing with distributed chaos. Plrys Rev E. GO, 363-377. Sinha. S .. T. Munakata and W.L. Ditto (2002). Parallel computing with e:-.1ended d)l1amical systems. Plrys. Rev. E, 65, 036214 [1-7]. VincenteHi
programmabl~
377