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A novel model of the high-voltage VDMOS for the circuit simulation
Solid-State Electronics 93 (2014) 21–26
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Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
A novel model of the high-voltage VDMOS for the circuit simulation Siyang Liu, Rongxia Zhu, Kan Jia, Dong Huang, Weifeng Sun ⇑, Chunwei Zhang National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu 210096, PR China
a r t i c l e
i n f o
Article history: Received 11 April 2013 Received in revised form 17 November 2013 Accepted 4 December 2013 Available online 29 December 2013 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Vertical double diffused MOS (VDMOS) Model Internal nodes Quasi-saturation effect
a b s t r a c t A novel model of the high-voltage vertical double diffused MOS (VDMOS) for the circuit simulation has been presented in this paper. In the DC section of the model, the VDMOS is treated as a normal MOS device with four series resistors. In contrast to other VDMOS models, the resistance model of the accumulation region is built based on the surface potential calculation method. Moreover, both the channel depletion and the pinch-off effects of the parasitic JFET region are also taken into account carefully. In addition, the three important capacitances, Cgd, Cgs and Cds, have been considered and modeled in the AC section. The proposed complete device model is validated by the comparison with the measured data of the target VDMOS. The comparison results demonstrate that the new model gives the accurate descriptions for both DC and AC characteristics of the VDMOS device. Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction The vertical double diffused MOS (VDMOS) is one of the most important power electronic switch devices [1–5]. For the advantages of the high input resistance, the low driving power, the superior frequency characteristic and the low noise, the VDMOS has been widely used in the motor speed regulation, the Hi-Fi audio, the automotive electronics and so on [6–9]. It is noted that the SPICE (Simulation Program with Integrated Circuit Emphasis) models are the links between the physical world and the design world of the semiconductor industry [10]. Nowadays, the wide application of the VDMOS device makes its SPICE model urgently needed [11–15]. Many works have reported the SPICE model of the VDMOS device. Sanchez et al. proposed a kind of VDMOS SPICE model with the quasi-saturation effect [16]. Victory et al. built a SPICE model of the VDMOS based on the charge sheet theory, but the model did not account for the channel pinch-off effect of the parasitic JFET region [17]. Chauhan et al. developed a model of the VDMOS including the DC and AC characteristics [18]. As for the HiSIM_HV model, it was a universal model that can be suitable for HV_DMOS (LDMOS or VDMOS) [19], however, it was used for the target VDMOS at first by us with no good results. In this paper, a novel model of the high-voltage VDMOS for the circuit simulation is presented. Except for the three normal external nodes (source, drain, gate), four internal nodes are added ⇑ Corresponding author. Tel.: +86 25 83795811x8308; fax: +86 25 83795077. E-mail address: [email protected] (W. Sun). 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.12.006
into the device, so as to consider the different regions of the device conveniently. In the DC section, the VDMOS device is seen as a normal MOS device with four series resistors. The influences of the special effects upon the resistors in the different regions have been considered during the modeling. In the AC section, the three important capacitances, Cgd, Cgs and Cds, have been modeled. Finally, the comprehensive model is verified by the comparisons with the measured Ids_Vds curves, the Ids_Vgs curves and the capacitance curves of the 600 V-class high-voltage target VDMOS device, which show the good accuracy.
2. Device structure and model schematic diagram The VDMOS device adopts the parallel construction of the multiple cells to get the large current capability. Fig. 1a shows one cell in the VDMOS, and the N epitaxial layer is designed to withstand the high voltage. The VDMOS is symmetrical along the red dashed line in Fig. 1a. The special structure of the VDMOS makes that the normal MOS model cannot describe the electrical characteristics of the VDMOS well. As shown in Fig. 1a, in this article, we introduce four internal nodes 1, 2, 3 and 4 on the base of the three normal external nodes. So the VDMOS can be divided into five regions. Just as shown in Fig. 1a, the gate, source and the node 1 form a normal MOS structure, and it is noted that the bulk node of the MOSFET structure is shorted to the source node. Here we define the accumulation region as the part A, the parasitic JFET region composed by the two P+ bodies and N epitaxial layer as the part B, the
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
In the VDMOS, the current IA flowing through the accumulation region can be expressed as [20]:
IA ¼ W lN eff ðQ N Þ Part A
RA RB
Part B
RC
Part C
RD
dV g2 dx
ð1Þ
where W is the width of VDMOS, lN eff is the effective carrier mobility of the accumulation region, Vg2 is the quasi-Fermi potential of the accumulation region, and Q N is the carrier density of the accumulation region. Q N consists of two components, namely, the charge of the free electrons due to the ionized doping and the gate-voltage-induced charge Qin.
Q N ¼ Q in qN N tsi
Part D
ð2Þ
Here, q denotes the electron charge, while N N and tsi are the doping concentration and the thickness of the accumulation region, respectively. By substituting Eq. (2) into Eq. (1) and integrating it from node 1 to node 2, it yields Fig. 1a. The cross-section of the VDMOS cell.
region between the node 3 and the node 4 as the part C, and the region between the node 4 and the drain as the part D. For the DC model, the VDMOS device is seen as a normal MOS device with four series resistors. As shown in Fig. 1b, the influences of the four parts (the part A, B, C, D) for the DC characteristics of the VDMOS are presented as the four resistors, which are RA, RB, RC and RD, respectively. Here, the model of the normal MOS structure adopts the typical BSIM3v3 model, thereby the DC model of the VDMOS is built just by modeling the four resistors. In order to describe the AC characteristics of the VDMOS, we introduce three important capacitances, the capacitance between the gate and drain Cgd, the capacitance between the drain and source Cds and the capacitance between the gate and source Cgs. Similarly, the AC model of the VDMOS is completed by modeling the three capacitances.
3.1. The resistance model of the accumulation region (RA) In the part A, the changes of VG make the accumulation region accumulated or depleted. Thereby, we build the resistance model of the accumulation region based on the surface potential calculation method.
D
RD
4
RC
3
RB
2
Cds
RA
MOS 1
G
Z V2 W lN eff qNN tsi V 21 þ ðQ in ÞdV g2 Lt V1
Cgs
Q in ¼ C ox cG2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ut ews =ut ut ws
Fig. 1b. The equivalent circuit diagram of the SPICE model for the VDMOS.
ð4Þ
Here, Cox is the capacitance of gate oxide per unit area, cG2 is the body coefficient in the accumulation region, ws is the surface potential of the accumulation region, and ut is the thermal voltage. In Eq. (4), when ws is positive, the electron will accumulate on the surface of the accumulation region and the Qin will be negative. However, when ws is negative, the depletion layer formed by the immovable positive charge will appear on the surface of the accumulation region, and the Qin will be positive. For the strong inversion regime of the accumulation region, we consider Qin as a constant Qdep0.
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2uFg þ Dut
ð5Þ
uFg is the Fermi potential of the accumulation region. The value of Dut is several times bigger than the ut. When the accumulation region is accumulated, the Qin and the VGg2 (VGg2 = VG Vg2) are almost linear relation. Q inðacÞ ¼ C ox ðV Gg2 V FBg2 Dut Þ
ð6Þ
VFBg2 is the flat voltage of the accumulation region. In order to describe the connection between the induced charge and the gate voltage by a uniform equation, we modify Eq. (6). The equivalent surface charge can be written as [22]:
Q ina ¼ C ox ðV Gg2q V FBg2 Dut Þ
ð7Þ
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V Gg2q ¼ V Gg2min þ 0:5 V Gg2 D V Gb2min þ ðV Gg2 D V Gb2min Þ2 þ 4D
ð8Þ
Where Dut = 8ut, VGg2q is the efficient data of VGg2 and it can smoothly change from VGg2min in the strong inversion regime to the accumulation regime. D is the mathematical coefficient in order to have a smooth behavior. Bringing Q ina jV Gg2q ¼V Gg2 min ¼ Q dep0 into Eq. (7), we get:
V Gg2 min ¼ V FBg2 þ Dut S
ð3Þ
In the equation, 2Lt is the length of the accumulation region, V21 = V2 V1. As shown in Eq. (3), we must calculate Qin firstly in order to work out IA. The accumulation region and the gate oxide form the two terminal MOS structure. The Qin can be calculated as [21]:
Q dep0 ¼ C ox cG2
3. The DC model of the VDMOS
Cgd
IA ¼
Q dep0 C ox
ð9Þ
Substituting the Qin in Eq. (3) by Qina in Eq. (7), the IA can be written as:
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
Z V2 W qN N tsi IA ¼ C ox lN eff V FBg2 Dut V 21 þ V Gg2q dV g2 Lt C ox V1 ð10Þ Simplifying
Z
V2
V1
R V2 V1
V Gg2q dV g2 by Eq. (8), we get
V Gg2q dV g2 V G2q V 21 þ 0:5 V 221q
Here, ln is the electron mobility in the channel of the parasitic JFET, ND is the doping concentration of the N epitaxial layer, and b(y) = Lt Xh(y). Integrating along the channel from y = 0 to y = L, we will get the Shockley theory formula. By simplifying it, we will have the current equation of the linear region for the parasitic JFET:
ð11Þ IB ¼ b
Here, VG1 = VG V1, VG2 = VG V2, V Gg2q jV Gg2 ¼V G1 ¼ V G1q , V Gg2q jV Gg2 ¼V G2 ¼ V G2q , V21q = VG2q VG1q. The mobility of the VDMOS in the accumulation region is controlled by the lateral and vertical electric field. The stronger the vertical electric field is, the free electron will be closer to the surface and the mobility will be smaller. When the lateral electric field is overlarge, the free electron will be velocity saturation. Based on this discussion, we model the mobility empirically in Eq. (12):
lN eff ¼
1þ
l0 h
V G2 þV G1 2
V 21 1 þ Esat Lt
i
ð12Þ
where l0 is the mobility without considering the lateral and the vertical electric field, and Esat is the lateral electric field when the carrier is under the velocity saturation. By substituting Eqs. (11) and (12) into Eq. (10), the final IA will be calculated. Then we can calculate the equivalent resistance of the accumulation region by RA ¼ V 21 =IA . 3.2. The resistance of the parasitic JFET region (RB) In the part B, the channel of the parasitic JFET region can appear the depletion or the pinch-off with the voltage changes of the source, the node 2 and 3. Here, both the channel depletion and the pinch-off effects of the parasitic JFET region are taken into account carefully. We make two assumptions. Firstly, we assume that the P+ body region and the N epitaxial layer compose the parasitic JFET, and the doping of its channel is linear graded. Secondly, we suppose that the electric field of the P–N junction is one dimensional distribution and single-side abrupt junction. Considering the symmetrical structure of the parasitic JFET and the physical dimension shown in Fig. 2, the total current in the channel of the parasitic JFET is:
IB ¼ 2qln ND WbðyÞ
dVðyÞ dy
ð13Þ
i Wh 2ðV S2 V T ÞV 32 V 232 L
Here, b ¼ n0 ns ln =Lt , in which n0 is the permittivity of the vacuum and ns is the permittivity of the silicon. V32 = V3 V2, VT is the threshold voltage. If V32 is larger than V32sat, which is the pinch-off voltage of the parasitic JFET, the channel of the JFET region will be pinched off. But when V32 is increased, the dropout voltage from the pinchoff point to the node 2 will be always equal to V32sat. So the pinch-off point will move towards the node 2, and the voltage across the channel pinch-off area will be V32 V32sat. The carrier arriving at the pinch-off area will be floated to the node 3 immediately. So the current in the channel will be decided by the conductive channel region. We introduce the efficient voltage between the node 2 and 3 (V32eff) to make the continuous transition across from the linear region to the saturation region [10]. 1 V 32eff ¼ V 32sat ½ðV 32sat V 32 dÞ þ 2
IB ¼ b
i Wh 2ðV S2 V T ÞV 32eff V 232eff ð1 þ kV 32eff Þ L
Xh
Wj
b RB L
V3
α ≈ 45
Le
LV
RC
WC
RD
2Wt Y Fig. 2. The schematic diagram for the resistances of the part B, part C and part D.
ð16Þ
3.3. The resistance of the part C (RC) and the resistance of the part D (RD) In the part C of the VDMOS, the current path is shown as the red dashed line in Fig. 2. Empirically, we consider the angle a between the current path and the y axis is 45° [17]. The lateral dashed line cross the node 3 is an equipotential line with the potential of V3. The thickness of the depletion layer made by the Pbody–Nepi junction is:
1=2 2n0 ns ½U BJ þ V 3 V S qN D
ð17Þ
The boundary depletion layer decides the resistance of RC. According to the method proposed by Victory in [17],
RC ¼
W1
ð15Þ
In the same way, by RB = V32/IB, the resistance of the parasitic JFET region will be calculated.
X
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðV 32sat V 32 dÞ2 þ 4dV 32sat
Here, d is a parameter. In order to consider the channel length modulation effect, we introduce the channel modulation coefficient k = (DLV32)/L (DL is the length of the pinch-off channel).
W1 ¼
Lt
ð14Þ
q 2 tan a
ln
Wt Lt ðW 1 gW j Þ
ð18Þ
As shown in Fig. 2, 2Wt is the length of the device, Wj is the thickness between the node 2 and the lower boundary of P+ body. g is the model parameter with the value of about 0.16, which takes into account the lateral diffusion [15]. The cross-section of the current path in part D keeps invariant. So the resistance of this part simply connects to Wc, which is the width between the node 3 and the node 4.
RD ¼ q
Wc ¼
Le W c W j þ W 1 Lv Le þ qN Wt Wt
W t Lt þ ðW 1 gW j Þ tan a
ð19Þ
ð20Þ
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
q and qN are the resistivity of the N epitaxial layer and the N+ substrate respectively. Le is the thickness from the node 2 to N epitaxial layer. LV is the width across the node 2 to the bottom of the N+ substrate. Up to now, the four series resistances have been calculated carefully, and we have completed the DC model of the VDMOS finally. 4. The AC model of VDMOS It is noted that VDMOS is usually applied in the switching mode, so the AC model of the device is very important for the circuit simulation. Considering the high-frequency application of the target VDMOS, the gate voltage (>0 V) will have small influence upon the capacitances Cgs and Cgd. In addition, for Cds, it is mainly a depletion capacitance made of by the vertical Pbody–Nepi junction, the depletion width is directly affected by drain voltage. Thereby, the Cds cannot change too much at the same drain voltage, though the gate voltage is increased (the gate voltage only affects a small number of surface junction capacitance for Cds). Consequently, in this paper, the relations between the three capacitances and drain voltage will be concerned. 3.4. The model of Cgd The miller capacitance Cgd is one of the decisive factors for the AC characteristic of VDMOS. As shown in Fig. 1, The miller capacitance Cgd is exhibited by two capacitances C 0ox and Cc connected in series [21]. That is:
1 1 1 ¼ þ C gd C 0ox C c
ð21Þ
Cc is the surface capacitance above the N-epi layer. C 0ox is the total gate oxide capacitance above the N-epi layer, which can be calculated by the following equation:
C 0ox
nsio2 ¼ C ox W Lt ¼ W Lt t ox
ð22Þ
where tox is the thickness of the gate oxide, nsio2 is the permittivity of the SiO2. The capacitance Cc mentioned in [23,24] is:
C ox C C ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi W Lt 2V DG C 2ox 1 þ qns NN 1
ð23Þ
By substituting Eqs. (22) and (23) into Eq. (21), we obtain the miller capacitance Cgd finally. 3.5. The model of Cds As shown in Fig. 1, the capacitance Cds is mainly a depletion capacitance made of by the vertical Pbody–Nepi junction diode. According to the capacitance model of diode, we set the model of Cds as follows:
mj VD VS C ds ¼ C jeff 1 þ pb
ð24Þ
where Cjeff is the zero-bias junction capacitance, pb is the junction built-in potential, and mj is the varying coefficient of the junction capacitance. 3.6. The model of Cgs The capacitance Cgs consists of the channel capacitance and the overlap capacitance between the gate and source. Along with the
rise of Vds, the capacitance Cgs firstly rises and then nearly keeps constant. According to this analysis, we set up the model of Cgs empirically:
C gs ¼ C gs1
1 þ C gs2 ðV D V S Þ 1 þ C gs3 ðV D V S Þ
ð25Þ
Cgs1, Cgs2 and Cgs3 are all model parameters. By describing the three capacitances, we have built the AC model of the VDMOS. 5. The verification of the DC and AC models In order to verify the accuracy of the above DC and AC models, the Ids_Vds curves, the Ids_Vgs curves and the capacitance curves of the 600 V-class high-voltage target VDMOS device have been measured. The main structure and doping parameters of the target VDMOS have been shown in Table 1. The DC and AC models of VDMOS device have been implemented by the Verilog-A languages, which are supported by main commercial simulators. By loading the measured data and the models into the software for the model building, such as IC-CAP (developed by Agilent) and MBP (developed by Accelicon), we verify the accuracy of the presented models. Table 2 indicates the used main model parameters for the target VDMOS device. Fig. 3(a and b) shows the measured Ids_Vds curves and the model fitting results of the target VDMOS at the linear and logarithmic scales, respectively. Fig. 3(c and d) shows the measured Ids_Vgs curves and the model fitting results of the target VDMOS at the linear and logarithmic scales, respectively. From the figures, we can see the quasi-saturation effect. When the voltage of Vgs is more than 6 V, the value of Ids does not increase obviously with the increase of Vgs. It is clear that the DC model proposed in the paper gives the accurate description for the quasi-saturation region, the
Table 1 Main structure and doping parameters of the target VDMOS. The thickness of the gate oxide The effective width of the device The channel length of the inner MOSFET Half of length in the accumulation region (Lt) The depth of the P+ body (Wj) The depth of the N epitaxial layer (Le) The length of the device (Wt) The doping concentration of the N epitaxial layer The doping concentration of the P+ body region The maximum value of the gate potential The off-state breakdown voltage
100 nm 5e5 lm 2.5 lm 3 lm 3.5 lm 56 lm 10 lm 2e14 (cm3) 3e16 (cm3) 15 V 675 V
Table 2 Main model parameters for the target VDMOS. The main parameters for the normal MOSFET: +Vth0 = 3.60622 u0 = 0.462203 +uc = 4.65E11 Vsat = 5E4 +ags = 2.35234 rdsw = 1.35721E3
ua = 1.85462E9 a0 = 1.15
The parameters for the DC characteristics of the VDMOS: +VGg2min = 2.936 D = 0.835 +l0 = 0.306 V32sat = 1.462 +VT = 1.01286 k = 0.995 +qN = 6.413
Esat = 0.84 d = 0.218 q = 4.753
The parameters for the AC characteristics of the VDMOS: The parameters for Cgd +Cox = 3.45E8 C 0ox ¼ 5:2E 10 The parameters for Cds +Cjeff = 2.16E10 pb = 0.61 The parameters for Cgs +Cgs1 = 2.21E10 Cgs2 = 0.63
NN = 2.46E14 mj = 0.665 Cgs3 = 0.503
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
Ids_Vds
(a) 1.0
Vgs[V] 15.0 13.0 7.0 6.0 5.0 4.7 4.4 4.1
Model Measurement data Vgs=15V
0.8
Ids (A)
0.6
linear region and the saturation region. Fig. 4 shows the validation of the AC model for Cgd, Cds and Cgs of the device, and the voltage of the large-signal between gate and source is 0 V. Along with the increase of Vds, the accumulation region trends to deplete and the width of the depletion layer becomes wider gradually, which
Cgd
0.4
(a) 540 0.2
measure data model
480 Cgd
5
10
20
Vds (V) Ids_Vds
Vgs[V]
1
15.0 13.0 7.0 6.0 5.0 4.7 4.4 4.1
Vgs=15V
0.1
Ids (A)
measure data model
480
15
360
420 360
300
Cgd (pF)
Vgs=4.1V
Cgd (pF)
0
(b)
540
420
0.0
240
300 240 180
180
120 60
120
0 0
60
10
30
40
50
Vds (V)
0
Vgs=4.1V
0
100
200
300
400
500
600
Vds (V)
Model Measurement data
0.01
20
Cds
(b) 240 0
5
10
15
20
measure data model
200
Cds 240
Vds (V)
Ids (A)
0.8 0.6
160
160 Cds (pF)
Vds=20V
Measurement Data Model
1.0
Vds[V] 0.1 1 4 8 12 16 20
Cds (pF)
Ids_Vgs
(c) 1.2
measure data model
200
120
120 80
80 40
40
0 0
0
100
200
60
80
100
300
400
500
600
Vds (V)
0.0 15
Vgs (V) Ids_Vgs
Vds[V] 0.1 1 4 8 12 16 20
Vds=20V
1 0.1
0.01
Cgs
(c) 285 270 285
255 270
240
Vds=0.1V
1E-3 Measurement Data Model
1E-4
measure data model
Cgs
Cgs (pF)
10
Cgs (pF)
5 Vds=0.1V
0
Ids (A)
40
0
0.2
(d)
20
Vds (V)
0.4
225
measure data model
255
240
225
210 0
1E-5
20
40
210 0
2
4
6
8
10
12
14
16
Vgs (V) Fig. 3. The DC curves of the measured data and the model fitting results for the target VDMOS.
0
100
200
300
60
Vds (V)
400
80
500
100
600
Vds (V) Fig. 4. The AC curves of the measured data and the model fitting results for the target VDMOS.
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
makes the decrease of Cgd. Similarly, the depletion region of parasitic Pbody–Nepi junction widens along with the increase of Vds and the capacitance Cds decreases rapidly. As shown in Fig. 4, the simulation curves not only describe the variation tendency of the three capacitances along with the increase of Vds, but also present the good agreement with the measured data. 6. Conclusion In this paper, a comprehensive model of the high-voltage VDMOS for the circuit simulation is set up. In the DC section, we treat the VDMOS as a normal MOS with four series resistors. In the AC section, we consider three important capacitances, which are Cgd, Cgs and Cds. In terms of the model verification with the actual measured data of the target VDMOS, the model provides the accurate description in all operation regions for both DC and AC characteristics. Acknowledgements The authors would like to thank the National Natural Science Foundation of China (61204083, 61306092), the Natural Science Foundation of the Jiangsu province (BK20130021, BK2011059), and the Scientific Research Foundation of Graduate School of Southeast University (YBJJ1311). References [1] Luo XR, Jiang YH, Zhou K, et al. Ultralow specific on-resistance superjunction vertical DMOS With high-K dielectric pillar. IEEE Electron Dev Lett 2012;33(7):1042–4. [2] Qian QS, Sun WF, Zhu J, et al. A novel charge-imbalance termination for trench superjunction VDMOS. IEEE Electron Dev Lett 2010;31(12):1434–6. [3] Zhu J, Zhang L, Sun WF, et al. Analysis of the electrical characteristics of 600Vclass electron irradiated fast recovery superjunction VDMOS. Solid-state Electron 2013;80:38–44. [4] Chevaux Nicolas, Souza Maria Merlyne De. Comparative analysis of VDMOS/ LDMOS power transistors for RF amplifiers. IEEE Trans Microwave Theory Tech 2009;57(11):2643–51.
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A novel model of the high-voltage VDMOS for the circuit simulation Siyang Liu, Rongxia Zhu, Kan Jia, Dong Huang, Weifeng Sun ⇑, Chunwei Zhang National ASIC System Engineering Research Center, Southeast University, Nanjing, Jiangsu 210096, PR China
a r t i c l e
i n f o
Article history: Received 11 April 2013 Received in revised form 17 November 2013 Accepted 4 December 2013 Available online 29 December 2013 The review of this paper was arranged by Prof. S. Cristoloveanu Keywords: Vertical double diffused MOS (VDMOS) Model Internal nodes Quasi-saturation effect
a b s t r a c t A novel model of the high-voltage vertical double diffused MOS (VDMOS) for the circuit simulation has been presented in this paper. In the DC section of the model, the VDMOS is treated as a normal MOS device with four series resistors. In contrast to other VDMOS models, the resistance model of the accumulation region is built based on the surface potential calculation method. Moreover, both the channel depletion and the pinch-off effects of the parasitic JFET region are also taken into account carefully. In addition, the three important capacitances, Cgd, Cgs and Cds, have been considered and modeled in the AC section. The proposed complete device model is validated by the comparison with the measured data of the target VDMOS. The comparison results demonstrate that the new model gives the accurate descriptions for both DC and AC characteristics of the VDMOS device. Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction The vertical double diffused MOS (VDMOS) is one of the most important power electronic switch devices [1–5]. For the advantages of the high input resistance, the low driving power, the superior frequency characteristic and the low noise, the VDMOS has been widely used in the motor speed regulation, the Hi-Fi audio, the automotive electronics and so on [6–9]. It is noted that the SPICE (Simulation Program with Integrated Circuit Emphasis) models are the links between the physical world and the design world of the semiconductor industry [10]. Nowadays, the wide application of the VDMOS device makes its SPICE model urgently needed [11–15]. Many works have reported the SPICE model of the VDMOS device. Sanchez et al. proposed a kind of VDMOS SPICE model with the quasi-saturation effect [16]. Victory et al. built a SPICE model of the VDMOS based on the charge sheet theory, but the model did not account for the channel pinch-off effect of the parasitic JFET region [17]. Chauhan et al. developed a model of the VDMOS including the DC and AC characteristics [18]. As for the HiSIM_HV model, it was a universal model that can be suitable for HV_DMOS (LDMOS or VDMOS) [19], however, it was used for the target VDMOS at first by us with no good results. In this paper, a novel model of the high-voltage VDMOS for the circuit simulation is presented. Except for the three normal external nodes (source, drain, gate), four internal nodes are added ⇑ Corresponding author. Tel.: +86 25 83795811x8308; fax: +86 25 83795077. E-mail address: [email protected] (W. Sun). 0038-1101/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2013.12.006
into the device, so as to consider the different regions of the device conveniently. In the DC section, the VDMOS device is seen as a normal MOS device with four series resistors. The influences of the special effects upon the resistors in the different regions have been considered during the modeling. In the AC section, the three important capacitances, Cgd, Cgs and Cds, have been modeled. Finally, the comprehensive model is verified by the comparisons with the measured Ids_Vds curves, the Ids_Vgs curves and the capacitance curves of the 600 V-class high-voltage target VDMOS device, which show the good accuracy.
2. Device structure and model schematic diagram The VDMOS device adopts the parallel construction of the multiple cells to get the large current capability. Fig. 1a shows one cell in the VDMOS, and the N epitaxial layer is designed to withstand the high voltage. The VDMOS is symmetrical along the red dashed line in Fig. 1a. The special structure of the VDMOS makes that the normal MOS model cannot describe the electrical characteristics of the VDMOS well. As shown in Fig. 1a, in this article, we introduce four internal nodes 1, 2, 3 and 4 on the base of the three normal external nodes. So the VDMOS can be divided into five regions. Just as shown in Fig. 1a, the gate, source and the node 1 form a normal MOS structure, and it is noted that the bulk node of the MOSFET structure is shorted to the source node. Here we define the accumulation region as the part A, the parasitic JFET region composed by the two P+ bodies and N epitaxial layer as the part B, the
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In the VDMOS, the current IA flowing through the accumulation region can be expressed as [20]:
IA ¼ W lN eff ðQ N Þ Part A
RA RB
Part B
RC
Part C
RD
dV g2 dx
ð1Þ
where W is the width of VDMOS, lN eff is the effective carrier mobility of the accumulation region, Vg2 is the quasi-Fermi potential of the accumulation region, and Q N is the carrier density of the accumulation region. Q N consists of two components, namely, the charge of the free electrons due to the ionized doping and the gate-voltage-induced charge Qin.
Q N ¼ Q in qN N tsi
Part D
ð2Þ
Here, q denotes the electron charge, while N N and tsi are the doping concentration and the thickness of the accumulation region, respectively. By substituting Eq. (2) into Eq. (1) and integrating it from node 1 to node 2, it yields Fig. 1a. The cross-section of the VDMOS cell.
region between the node 3 and the node 4 as the part C, and the region between the node 4 and the drain as the part D. For the DC model, the VDMOS device is seen as a normal MOS device with four series resistors. As shown in Fig. 1b, the influences of the four parts (the part A, B, C, D) for the DC characteristics of the VDMOS are presented as the four resistors, which are RA, RB, RC and RD, respectively. Here, the model of the normal MOS structure adopts the typical BSIM3v3 model, thereby the DC model of the VDMOS is built just by modeling the four resistors. In order to describe the AC characteristics of the VDMOS, we introduce three important capacitances, the capacitance between the gate and drain Cgd, the capacitance between the drain and source Cds and the capacitance between the gate and source Cgs. Similarly, the AC model of the VDMOS is completed by modeling the three capacitances.
3.1. The resistance model of the accumulation region (RA) In the part A, the changes of VG make the accumulation region accumulated or depleted. Thereby, we build the resistance model of the accumulation region based on the surface potential calculation method.
D
RD
4
RC
3
RB
2
Cds
RA
MOS 1
G
Z V2 W lN eff qNN tsi V 21 þ ðQ in ÞdV g2 Lt V1
Cgs
Q in ¼ C ox cG2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ut ews =ut ut ws
Fig. 1b. The equivalent circuit diagram of the SPICE model for the VDMOS.
ð4Þ
Here, Cox is the capacitance of gate oxide per unit area, cG2 is the body coefficient in the accumulation region, ws is the surface potential of the accumulation region, and ut is the thermal voltage. In Eq. (4), when ws is positive, the electron will accumulate on the surface of the accumulation region and the Qin will be negative. However, when ws is negative, the depletion layer formed by the immovable positive charge will appear on the surface of the accumulation region, and the Qin will be positive. For the strong inversion regime of the accumulation region, we consider Qin as a constant Qdep0.
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2uFg þ Dut
ð5Þ
uFg is the Fermi potential of the accumulation region. The value of Dut is several times bigger than the ut. When the accumulation region is accumulated, the Qin and the VGg2 (VGg2 = VG Vg2) are almost linear relation. Q inðacÞ ¼ C ox ðV Gg2 V FBg2 Dut Þ
ð6Þ
VFBg2 is the flat voltage of the accumulation region. In order to describe the connection between the induced charge and the gate voltage by a uniform equation, we modify Eq. (6). The equivalent surface charge can be written as [22]:
Q ina ¼ C ox ðV Gg2q V FBg2 Dut Þ
ð7Þ
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V Gg2q ¼ V Gg2min þ 0:5 V Gg2 D V Gb2min þ ðV Gg2 D V Gb2min Þ2 þ 4D
ð8Þ
Where Dut = 8ut, VGg2q is the efficient data of VGg2 and it can smoothly change from VGg2min in the strong inversion regime to the accumulation regime. D is the mathematical coefficient in order to have a smooth behavior. Bringing Q ina jV Gg2q ¼V Gg2 min ¼ Q dep0 into Eq. (7), we get:
V Gg2 min ¼ V FBg2 þ Dut S
ð3Þ
In the equation, 2Lt is the length of the accumulation region, V21 = V2 V1. As shown in Eq. (3), we must calculate Qin firstly in order to work out IA. The accumulation region and the gate oxide form the two terminal MOS structure. The Qin can be calculated as [21]:
Q dep0 ¼ C ox cG2
3. The DC model of the VDMOS
Cgd
IA ¼
Q dep0 C ox
ð9Þ
Substituting the Qin in Eq. (3) by Qina in Eq. (7), the IA can be written as:
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Z V2 W qN N tsi IA ¼ C ox lN eff V FBg2 Dut V 21 þ V Gg2q dV g2 Lt C ox V1 ð10Þ Simplifying
Z
V2
V1
R V2 V1
V Gg2q dV g2 by Eq. (8), we get
V Gg2q dV g2 V G2q V 21 þ 0:5 V 221q
Here, ln is the electron mobility in the channel of the parasitic JFET, ND is the doping concentration of the N epitaxial layer, and b(y) = Lt Xh(y). Integrating along the channel from y = 0 to y = L, we will get the Shockley theory formula. By simplifying it, we will have the current equation of the linear region for the parasitic JFET:
ð11Þ IB ¼ b
Here, VG1 = VG V1, VG2 = VG V2, V Gg2q jV Gg2 ¼V G1 ¼ V G1q , V Gg2q jV Gg2 ¼V G2 ¼ V G2q , V21q = VG2q VG1q. The mobility of the VDMOS in the accumulation region is controlled by the lateral and vertical electric field. The stronger the vertical electric field is, the free electron will be closer to the surface and the mobility will be smaller. When the lateral electric field is overlarge, the free electron will be velocity saturation. Based on this discussion, we model the mobility empirically in Eq. (12):
lN eff ¼
1þ
l0 h
V G2 þV G1 2
V 21 1 þ Esat Lt
i
ð12Þ
where l0 is the mobility without considering the lateral and the vertical electric field, and Esat is the lateral electric field when the carrier is under the velocity saturation. By substituting Eqs. (11) and (12) into Eq. (10), the final IA will be calculated. Then we can calculate the equivalent resistance of the accumulation region by RA ¼ V 21 =IA . 3.2. The resistance of the parasitic JFET region (RB) In the part B, the channel of the parasitic JFET region can appear the depletion or the pinch-off with the voltage changes of the source, the node 2 and 3. Here, both the channel depletion and the pinch-off effects of the parasitic JFET region are taken into account carefully. We make two assumptions. Firstly, we assume that the P+ body region and the N epitaxial layer compose the parasitic JFET, and the doping of its channel is linear graded. Secondly, we suppose that the electric field of the P–N junction is one dimensional distribution and single-side abrupt junction. Considering the symmetrical structure of the parasitic JFET and the physical dimension shown in Fig. 2, the total current in the channel of the parasitic JFET is:
IB ¼ 2qln ND WbðyÞ
dVðyÞ dy
ð13Þ
i Wh 2ðV S2 V T ÞV 32 V 232 L
Here, b ¼ n0 ns ln =Lt , in which n0 is the permittivity of the vacuum and ns is the permittivity of the silicon. V32 = V3 V2, VT is the threshold voltage. If V32 is larger than V32sat, which is the pinch-off voltage of the parasitic JFET, the channel of the JFET region will be pinched off. But when V32 is increased, the dropout voltage from the pinchoff point to the node 2 will be always equal to V32sat. So the pinch-off point will move towards the node 2, and the voltage across the channel pinch-off area will be V32 V32sat. The carrier arriving at the pinch-off area will be floated to the node 3 immediately. So the current in the channel will be decided by the conductive channel region. We introduce the efficient voltage between the node 2 and 3 (V32eff) to make the continuous transition across from the linear region to the saturation region [10]. 1 V 32eff ¼ V 32sat ½ðV 32sat V 32 dÞ þ 2
IB ¼ b
i Wh 2ðV S2 V T ÞV 32eff V 232eff ð1 þ kV 32eff Þ L
Xh
Wj
b RB L
V3
α ≈ 45
Le
LV
RC
WC
RD
2Wt Y Fig. 2. The schematic diagram for the resistances of the part B, part C and part D.
ð16Þ
3.3. The resistance of the part C (RC) and the resistance of the part D (RD) In the part C of the VDMOS, the current path is shown as the red dashed line in Fig. 2. Empirically, we consider the angle a between the current path and the y axis is 45° [17]. The lateral dashed line cross the node 3 is an equipotential line with the potential of V3. The thickness of the depletion layer made by the Pbody–Nepi junction is:
1=2 2n0 ns ½U BJ þ V 3 V S qN D
ð17Þ
The boundary depletion layer decides the resistance of RC. According to the method proposed by Victory in [17],
RC ¼
W1
ð15Þ
In the same way, by RB = V32/IB, the resistance of the parasitic JFET region will be calculated.
X
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðV 32sat V 32 dÞ2 þ 4dV 32sat
Here, d is a parameter. In order to consider the channel length modulation effect, we introduce the channel modulation coefficient k = (DLV32)/L (DL is the length of the pinch-off channel).
W1 ¼
Lt
ð14Þ
q 2 tan a
ln
Wt Lt ðW 1 gW j Þ
ð18Þ
As shown in Fig. 2, 2Wt is the length of the device, Wj is the thickness between the node 2 and the lower boundary of P+ body. g is the model parameter with the value of about 0.16, which takes into account the lateral diffusion [15]. The cross-section of the current path in part D keeps invariant. So the resistance of this part simply connects to Wc, which is the width between the node 3 and the node 4.
RD ¼ q
Wc ¼
Le W c W j þ W 1 Lv Le þ qN Wt Wt
W t Lt þ ðW 1 gW j Þ tan a
ð19Þ
ð20Þ
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q and qN are the resistivity of the N epitaxial layer and the N+ substrate respectively. Le is the thickness from the node 2 to N epitaxial layer. LV is the width across the node 2 to the bottom of the N+ substrate. Up to now, the four series resistances have been calculated carefully, and we have completed the DC model of the VDMOS finally. 4. The AC model of VDMOS It is noted that VDMOS is usually applied in the switching mode, so the AC model of the device is very important for the circuit simulation. Considering the high-frequency application of the target VDMOS, the gate voltage (>0 V) will have small influence upon the capacitances Cgs and Cgd. In addition, for Cds, it is mainly a depletion capacitance made of by the vertical Pbody–Nepi junction, the depletion width is directly affected by drain voltage. Thereby, the Cds cannot change too much at the same drain voltage, though the gate voltage is increased (the gate voltage only affects a small number of surface junction capacitance for Cds). Consequently, in this paper, the relations between the three capacitances and drain voltage will be concerned. 3.4. The model of Cgd The miller capacitance Cgd is one of the decisive factors for the AC characteristic of VDMOS. As shown in Fig. 1, The miller capacitance Cgd is exhibited by two capacitances C 0ox and Cc connected in series [21]. That is:
1 1 1 ¼ þ C gd C 0ox C c
ð21Þ
Cc is the surface capacitance above the N-epi layer. C 0ox is the total gate oxide capacitance above the N-epi layer, which can be calculated by the following equation:
C 0ox
nsio2 ¼ C ox W Lt ¼ W Lt t ox
ð22Þ
where tox is the thickness of the gate oxide, nsio2 is the permittivity of the SiO2. The capacitance Cc mentioned in [23,24] is:
C ox C C ¼ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi W Lt 2V DG C 2ox 1 þ qns NN 1
ð23Þ
By substituting Eqs. (22) and (23) into Eq. (21), we obtain the miller capacitance Cgd finally. 3.5. The model of Cds As shown in Fig. 1, the capacitance Cds is mainly a depletion capacitance made of by the vertical Pbody–Nepi junction diode. According to the capacitance model of diode, we set the model of Cds as follows:
mj VD VS C ds ¼ C jeff 1 þ pb
ð24Þ
where Cjeff is the zero-bias junction capacitance, pb is the junction built-in potential, and mj is the varying coefficient of the junction capacitance. 3.6. The model of Cgs The capacitance Cgs consists of the channel capacitance and the overlap capacitance between the gate and source. Along with the
rise of Vds, the capacitance Cgs firstly rises and then nearly keeps constant. According to this analysis, we set up the model of Cgs empirically:
C gs ¼ C gs1
1 þ C gs2 ðV D V S Þ 1 þ C gs3 ðV D V S Þ
ð25Þ
Cgs1, Cgs2 and Cgs3 are all model parameters. By describing the three capacitances, we have built the AC model of the VDMOS. 5. The verification of the DC and AC models In order to verify the accuracy of the above DC and AC models, the Ids_Vds curves, the Ids_Vgs curves and the capacitance curves of the 600 V-class high-voltage target VDMOS device have been measured. The main structure and doping parameters of the target VDMOS have been shown in Table 1. The DC and AC models of VDMOS device have been implemented by the Verilog-A languages, which are supported by main commercial simulators. By loading the measured data and the models into the software for the model building, such as IC-CAP (developed by Agilent) and MBP (developed by Accelicon), we verify the accuracy of the presented models. Table 2 indicates the used main model parameters for the target VDMOS device. Fig. 3(a and b) shows the measured Ids_Vds curves and the model fitting results of the target VDMOS at the linear and logarithmic scales, respectively. Fig. 3(c and d) shows the measured Ids_Vgs curves and the model fitting results of the target VDMOS at the linear and logarithmic scales, respectively. From the figures, we can see the quasi-saturation effect. When the voltage of Vgs is more than 6 V, the value of Ids does not increase obviously with the increase of Vgs. It is clear that the DC model proposed in the paper gives the accurate description for the quasi-saturation region, the
Table 1 Main structure and doping parameters of the target VDMOS. The thickness of the gate oxide The effective width of the device The channel length of the inner MOSFET Half of length in the accumulation region (Lt) The depth of the P+ body (Wj) The depth of the N epitaxial layer (Le) The length of the device (Wt) The doping concentration of the N epitaxial layer The doping concentration of the P+ body region The maximum value of the gate potential The off-state breakdown voltage
100 nm 5e5 lm 2.5 lm 3 lm 3.5 lm 56 lm 10 lm 2e14 (cm3) 3e16 (cm3) 15 V 675 V
Table 2 Main model parameters for the target VDMOS. The main parameters for the normal MOSFET: +Vth0 = 3.60622 u0 = 0.462203 +uc = 4.65E11 Vsat = 5E4 +ags = 2.35234 rdsw = 1.35721E3
ua = 1.85462E9 a0 = 1.15
The parameters for the DC characteristics of the VDMOS: +VGg2min = 2.936 D = 0.835 +l0 = 0.306 V32sat = 1.462 +VT = 1.01286 k = 0.995 +qN = 6.413
Esat = 0.84 d = 0.218 q = 4.753
The parameters for the AC characteristics of the VDMOS: The parameters for Cgd +Cox = 3.45E8 C 0ox ¼ 5:2E 10 The parameters for Cds +Cjeff = 2.16E10 pb = 0.61 The parameters for Cgs +Cgs1 = 2.21E10 Cgs2 = 0.63
NN = 2.46E14 mj = 0.665 Cgs3 = 0.503
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Ids_Vds
(a) 1.0
Vgs[V] 15.0 13.0 7.0 6.0 5.0 4.7 4.4 4.1
Model Measurement data Vgs=15V
0.8
Ids (A)
0.6
linear region and the saturation region. Fig. 4 shows the validation of the AC model for Cgd, Cds and Cgs of the device, and the voltage of the large-signal between gate and source is 0 V. Along with the increase of Vds, the accumulation region trends to deplete and the width of the depletion layer becomes wider gradually, which
Cgd
0.4
(a) 540 0.2
measure data model
480 Cgd
5
10
20
Vds (V) Ids_Vds
Vgs[V]
1
15.0 13.0 7.0 6.0 5.0 4.7 4.4 4.1
Vgs=15V
0.1
Ids (A)
measure data model
480
15
360
420 360
300
Cgd (pF)
Vgs=4.1V
Cgd (pF)
0
(b)
540
420
0.0
240
300 240 180
180
120 60
120
0 0
60
10
30
40
50
Vds (V)
0
Vgs=4.1V
0
100
200
300
400
500
600
Vds (V)
Model Measurement data
0.01
20
Cds
(b) 240 0
5
10
15
20
measure data model
200
Cds 240
Vds (V)
Ids (A)
0.8 0.6
160
160 Cds (pF)
Vds=20V
Measurement Data Model
1.0
Vds[V] 0.1 1 4 8 12 16 20
Cds (pF)
Ids_Vgs
(c) 1.2
measure data model
200
120
120 80
80 40
40
0 0
0
100
200
60
80
100
300
400
500
600
Vds (V)
0.0 15
Vgs (V) Ids_Vgs
Vds[V] 0.1 1 4 8 12 16 20
Vds=20V
1 0.1
0.01
Cgs
(c) 285 270 285
255 270
240
Vds=0.1V
1E-3 Measurement Data Model
1E-4
measure data model
Cgs
Cgs (pF)
10
Cgs (pF)
5 Vds=0.1V
0
Ids (A)
40
0
0.2
(d)
20
Vds (V)
0.4
225
measure data model
255
240
225
210 0
1E-5
20
40
210 0
2
4
6
8
10
12
14
16
Vgs (V) Fig. 3. The DC curves of the measured data and the model fitting results for the target VDMOS.
0
100
200
300
60
Vds (V)
400
80
500
100
600
Vds (V) Fig. 4. The AC curves of the measured data and the model fitting results for the target VDMOS.
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S. Liu et al. / Solid-State Electronics 93 (2014) 21–26
makes the decrease of Cgd. Similarly, the depletion region of parasitic Pbody–Nepi junction widens along with the increase of Vds and the capacitance Cds decreases rapidly. As shown in Fig. 4, the simulation curves not only describe the variation tendency of the three capacitances along with the increase of Vds, but also present the good agreement with the measured data. 6. Conclusion In this paper, a comprehensive model of the high-voltage VDMOS for the circuit simulation is set up. In the DC section, we treat the VDMOS as a normal MOS with four series resistors. In the AC section, we consider three important capacitances, which are Cgd, Cgs and Cds. In terms of the model verification with the actual measured data of the target VDMOS, the model provides the accurate description in all operation regions for both DC and AC characteristics. Acknowledgements The authors would like to thank the National Natural Science Foundation of China (61204083, 61306092), the Natural Science Foundation of the Jiangsu province (BK20130021, BK2011059), and the Scientific Research Foundation of Graduate School of Southeast University (YBJJ1311). References [1] Luo XR, Jiang YH, Zhou K, et al. Ultralow specific on-resistance superjunction vertical DMOS With high-K dielectric pillar. IEEE Electron Dev Lett 2012;33(7):1042–4. [2] Qian QS, Sun WF, Zhu J, et al. A novel charge-imbalance termination for trench superjunction VDMOS. IEEE Electron Dev Lett 2010;31(12):1434–6. [3] Zhu J, Zhang L, Sun WF, et al. Analysis of the electrical characteristics of 600Vclass electron irradiated fast recovery superjunction VDMOS. Solid-state Electron 2013;80:38–44. [4] Chevaux Nicolas, Souza Maria Merlyne De. Comparative analysis of VDMOS/ LDMOS power transistors for RF amplifiers. IEEE Trans Microwave Theory Tech 2009;57(11):2643–51.
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