A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA

Microprocessors and Microsystems 65 (2019) 107–120

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Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro

A novel parallel duty cycle control algorithm for photovoltaic voltage regulator system using FPGA Joseph Anthony Prathap a,∗, T.S. Anandhi b a b

Department of Electronics & Communication Engineering, Vardhaman College of Engineering, Hyderabad, India Department of Electronics & Instrumentation Engineering, Annamalai University, Chidambaram, India

a r t i c l e

i n f o

Article history: Received 27 April 2018 Revised 9 November 2018 Accepted 12 January 2019 Available online 15 January 2019 Keywords: Field programmable gate array Maximum power point tracking algorithm Digital PI control Digital pulse width modulation techniques DC-DC buck converter

a b s t r a c t In this paper, a novel parallel duty cycle control method is proposed to regulate the load voltage of the photo voltaic (PV) fed DC-DC buck converter. The proposed method concentrates on the control of PV fed DC-DC buck converter by fusing the two duty cycles from maximum power point tracking (MPPT) and digital proportional integral-digital pulse width modulation (DPI-DPWM) through the HDPWM algorithm. The fusion of the MPPT algorithms and DPI-DPWM algorithms achieve high precision in the voltage regulation of the PV fed DC-DC buck converter. The proposed parallel duty cycle control is passed through the HDPWM algorithm to compensate the high clocking frequency demand with the design resolution of 210 bits. Further, the design complexity of the HDPWM algorithm is reduced as the resolution of 210 bits is split as 25 and 25 bits for CDPWM and DDPWM respectively. The FPGA based implementation of the proposed parallel duty cycle method includes the synthesizable VHDL code for i) MPPT algorithms, ii) DPI-based DPWM algorithms, iii) Fusing of the MPPT-DPI-DPWM and iv) Passing the fused MPPT-DPIDPWM through the HDPWM algorithm. The Xilinx Spartan 3A DSP, FPGA implementation is suitable for the proposed parallel duty cycle control method. The hardware results validate the satisfactory PV voltage regulation under continuous changing weather conditions. The transient response of INC-DPI-HDPWM seems to have a faster settling time compared to other MPPT-DPI-DPWM methods. Also, its FPGA implementation proves less area in design and low power consumption compared to the existing methods. © 2019 Elsevier B.V. All rights reserved.

1. Introduction The PV is the most common renewable energy source across the globe for its dependency on the Sun’s radiation. Practically, the PV module exhibits low power conversion efficiency when subjected to varying atmospheric conditions. In order to overcome this issue, the MPPT techniques are required to extract the maximum power from the PV module. Conventionally, there are several types of MPPT algorithms like open circuit voltage, short circuit current, curve fitting, P&O, and INC. But the MPPT algorithms show instability in the voltage regulation of any PV fed systems. In order to stabilize the voltage regulation of the PV fed systems, the MPPT should be able to track the continuous and rapid changes of the irradiance. Though many modified MPPT algorithms have been modeled for the improvement of continuous tracking, the speed of tracking has to be enhanced. The evolution of hybrid MPPT algorithms proves to enhance the voltage regulation of the PV fed systems

∗

Corresponding author. E-mail address: [email protected] (J.A. Prathap).

https://doi.org/10.1016/j.micpro.2019.01.004 0141-9331/© 2019 Elsevier B.V. All rights reserved.

The real-time implemented P&O algorithm has acceptable reliability [1] and is highly competitive against INC MPPT algorithms for its easy implementation [2]. When properly optimized, the P&O method could have the same MPPT efficiency as the INC method. The main weakness of the P&O method is the oscillations around the MPP and could be overcome effectively by developing optimal operating points using the nonlinear method [3]. The integration of the P&O method and twin axis solar tracker uniformly maximizes the irradiance to the solar module [4]. The accurate temperature control of the solar panel and the tracking of MPPT could be achieved by using an indoor lightening system [5]. Comparatively the INC algorithm exhibits reduction in steady state oscillations with the sudden increase in the solar irradiation [6]. The constant voltage based INC algorithm combined with a solar tracker increase its convergence speed and reduce the computational complexity [7]. The fractional-order Integrator based conventional INC method ensures faster tracking accuracy for the MPP under varying climatic conditions [8]. The INC based on constraint fuzzy logic controller method removes the unnecessary oscillations at the best operating point in transient time and steady states [9]. The variable step P&O MPPT algorithm has a fast dynamic response under

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Nomenclature b dFB dPV ess td tp tr ts DVIPV’ DVFB DVPV’ DVREF ESR(C) ESR(L) Fsw Imp IPV ISC KI Np Ns Pmax VFB VIN VLOAD Vmp VO VOC VIPV’ VPV VPV’ d τ I P V %MP

bias value duty cycle from the DPI-DPWM algorithm duty cycle from the MPPT algorithm steady state error delay time peak time rise time settling time digital PV current in 210 -bit resolution digital feedback voltage in 210 -bit resolution digital PV voltage in 210 -bit resolution digital set point value, in 210 -bit resolution equivalent series resistance capacitor equivalent series resistance inductor switching frequency maximum current PV current short circuit current current temperature coefficient number of PV cells in parallel number of PV cells in series maximum power feedback voltage input voltage load voltage maximum voltage output voltage open circuit voltage PV current from SCC PV voltage PV voltage from SCC total duty difference in current difference in power difference in voltage percentage peak overshoot

rapid solar irradiance variations [10]. The automatically adjustable step size MPPT algorithm produces a better dynamic response and less steady state oscillations [11]. The Fractional Order INC MPPT method has features like (a) ensuring the maximum amount of energy transferred to the battery or the load, (b) reducing the tracking time, tracking number, and switching number, (c) easy to implement in a single-chip embedded system [12]. The FPGA based PWM control enables rapid system prototyping capabilities with a reduction in the power converter size [13]. The simulation results of synergetic control based MPPT algorithm precisely tracks and behave robustly to the abrupt changes of sun’s irradiation [14]. The mathematical model of second order sliding mode control strategy with INC MPPT presents fast response and less chattering [15]. The hybrid simplified accelerated particle swarm optimization based MPPT algorithm for partially shaded conditions provide cheaper hardware implementation [16]. To overcome the dynamic partial shading and increasing the solar energy utilization, the hybrid Adaptive Multi-context Cooperatively Coevolving Particle Swarm Optimization - Minimum Control Unit (AMCCPSO-MPC) algorithm is utilized for marine photovoltaic systems [17]. Theoretical analysis and simulation results of PV pumping system based on finite time slide mode control of the MPPT leads to tracking error convergence to zero in pre-specified finite time [18]. The LUO converter based MPPT controller proves to have reduced ripple, fast response and cost-effective [19].

The main disadvantage of the existing methods is that the MPPT could not evaluate the attainment of MPP, thus leading to oscillation around the MPP. The hybrid PID-P&O MPPT could improve the settling time, stabilize the oscillation around the MPP and reduce the losses [20]. Though the PID controller could broaden its operation by using a distributed order PID controller [21], the Digital PI controller is preferred for FPGA implementation. The FPGA implemented DPI is utilized as the derivative term is influenced by the noise which affects the steady state of the voltage regulator. The duty cycle control of DPI-based DPWM system is advantaged in many power applications. DPWM techniques involve the logic circuits using ring oscillators, delay elements, flip-flops, high-resolution ADC, digital PWM block in digital controllers and a time-based controller to eliminate the wide bandwidth error [22]. The unified Multimode digital control implemented in FPGA device can achieve the smooth controller transition [23]. The FPGA based implementation is suitable for MPPT algorithms as the measurement principle used in the FPGA circuit is capable of rejecting the switching disturbances during current and voltage measurements [24]. The inclusion of the artificial neural network with FPGA exhibits effective control of the duty cycle for the boost converter [25]. The FPGA prototype used for the fuzzy logic based MPPT algorithm ensures the optimal operation of the PV system with reduced complexity [26]. The contribution of this work is the novel parallel duty cycle algorithm which specifies the control of the proposed HDPWM by using both the MPPT duty cycle and DPI-DPWM duty cycle. The parallel computing of duty cycles involves the combination of the on-line MPPT methods like P&O and INC MPPT algorithms and DPIDPWM controller with HDPWM for the voltage regulation of the PV fed DC-DC buck converter using Xilinx Spartan 3A DSP FPGA. In varying weather conditions, the proposed parallel duty control provides high-speed performance and exhibits good stability in voltage regulation of the DC-DC buck converter. The VHDL development of proposed MPPT-DPI-DPWM controller algorithms is tried with six combinations by taking into consideration the two MPPT algorithms and three DPWM techniques. The rest of this paper is organized as follows. Section 2 gives an overview of the proposed parallel computing of duty cycle for the voltage regulation of the DC-DC buck converter. Section 3 presents the flow diagram of the proposed method used in the FPGA implementation. Section 4 presents the hardware implementation of the proposed parallel duty cycle control. Section 5 provides a discussion of the results achieved and a comparison of the proposed design with the existing methods. Finally, Section 6 concludes this paper. 2. The proposed method The proposed novel parallel duty cycles control method presents the voltage regulation of the closed loop PV fed DC-DC buck converter with the DC load. As presented in Fig. 1, the voltage from the PV module is fed as the input VIN to the DC-DC Buck converter. Also for the purpose of duty cycle control, the input values of voltage as VPV and current as IPV are measured through the PV panel, and fed as inputs to the signal conditioning circuit (SCC). The SCC compensates the measured voltage VPV and current IPV with the FPGA device operating ranges. The SCC compensation is mandatory for the digital FPGA controller as the maximum permissible voltage is 5 V. The SCC uses the Hall Effect sensor for scaling down the measured current value IPV in terms of voltage represented as V’IPV and voltage value VPV as V’PV . Simultaneously, the feedback voltage VFB from the DC-DC buck converter is also fed into the FPGA as V’FB . The SCC outputs the voltage values for V’PV , V’IPV , and V’FB as fractional real values. For the sake of FPGA implementation,

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Fig. 1. Block diagram of the proposed photovoltaic based voltage regulator system.

the VHDL code is developed so as to convert the voltage values, namely V’PV , V’IPV, and V’FB into DV’PV , DV’IPV, and DV’FB by the use of Analog to Digital Converter (ADC) IC 7266. The three digitized values of DV’PV , DV’IPV, and DV’FB from the ADC IC have separated for two parallel operations, namely i) MPPT algorithm (DV’PV & DV’IPV ) and ii) DPI-DPWM generation (DV’FB ). The choice of selecting both the digitized MPPT algorithms and the DPI based DPWM is provided within the VHDL code. The developed VHDL code for the DPI based DPWM provides the choice of selecting one of three DPWM generation algorithms, namely Counter based DPWM (CDPWM), Delay-line based DPWM (DDPWM) and Hybrid based DPWM (HDPWM). The DPI is used for the control of the buck converter because the proportional term is zero when the set point is reached, and the residual value of the Integral term creates the moving bias to eliminate the offset. The DPI is developed using VHDL code with the 210 bits resolution. Based on the selection of the MPPT algorithms and DPI-DPWM techniques, the FPGA computes in parallel the MPP to generate the first duty cycle as ‘dPV ’ and the DPI-DPWM to generate the second duty cycle as ‘dFB ’. Both duty cycles are assigned with 210 -bit resolution. The novelty of the proposed method is the accurate detection and control of the minute changes in both duty cycles from MPPT and DPI-DPWM algorithms. For this purpose, the OR gate is specifically selected in the design. The OR gate is chosen because even a bit value change in any of the 210 bits duty cycles will reflect in the control of the effective voltage regulator. Thus the minute changes in the MPPT and DPI-DPWM are detected and controlled by combining both duty cycles (dPV and dFB ), to get total duty of dT . The duty cycle ‘dT ’ along with the bias ‘b’ is used as the input for the HDPWM generation to generate dNEW . Fig. 1 depicts the block diagram of the proposed parallel duty cycle control algorithm for the PV fed DC-DC buck converter. 3. Flow diagram of the proposed method

Fig. 2. The flow diagram of proposed parallel duty cycle control for PV fed DC-DC buck converter.

The flow diagram of the proposed method is depicted in Fig. 2. The code for the proposed method is developed in VHDL language. The proposed method has design challenges both in VHDL code and hardware implementation. As the flow diagram suggests, the SCC is utilized for the compensation of the PV operating the range of voltage and current with the FPGA device. Also, the SCC uses Hall Effect sensor for the conversion of current in the form of voltage. The VHDL code is developed such that, the SCC output values say V’PV , V’VPV , and V’FB are scaled down within the FPGA device range. The behavioral model of the VHDL code separates the digi-

tized values as DV’PV and DV’VPV for MPPT duty cycle control and DV’FB for DPI-based DPWM duty cycle control. The choice of MPPT algorithms (P&O and INC) and DPI-based DPWM techniques (CDPWM, DDPWM, HDPWM) are provided within the structural model of the VHDL code. According to the selection of MPPT and DPWM techniques, the duty cycles are generated as dPV and dFB with 210 bit resolution. The dT is obtained by the logical or operation of dPV and dFB . Also, the VHDL code is developed by combining the OR operation and the HDPWM to generate the regularized duty cycle

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Fig. 3. Flow diagram of the MPPT algorithm.

Fig. 4. The flow diagram for the DPWM generation using CDPWM, DDPWM and HDPWM.

as dNEW. The bias is considered along with the developed VHDL to avoid saturation of the duty cycle when initialized. The input voltage VIN for the buck converter is taken from the PV module (VPV ). From the flow diagram, the proposed method controls the PV fed DC-DC buck converter for the following. i) Selection of MPPT algorithms The MPPT algorithms like P&O and INC are developed using the VHDL code. Fig. 3 depicts the flow diagram of the MPPT algorithm

using Xilinx Spartan 3A DSP FPGA. The sensed solar voltage and current are fed as solar inputs to the FPGA. The flow of operation in obtaining the MPP differs based on the algorithm and are summarized as ➢ P&O algorithm is used to track the maximum power. It is an online technique and most preferred for its simplicity and easy implementation. In this work, the direct duty ratio P&O method is used for which D is taken as the control parameter. The P&O

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Fig. 5. Proves the control of the proposed parallel INC-DPI-HDPWM generation with switching frequency FSW = 23 KHz and at three different time scale points say at 15 μs, 24.99 μs & 68.06 μs for setpoint of 10 V and VPV ∼ 17 V.

algorithm senses the PV output voltage (VPV ) and output current (IPV ) to calculate the power and utilizes the voltage and power for updating the MPP. For every iteration, P and V are compared with zero and if positive the operating point is at the left of the MPP and the duty cycle of the converter is decreased and if negative its vice versa. The increase and decrease of the duty cycle by a constant step size track the MPP. Selection of step size plays a vital role in the rate of MPP tracking. ➢ INC algorithm is also an online method which overcomes the drawback of oscillations present in the P&O method. The operation of the INC algorithm involves the voltage and current for tracking the MPP. The V and I are related using a formulation with the V & I to check for several conditions. V and I are related to and compared with the following three conditions (1)–(3) as

dI I + =0 dV V

(1)

dI I + >0 dV V

(2)

dI I + <0 dV V

(3)

Depending on the condition satisfied, the MPP is adjusted either towards the right or the left directions. If the above expression is equal to ‘0’, the operating point has no change in MPP. If the expression produces a positive value, then the operating point is on the left side of the MPP and the duty cycle of the converter

is decreased. If the expression produces a negative value, the operating point is on the right side of the MPP and the duty cycle of the converter is increased. The developed VHDL code for the proposed method provides the choice of selecting one of the MPPT algorithms. ii) Selection of DPI-DPWM techniques The feedback value VFB from the DC-DC buck converter is taken into the FPGA through the ADC AD7266. Then the FPGA compares the actual value with the reference value to generate the error. The error enables the DPI to select the step size. The VHDL code for the DPI-DPWM is developed for all three types of DPWM techniques. They are ➢ Counter based DPWM In the CDPWM generation method, an asymmetric carrier wave is generated by the counter. The switching period value is equivalent to the highest count value. The first comparator block finds the initial value match (namely zero “0”) of the counter. This is referred to as “zero value match” (ZVM). The second comparator block finds the match value between the counter and the digitized DC input value. This is referred to as “DC value match” (DCVM). The ZVM is the input to the SET and DCVM is the input to the RESET of the SR-flip-flop. The SR-flip flop is triggered by these two signals, namely SET and RESET to generate the DPWM. ➢ Delay line based DPWM The DDPWM generation method involves the 210 ring counter, 1024:1 multiplexer and SR-flip flop. The converted 10-bit duty value is fed as the select line for 1024:1 multiplexer. The 210

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Fig. 6. (a). The startup transient response of the P&O MPPT DPI CDPWM controlled DC-DC buck converter Experimental results of the P&O MPPT DPI CDPWM controlled DC-DC buck converter. (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD .

ring counter is connected to the input side of 1024:1 multiplexer through 1024 D-flip flops. The SET signal of SR-flip flop is enabled by the 1023rd pin of the ring counter through its corresponding D-flip flop. The RESET signal of SR-flip flop is enabled by 1024:1 multiplexer output. Thus the DPWM is generated by the SR-flipflop to operate the DC-DC buck converter. ➢ Hybrid based DPWM The HDPWM generation method is the combinations of both CDPWM and DDPWM methods. The DC input signal of 210 resolutions is split into two 25 -bit resolutions. In which one half 25 bit resolution is used for the generation of the DDPWM generation and the other half 25 -bit resolution is used by the CDPWM generation. The HDPWM has two SETs and RESETs signals (each from CDPWM and DDPWM generations). These two SET signals and RESET signals are logically AND for the set and reset input of the SR-flip-flop. The choice of using DPWM techniques is depicted in Fig. 4.

iii) Parallel computing of generating duty cycles (dVPV’ and dVFB’ ) The parallel computing of the duty cycles from the MPPT algorithm and the DPI-DPWM technique is combined using the logical OR to generate the duty cycles ‘dT ’ in 210 bits. The OR gate is specially chosen because even one-bit value change in any of the 210 bits duty cycles will reflect in the control of the effective voltage regulator. The FPGA implementation is suitable for the parallel computing of the proposed method. iv) Bias in hardware implementation Practically, the bias ‘b’ is provided as the safety measure for the proposed control method because the duty cycle generated has to maintain at the minimum percentage value say 10% to avoid saturation. Without bias, the voltage regulation of the PV fed system may partially or may not be controlled. The bias value is assumed at 12% of the maximum PV voltage that is, 2.04 V converted as “0 0 01101001” for the 210 -bit resolution in the developed VHDL code

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Fig. 7. (a). The startup transient response of the P&O MPPT DPI DDPWM controlled DC-DC buck converter Experimental results for P&O MPPT DPI DDPWM controlled DC-DC buck converter (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD .

Table 1 Specification of the PV module.

v) HDPWM control The HDPWM is utilized for the overall control of the combined duty cycle from the output of the OR gate. The HDPWM technique has proved to be validated for the digital control of voltage regulation in DC-DC converter [27]. The inclusion of the HDPWM provides faster voltage regulation of the converter. The flow diagram of the proposed parallel duty cycle control algorithm for the PV fed Voltage regulator is depicted in Fig. 4 4. Hardware implementation of the proposed method This section discusses the hardware implementation of the proposed method. The proposed method is given with the PV source supply of two inputs namely voltage and current. The PV module has 36 cells in series. Each cell in the PV module consumes 0.472 V and thus the total voltage at maximum power Vmp = 17 V. The maximum power Pmax for the specified PV module is 59.5 W. The specification of the PV module used in the proposed method is given in Table 1. In order to make use of the available PV supply into the proposed method through the FPGA, the SCC is utilized. The SCC is used to scale down the maximum PV Voltage of 17 V as 4.25 V for the FPGA device. The scale down value of 0.25 compensates for

Parameters

Values

Open circuit voltage VOC Short circuit current ISC Voltage at maximum power Vmp Current at maximum power Imp Maximum power Pmax Current temperature coefficient KI Number of cells in series Ns Number of cells in parallel Np

21.20 V 4.03 A 17 V 3.50 A 59.5 W 2.80 mA/C 36 1

Table 2 Specification of the DC-DC buck converter. Laboratory prototype of the buck converter Vo Vin L C ESR(L) 20 V

10 V

15 mH

10 μF

0.001 Ω

ESR(C)

Load

Fsw

0.6 Ω

10 Ω

20 KHz

the PV voltage range with the FPGA. Also, the PV module current passes through the Hall Effect sensor, designed in the SCC to measure the equivalent voltage. The current rating 3.5 A is compensated as 5 V for the FPGA. The SCC device plays a vital role in the real data acquisition of the PV voltage and current for the FPGA

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Fig. 8. (a). The startup transient response of the P&O MPPT DPI HDPWM controlled DC-DC buck converter Experimental results for P&O MPPT DPI HDPWM controlled DC-DC buck converter (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD. Table 3 Start-up transient with the timing parameters for the proposed parallel duty cycle control for DC-DC buck converter. Method

Settling Time (ts ) Rise Time (tr ) Delay Time (td ) Peak Time (tp ) Steady State Error (ess ) Percentage Overshoot (%MP) Setpoint value (SP)

Proposed method

[22]

[28]

[29]

[30]

[37]

P&O with CDPWM

P&O with DDPWM

P&O with HDPWM

INC with CDPWM

INC with DDPWM

INC with HDPWM

35.34 μs 0.02 μs 0.01 μs 0.03 μs 0.1481

31.11 μs 0.08 μs 0.07 μs 0.06 μs 0.1111

23.21 μs 0.02 μs 0.01 μs 0.03 μs 0.0769

20.77 μs 0.04 μs 0.03 μs 0.23 μs 0.1429

8.55 μs 0.02 μs 0.01 μs 0.03 μs 0.1724

2.14 μs 0.02 μs 0.01 μs 0.03 μs 0.1111

0.380s 0.0181s – – –

0.045 s – – – 0.013

4.1 ms 1.45 ms – – –

22.7ms 14.2ms – – –

1.6 ms 1.4 ms – – 0.6

64%

68%

44%

76%

60%

56%

0.51%

60%

30%

0%

–

10

10 V

10 V

10

10 V

10 V

–

–

–

–

–

inputs. The DC-DC buck converter is directly fed with the PV voltage (VIN ). The design specification for the DC-DC buck converter used in this work is given in Table 2. At this stage, the FPGA continuously imports values of VPV (0– 17 V), VIPV (0–3.5A) and VFB (0–5 V) through the ADC IC 7266. As per the required evaluation, the FPGA initiates the selection of the MPPT algorithm and DPI-DPWM techniques. The proposed method

could generate six possible combinations for the voltage regulation. The DPI controller is included with all combinations, namely P&O with CDPWM, P&O with DDPWM, P&O with HDPWM, INC with CDPWM, INC with DDPWM and INC with HDPWM. The use of the MPPT algorithm and DPI-DPWM generate two duty cycles in 210 bits. Logically, the two duty cycle controls dPV and dFB are combined using the OR gate. The choice of the OR gate assures that the

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Fig. 9. (a). The startup transient response of the INC MPPT DPI CDPWM controlled DC-DC Buck Converter Experimental results of the INC MPPT DPI CDPWM controlled DC-DC Buck Converter. (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD.

single bit change in any of the two duty cycle controls of the DCDC buck converter effectively. The setpoint voltage VREF = 10 V for the DC-DC buck converter is fixed for the experimental evaluation of the proposed method. The experimental duty cycle control for the PV fed voltage regulator is given in Fig. 5. The Fig. 5 presents the startup transient for the voltage regulator with the duty cycle at 75%, while the proposed method starts to control the voltage, the duty is maintained at 59%–60% for the set point VREF = 10 V as given at different instants of time. Figs. 6(a), (b), 7(a), (b) and, 8(a), (b) prove the start-up transient response and the steady-state response of the proposed method using the P&O-DPI-DPWM algorithm for regulating the DC-DC buck converter. The time transient parameters like ts , tr , td , tp , ess and %MP are evaluated. The experimental result for the P&O-DPIHDPWM settles fast in 23.21 μs and steady-state error is 0.0769 with overshoot has 44%. The proposed DPI-HDPWM technique holds satisfactory when combined with the P&O MPPT algorithm in FPGA implementation. The startup transient for VVPV , VIPV and VLOAD using the P&O based DPI-DPWM techniques are shown in the Figs. 6(c), 7(c) and 8(c) respectively. The INC-DPI-DPWM techniques are validated by the FPGA implementation proves that the INC-DPI-HDPWM technique is good with settling time as minimum

as 2.14 μs. Figs. 9(a), (b), 10(a), (b) and 11(a), (b) depict the start-up transient response and the steady-state response of the proposed method using INC MPPT-DPI-DPWM algorithm. The startup transient for VVPV , VIPV , and VLOAD are shown in the Figs. 9(c), 10(c) and 11(c) respectively. The experimental setup for the above technique is shown in Fig. 12. 5. Results and discussions The proposed novel parallel duty cycle control method is implemented for six different algorithm combinations. The six combinations are evaluated as (i) P&O-DPI-CDPWM, (ii) P&O-DPI-DDPWM, (iii) P&O-DPI-HDPWM, (iv) INC-DPI-CDPWM, (v) INC-DPI-DDPWM and (vi) INC-DPI-HDPWM. With the parallel processing of the FPGA device, the six algorithms for the voltage regulation of the DCDC buck converter are developed within the VHDL code. According to the requirement, any of these six voltage regulation algorithms can be selected. Fig. 14 depicts the structural modeling of the VHDL code for the proposed method using the Xilinx ISE tool. The VHDL code for the proposed method is represented in the form of blocks by the Register Transfer Level (RTL) schematic as depicted in Fig. 13.

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Fig. 10. (a). The startup transient response of the INC MPPT DPI DDPWM controlled DC-DC buck converter Experimental results for INC MPPT DPI DDPWM controlled DC-DC buck converter (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD.

The proposed P&O-DPI-DPWM algorithms oscillate in the voltage regulation of the DC-DC buck converter due to the oscillatory nature of the P&O MPPT method. The settling time for the P&ODPI-DPWM algorithms consume less time compared to the [22,28– 30,37], but high compared to the proposed INC-DPI-DPWM algorithms. The tracking speed of P&O-DPI-CDPWM is 35.34 μs and the area occupancy is low due to the simple circuitry in the CDPWM design. The drawback of the P&O-DPI-CDPWM is the need of high clock frequency. The proposed MPPT-DPI-CDPWM algorithms with the resolution of 210 require high clocking frequency of 20 MHz to the switching frequency of 20 KHz.This drawback is overcome by using the P&O-DPI-DDPWM which proves the improved tracking speed of 31.11 μs, whereas the area occupancy is drastically increased as the DDPWM for 210 resolution uses 1024:1 multiplexer along with a 1024 D-flip flop for the ring counter. In order to optimize the tracking speed and the area, the P&O-DPI-HDPWM is implemented. The tracking speed of 23.21 μs holds well among the proposed P&O-DPI-DDPWM algorithms. Though the area occupancy of P&O-DPI-HDPWM is very close to that of the P&O-DPI-

CDPWM, the P&O-DPI-HDPWM is preferred for lower clock frequency requirements. Also, the proposed parallel duty cycle control is implemented with INC MPPT algorithms with the three DPWM techniques to improve the tracking speed. As shown in Table 3, the tracking speed of the INC-DPI-HDPWM attains the value of 2.14 μs. The tracking speed of the other INC algorithms like INC-DPICDPWM and INC-DPI-DDPWM are 20.77 μs and 8.55 μs respectively. Table 3 proves the improvement of the proposed parallel INC-DPI-HDPWM method in comparison with [22,28–30,37] with respect to the startup time transient response and steady state response. The [30] considers the MPPT with PID to achieve the settling time of 22.7 ms and rise time of 14.2 ms. The simulated settling time for [22,29,37] are 0.380 s, 4.1 ms, and 1.6 ms respectively. Comparatively the proposed INC-DPI-HDPWM technique supersedes the existing methodology by settling in 2.14 μs. Table 4 presents the device utilization chart of the proposed method and clearly proves that the MPPT-DPI-HDPWM combination occupies less area and consumes low power. The Fuzzy based MPPT algorithm implemented using the Cyclone II 2C35 FPGA

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Fig. 11. (a). The startup transient response of the INC MPPT DPI HDPWM controlled DC-DC buck converter Experimental results for INC MPPT DPI HDPWM controlled DC-DC buck converter (b). The response of VPV along with VIN (c) response of VVPV , VIPV , and VLOAD.

Fig. 12. Experimental setup for the proposed method indicates the PV source through the SCC fed to the FPGA to control the DC-DC buck converter.

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Fig. 13. RTL Schematic view of the proposed method.

Fig. 14. VHDL code for the proposed parallel duty cycle control method in Xilinx ISE tool.

utilizes 53% (17,480 out of 33,216) for the slices and 52% (17,389 out of 33,216) for the LUTs [21]. Comparatively, the proposed INCDPI-HDPWM method when implemented using the Xilinx Spartan 3A DSP, FPGA uses 11% of the slices (1806 out of 16,640) and 7% of the LUT (2476 out of 33,280). As the number of devices is reduced, the power consumed by the proposed INC-DPI-HDPWM method is low. Table 5 depicts the power analysis of the proposed INC-DPIHDPWM method which is as low as 114.97 mW for On-Chip total power and dynamic power is 0.88 with the Xilinx Spartan 3A DSP FPGA compared to [31]. The max path delays present in the pro-

posed INC-DPI-DPWM is 1.667 ns. Due to enhanced performance of the proposed INC-DPI-HDPWM with respect to the tracking speed and area occupied, the power analysis is calculated for the proposed INC-DPI-HDPWM algorithm. The performance comparison of the proposed method based on the FPGA implementation is depicted in Table 6. The FPGA XC3SD1800A is used for the hardware implementation with the switching frequency of 20 KHz and maximum power of 59.5 W from the PV module. The tracking time required for the proposed INC-DPI-HDPWM is 2.14 μs, which is very low in comparison with the [32,33–36] as given in Table 6.

J.A. Prathap and T.S. Anandhi / Microprocessors and Microsystems 65 (2019) 107–120

119

Table 4 Device utilization chart for the proposed parallel duty cycle control for DC-DC buck converter.

Methods

Number of Sliced Flip Flops Number of 4 input LUTs Number of occupied slices Number of bonded IOBs Number of BUFGMUXs Number of DSP48As Average Fan-out of Non-clock nets

Cyclone II 2C35 FPGA

Xilinx Spartan 3A DSP FPGA P&O MPPT based CDPWM

P&O MPPT based DDPWM

P&O MPPT based HDPWM

INC MPPT based CDPWM

INC MPPT based DDPWM

INC MPPT based HDPWM

[21] Fuzzy Based MPPT

1330

2356

1362

1319

2345

1351

–

2545

3055

2572

2449

2959

2476

17,389

1814

3098

1858

1762

3049

1806

17,480

45

45

45

45

45

45

97

1

1

1

1

1

1

–

13

13

13

12

12

12

–

2.66

2.65

2.66

2.67

2.66

2.67

–

Table 5 Power analysis for the proposed method using the Xilinx Spartan 3A DSP device. Proposed method using XILINX Spartan 3A DSP FPGADevice: XC3SD1800A Package: FG676 Speed: −5

[31] Based on multiplier

[31] Based on LUT

On-Chip Total Power (mW) Dynamic Power (mW) Quiescent Power (mW) Max path delay (ns)

462.3 18.4 443.9 –

461.8 18.0 443.8 –

114.97 0.88 114.09 1.667

Table 6 Comparison of the proposed method with the existing FPGA implementation of MPPT algorithms. Converter type

Switching frequency

Maximum PV power

Technique used

Hardware device utilized

Tracking speed

Year

Work

Boost Converter Boost Converter Boost Converter Boost Converter Buck Converter Buck Converter

5 KHz 50–100 KHz 100 KHz – 100 KHz 20 KHz

80 W 1.5 kW 10 W 55 W 80 W 59.5 W

P&O P&O P&O Neuro-Fuzzy Controller INC INC-DPI-HDPWM

FPGA FPGA FPGA FPGA FPGA FPGA

564 ms 100 ms 85 ms 30 ms 2.5 ms 2.14 μs

2012 2013 2006 2012 2013 Proposed

[32] [33] [34] [35] [36] Proposed

6. Conclusion The implementation of the proposed parallel duty cycle control using Xilinx Spartan 3A DSP, FPGA in this paper proves that the transient and steady state response of DC-DC CONVERTER is satisfactory for the INC-DPI-HDPWM technique. The tracking speed of the proposed INC-DPI-HDPWM is more rapid than the existing methods. Also, the area occupancy and power consumption of the proposed INC-DPI-HDPWM technique is found to be reduced in comparison with the existing voltage regulation techniques. Future works could be directed towards high switching frequency DPWM generation interconnected with the Multi-Level Inverter. Acknowledgments The authors would like to thank the Department of Electronics and Instrumentation Engineering, Annamalai University, Chidambaram, India for the facilities and assistance provided in the laboratory. Supplementary material Supplementary material associated with this article can be found, in the online version, at doi:10.1016/j.micpro.2019.01.004.

Quartus II XC4VLX60 XC2C384 Virtex II XC3S400 XC3SD1800A

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[29] Y. Chen, C. Chang, Y. Yan, FPGA-based expert PID controller for buck DC-DC converter, Appl. Mech. Mater. 431 (2013) 215–220. [30] E.K. Anto, J. A, Asumadu and Philip Yaw Okyere, “PID-based P&O MPPT controller for off-grid solar PV systems using ziegler-nichols tuning method to step, ramp and impulse inputs, J. Multidiscip. Eng. Sci. Stud. (JMESS) 2 (July (7)) (2016) 669–680. [31] S. Chander, P. Agarwal, I. Gupta, FPGA-based PID controller for DC-DC converter, IEEE Xplorer (2010) 1–6. [32] D. Das, FPGA based implementation of Mppt of solar cell, in: Proc. 2012 National Conf. on Computing and Communication Systems (NCCCS), 2012. [33] I. Wey, S.H. Kuo, All digital folded low-area, low-power maximum power point tracking chip for photovoltaic energy conversion system, Int. J. Circuit Theory Appl. (2013). [34] N. Khaehintung, T. Wiangtong, P. Sirisuk, FPGA implementation of MPPT using the variable step-size P&O algorithm for PV applications, IEEE Int. Symp. on Communications and Information Technologies (ISCIT’06), 2006. [35] F. Chekired, C. Larbes, A. Mellit, Comparative study between two intelligent MPPT-controllers implemented on FPGA: application for photovoltaic systems, Int. J. Sustain. Energy 31 (2012) 1–17. [36] R. Faraji, A. Rouholamini, H.R. Naji, R. Fadaeinedjad, M.R. Chavoshian, FPGA-based real-time incremental conductance maximum power point tracking controller for photovoltaic systems, IET Power Electron. 7 (5) (Oct 2014) 1294–1304. [37] R. Iftikhar, I. Ahmad, M. Arsalan, N. Naz, N. Ali, H. Armghan, MPPT for photovoltaic system using nonlinear controller, Int. J. Photoenergy (2018) 1–11. Joseph Anthony Prathap was born in 1981 in Puducherry. He has obtained B.E [Electronics and Communication] and M. Tech [VLSI Design] degrees in 2003 and 2007 respectively, and the Ph.D. in FPGA based Power Converters in 2017 from Annamalai University. He has put in 14 years of service in teaching and research. He is currently Associate Professor in the Department of Electronics and Communication Engineering at Vardhaman College of Engineering, Shamshabad,Hyderabad, Telangana, India. His research interest includes VLSI design, development of digital switch patterns, FPGA control techniques for power converters, photovoltaic power electronics converters. T.S. Anandhi was born in 1974 in Chidambaram. She has obtained B.E [Electronics and Instrumentation] and M.E [process control and Instrumentation] degrees in 1996 and 1998 respectively, and the Ph.D. in power electronics in 2008 from Annamalai University. She is currently an Associate Professor in the Department of Electronics and Instrumentation Engineering at Faculty of Engineering and Technology, Annamalai University, Chidambaram, Tamil Nadu, India and has put in 22 years of service. Her research interests are in power converters, control techniques for multiple connected power converters, embedded controllers for power converters, renewable energy based power converters.