A novel phaselet-based approach for islanding detection in inverter-based distributed generation systems

Electric Power Systems Research 182 (2020) 106226

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A novel phaselet-based approach for islanding detection in inverter-based distributed generation systems

T

Afshin Taheri Kolli, Navid Ghaffarzadeh* Department of Electrical Engineering, Imam Khomeini International University, Qazvin, Iran

A R T I C LE I N FO

A B S T R A C T

Keywords: Distributed generation (DG) Islanding detection Signal processing Negative sequence impedance (NSI) Phaselet algorithm

In this paper, a novel signal processing approach based on phaselet algorithm is proposed to detect the islanding phenomenon. Phaselets can effectively compute the phasors over data windows that are not limited to an integer multiplication of a half-cycle. Thereby, they can obtain features of the islanded and non-islanded situations without injecting any disturbance or high frequency signal into the power system, which makes the proposed method more accurate and reliable because there are no power quality reduction problems. In the proposed approach, phaselet algorithm uses the variable filtering window capability in order to phasor estimation of the negative sequence components of the voltage and current waveforms. To evaluate the performance of the proposed technique, various islanding and non-islanding events have been implemented using a grid-connected PV system modeled in a MATLAB/Simulink environment, which are based on the UL-1741 and IEEE-1547 standards. The simulation results show that our approach is able to accurately distinct islanding incident from other power quality disturbances. The ability to detect islanding occurrence in less than two cycles even in the case of perfect power match, the zero non-detection zone (NDZ) and no power quality degradation are the main advantages of the proposed method.

1. Introduction Increasing costs of natural gas and oil, environmental pollution of fossil fuels and global warming caused a great affirmation on the importance and application of distributed generation (DG) based on renewable energy sources such as solar photovoltaic, wind power, micro hydro and landfill gas [1,2]. Merger of these DGs to distribution system has considerable advantages, such as enhance reliability and energy efficiency, improving power quality and reduction of line losses [3]. However, the DGs are generating many problems and concerns in electrical power grid. One of these problems is unintentional islanding [4]. Islanding phenomenon occurs when a part of the distribution network comprising local load and DGs are disconnected from the utility system while the DGs carry on to supply the local load in the isolated portion [5]. Islanding is an unpleasant condition because it has several negative effects on utility and the DG itself, such as the safety hazards to maintenance personal, the system equipment damage, power quality issues and serious damage to the DG and loads in the state of unsynchronized restoration of the utility power because of phase difference between the utility system and DG [6,7]. Therefore, islanding condition has become a mandatory requirement for DGs, determined in the IEEE std. 929-2000, IEEE std. 1547-2003 and UL1741 standards. ⁎

Regarding to these standards, an unwanted islanding condition must be detected within 2 s from its beginning and the related DGs must be disconnected from the distribution network [8–10]. So, islanding situation must be detected quickly and effectively. Usually, islanding detection methods can be categorized into two major groups such as remote and local methods. Remote detection methods including power line carrier communication (PLCC) [11], supervisory control and data acquisition (SCADA) [12] and transfer trip [13] are based on communication between the utility grid and the DGs. These techniques have high reliability, insignificant NDZ, zero effect on power quality and quick response, but they are too expensive for implementation in small distribution network. Therefore, local techniques are broadly used for islanding detection. These techniques can be classified into passive, active and hybrid methods. Active detection methods mainly are based on injecting a distortion into distribution networks and investigating the variation in a certain output system parameters for islanding detection. In the grid connected situation, the disturbances get absorbed by the utility grid. However, in the loss of main condition, the disturbances are designed to drive the operating point of the island to a level that triggers the system protection equipment [14,15]. The main advantage of these techniques is their small NDZ and the major disadvantages of them are complication

Corresponding author. E-mail addresses: [email protected] (A. Taheri Kolli), ghaff[email protected] (N. Ghaffarzadeh).

https://doi.org/10.1016/j.epsr.2020.106226 Received 6 February 2019; Received in revised form 1 September 2019; Accepted 13 January 2020 Available online 18 January 2020 0378-7796/ © 2020 Elsevier B.V. All rights reserved.

Electric Power Systems Research 182 (2020) 106226

A. Taheri Kolli and N. Ghaffarzadeh

Fˆc − jFˆs = Fˆ

of control circuit and reduction power quality due to introducing distortions to the grid [16]. There are various active islanding detection techniques such as sandia voltage shift (SVS) and sandia frequency shift (SFS) [17], active frequency drift (AFD) [18], slip mode frequency shift (SMFS) [19], current injection [20], high-frequency signal injection [21], phase locked loop (PLL) perturbation [22], virtual inductor [23] and virtual capacitor [24]. Passive detection schemes continuously monitor the change in some certain system parameters including voltage, current, frequency and harmonic distortion in the DG side at the point of common coupling (PCC) without any distortion to the system. After loss of the main if there are large variations in the DG loading, then by measuring some of the system parameters and also by determining an accurate threshold islanding and non-islanding situations can be categorized [25,26]. Simple and low cost implementation and lack of undesirable effect on the power quality are the main advantages of these techniques [27]. Although about small variations in DG loading (small active and reactive power mismatch), the traditional techniques have some problems such as large NDZ and determining an accurate threshold value [28]. Therefore, signal processing methods are proposed to improve the performance of the conventional techniques. In fact, these methods significantly reduce the NDZ and increase the speed of islanding detection. There are various signal processing techniques such as wavelet transform (WT) [29] wavelet packet transform (WPT) [30], pattern recognition based method using Random Forest (RF) classifier to categorize the islanding and non-islanding events [31], S-transform (ST) [32], Hilbert Huang transform (HHT) [33], time-time transform (TTT) and hyperbolic S-transform (HST) [34–36]. In this paper, a novel signal processing approach based on phaselet algorithm is proposed to detect the islanding phenomenon. In fact, the main innovation of this paper is the application of the Phaselet algorithm due to its efficient and effective potential of computation compared with other conventional methods in the islanding detection of inverter-based distributed generation (DG) units. Phaselets are the partial summations of products of the data samples and the sinusoidal/cosine functions over a specified data window. Phaselets can effectively compute the phasors over data windows that are not limited to an integer multiplication of a half-cycle, as well as considerably reduce the operating time, which makes the proposed method, has a very fast speed of response. It is possible using the phaselet algorithm to obtain features of the islanded and non-islanded situations without injecting any disturbance or high frequency signal into the power system which makes it more accurate and reliable because there are no power quality reduction problems. Also the NDZ of the employed technique is zero even in the very small power mismatches condition. References [37–39] employ phaselet algorithm to current differential and high speed distance protection for transmission lines. The overall structure of this study is organized as follows: In Section 2, phasor estimation method based on phaselet is described. Section 3 presents the details of the proposed method. In Section 4, the case study power system is described. In Section 5, performance of the proposed technique for various islanding and non-islanding events is evaluated through simulation results and compared with the other available techniques. At the end, the conclusion is expressed in Section 6.

(3)

The conventional method to the computation of the Fourier uses a sliding data window. When a disturbance such as islanding, fault and etc. occurs, the data window includes two parts: pre-islanding measured values and during islanding measured values. Therefore, due to the fixed window size, there is a natural transient time delay in the phasor estimation. To address this problem, phaselet-based phasor estimation is introduced that is a variable window-length filtering approach. The meaning of a variable window is developed to progress the response of the phasor estimation, and also as a direct effect to speed up the islanding detection. Phaselets are the partial summations of products of the data samples and the sinusoidal/cosine functions over a specified data window. Phaselets can effectively compute the phasors over data windows that are not limited to an integer multiplication of a halfcycle. In this case, there is an extra correction that arises from the orthogonality of sinusoidal and cosine functions on the same window. In the other words, phaselets are combined into phasors over a set of linearly expanding window lengths, as depicted by the dotted line boxes in Fig. 1. In the normal mode of operation, the phaselets are added over one full cycle and the filtering window W (k ) is fixed to N , creating an equivalent of a one full cycle DFT, as illustrated by the solid line box in Fig. 1. As a disturbance happens, the filter window size is automatically decreased to the width of first phaselet. When new phaselets acquired, the window size gets bigger to contain the new data. The data window size continues to increase until it is equal to the full cycle. The precision of the estimated phasor improves when the data window increases. Each box in the Fig. 1 illustrates a filtering window W (k ). The phaselets are obtained as follows: P.q+q−1

FPlc (P ) =

∑ n=P.q

P.q+q−1

FPls (P ) =

∑ n=P.q

2nπ ⎞ f (n). cos ⎛ ⎝ N ⎠

(4)

2nπ ⎞ f (n). sin ⎛ ⎝ N ⎠

(5)

where FPlc (P ) and FPls (P ) respectively are the real and imaginary parts of the Pth phaselet and P is the phaselet index that changes from 0 to NPl − 1 for the first cycle data samples. Also N and NPl are number of samples per full cycle and number of phaselets per full cycle respectively. In this paper there are 20 phaselets in one full cycle and each of them consist of sets of four samples that are processed together to create

2. Phaselet-based phasor estimation method Full-cycle discrete Fourier transform (FCDFT) estimates the fundamental phasor in a full cycle of samples as follows:

2 Fˆc = ⎛ ⎞. ⎝N ⎠

2 Fˆs = ⎛ ⎞. ⎝N ⎠

N −1

2nπ ⎞ ⎝ N ⎠

(1)

2nπ ⎞ ⎝ N ⎠

(2)

∑ f (n). cos ⎛ n=0

N −1

∑ f (n). sin ⎛ n=0

Fig. 1. Variable window size filtering. 2

Electric Power Systems Research 182 (2020) 106226

A. Taheri Kolli and N. Ghaffarzadeh

obtained as follows: k

∑

Plc (k ) =

P=k−

FPlc (P )

W (k ) q +1

(6)

K

∑

Pls (k ) =

FPls (P )

W (k ) P=k− q +1

(7)

where W (k ) is the filtering window which expands in a linear proce1 dure from 20 cycle to one full cycle and k is the phasor index. Plc (k ) and Pls (k ) respectively are the real and imaginary parts of the sum of the phaselets over the determined filtering window W (k ) . The real and imaginary parts of kth phasor, Fˆc (k ) and Fˆs (k ) can be obtained from Plc (k ) and Pls (k ) [40], as follows: −1 Fˆc (k ) ⎤ ⎡T1 (k ) T2 (k ) ⎤ ⎡ Plc (k ) ⎤ Fˆ (k ) = ⎡ ⎢ Fˆ (k ) ⎥ = ⎢T2 (k ) T3 (k ) ⎥ ⎢ Pls (k ) ⎥ ⎦ ⎣ ⎦ ⎣ s ⎦ ⎣

Fig. 2. Frequency responses of phaselet algorithm.

W (k ) − 1

∑

T1 (k ) =

n=0 W (k ) − 1

∑

T2 (k ) =

n=0 W (k ) − 1

T3 (k ) =

∑ n=0

Fig. 3. Negative sequence equivalent circuit.

2nπ ⎞ cos 2 ⎛ ⎝ N ⎠

(8)

(9)

2nπ 2nπ ⎞ ⎞ sin ⎛ cos ⎛ ⎝ N ⎠ ⎝ N ⎠

(10)

2nπ ⎞ sin2 ⎛ ⎝ N ⎠

(11)

In case W (k ) equals to N , T2 (k ) will be zero using the orthogonality principle of sine and cosine functions. As a result, the obtained phasors Fˆc (k ) and Fˆs (k ) according to (8) will be equivalent to FCDFT-based phasor estimation (1, 2). Also, when W (k ) is between 0 and N except N /2 , T2 (k ) will not be zero. To speed-up the islanding detection, it is required to pre-compute coefficient matrix T −1 (k ) in (8). Eventually, the magnitude and phase angle of the signal can be computed as follows:

|Fˆ (k )| =

Fig. 4. Negative sequence equivalent circuit in normal condition.

(Fˆ c (k ))2 + (Fˆs (k ))2

Fˆ (k ) ⎞ θ Fˆ (k ) = arctan ⎛⎜ s ⎟ ˆ ⎝ Fc (k ) ⎠

Table 1 Specification of the simulation model. Value

Parameter

Value

PV array rated power output DC source voltage

100 kW

Load quality factor

2.5

500 V

1980 Hz

Line-to-Line voltage rms Nominal frequency Transformer nominal power Load resonant frequency

260 V 60 Hz 100 KVA 60 Hz

Inverter switching frequency Filter resistance Filter inductance Infinite bus short circuit Infinite bus voltage

(13)

Fig. 2 illustrates the frequency response of the filters with different window sizes based on phaselet. When the window size is very small, it has little ability to eliminate the harmonics and decaying DC component but, when the window increases, the DC response and harmonic response improve until they are finally equivalent to full cycle DFT. When the window size reaches half cycle, the filter cannot eliminate even harmonics. In this paper, a mimic filter is employed to effectively eliminate the decaying offset before the phaselet computation. Because processing of signal including decaying DC component lead to an oscillation of the phasor estimation. The mimic calculation is used to the raw samples of the waveform of each phase current. The output data of the mimic computation is the input signal for the phaselet calculation.

Fig. 5. Negative sequence equivalent circuit in islanding condition.

Parameter

(12)

3. Description of the proposed method

2 mΩ 0.2 mH 2500 MVA 120 kV

3.1. Determining of negative sequence impedance based on phaselet algorithm Negative sequence components are one of the key indexes in case of any disturbance situation. This section is presented a phaselet-based signal processing technique for islanding detection. In this technique, the negative sequence components of the voltage and current signals are extracted at the point of common coupling (PCC) between the DG and the grid. First, these signals pass through the mimic filter and enter to the phaselet-based phasor estimation process. Then,

a mini phasor or phaselet. Consequently, the number of samples per phaselet is N / NPl that is denoted here by the constant q and is adjusted to 1/20 of number of samples in one cycle, so that the variations in voltage and current values can be detected as early as possible. The sum of the phaselets over the desired window W (k ) can be 3

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A. Taheri Kolli and N. Ghaffarzadeh

Fig. 6. Grid connected PV system.

phaselet algorithm uses the variable filtering window capability in order to phasor estimation of the negative sequence components of the voltage and current waveforms. Afterward, the amplitude of these signals is calculated by (14) and (17). Finally, the magnitude of negative sequence impedance (NSI) can be computed by the magnitude of the ratio of the negative sequence voltage to the negative sequence current at PCC as (20).

|Vpcc, neg (k )| =

m2 + n2 T1. T3 − T2 T2

k ⎛ m = T3 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

As stated, the magnitude of NSI at PCC can be used for an index of islanding condition. In this part, the negative sequence equivalent circuit is employed for analyzing the alteration of the magnitude of NSI respondent to the operating situation. This technique uses the supposition that the magnitude of NSI of an islanded network is much larger than a utility connected network. Fig. 3 shows the negative sequence equivalent circuit under above observations.

(14)

P.q+q−1

∑ n=P.q

k ⎛ − T2 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

3.2. Negative sequence impedance based islanding detection

3.2.1. Grid-connected condition In a grid-connected system, because the load impedance is much greater than the grid impedance, equivalent circuit in Fig. 3 becomes one in Fig. 4. In this state, the magnitude of NSI at PCC is equal to grid impedance as (21).

⎞ 2nπ ⎞⎟ Vpcc, neg (n). cos ⎛ ⎝ N ⎠⎟ ⎠

P.q+q−1

∑ n=P.q

⎞ 2nπ ⎞⎟ Vpcc, neg (n). sin ⎛ ⎝ N ⎠⎟ ⎠

|Zpcc, neg| = (15)

Vpcc, neg Ipcc, neg

= |Zload ∥Zgrid| =

= |Zgrid| k ⎛ n = T1 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

∑ n=P.q

k ⎛ − T2 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

|Ipcc, neg (k )| =

⎞ 2nπ ⎞⎟ Vpcc, neg (n). sin ⎛ ⎝ N ⎠⎟ ⎠

P.q+q−1

P.q+q−1

∑ n=P.q

⎞ 2nπ ⎞⎟ Vpcc, neg (n). cos ⎛ ⎝ N ⎠⎟ ⎠

r 2 + s2 T1. T3 − T2 T2 P.q+q−1

∑ n=P.q

k ⎛ − T2 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

(16)

(17)

k ⎛ s = T1 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

|Zpcc, neg| =

∑ n=P.q

P.q+q−1

∑ n=P.q

k ⎛ − T2 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

⎞ 2nπ ⎞⎟ Ipcc, neg (n). cos ⎛ ⎝ N ⎠⎟ ⎠

P.q+q−1

⎞ 2nπ ⎞⎟ Ipcc, neg (n). sin ⎛ ⎝ N ⎠⎟ ⎠

∑ n=P.q

⎞ 2nπ ⎞⎟ Ipcc, neg (n). cos ⎛ ⎝ N ⎠⎟ ⎠

|Zpcc, neg| (21)

(22)

In this section, in order to evaluate the efficiency of the proposed method, a photovoltaic system as a DG unit connected to the grid is implemented in the MATLAB/Simulink software environment. System characteristics are exhibited in Table 1. SunPower (SPR-305E-WHT-D) modules are used to simulated PV array. The technical specifications of these modules are: Short circuit current (Isc = 5.96A ), Open circuit voltage (Voc = 64.2V ) and also current and voltage at maximum power (Vmp = 54.7V, Imp = 5.58A ). In this system, in order to produce a nominal power of 100kW in standard working conditions (25°C ambient temperature and 1000W/m2 irradiance) the PV array includes 66 parallel strings, each containing 5 series modules. The PV array is connected to a step-up transformer (260V / 25KV ) via a DC-DC boost converter and a three-phase threelevel Voltage Source Converter (VSC). DC-DC boost converter increases voltage from PV natural voltage (273V DC at maximum power) to 500V DC. Switching duty cycle is optimized by a Maximum Power Point Tracking (MPPT) controller. This MPPT system automatically varies the duty cycle in order to generate the required voltage to extract maximum power. The MPPT controller is implemented in the boost converter using the “Perturb and Observe” technique. The converter is connected to a VSC to convert 500V DC link voltage into 260V AC. The

(18)

(19)

Vpcc, neg Ipcc, neg

→

4. System description

⎞ 2nπ ⎞⎟ Ipcc, neg (n). sin ⎛ ⎝ N ⎠⎟ ⎠

P.q+q−1

Zload ≫ Zgrid

3.2.2. Islanding condition In islanded mode of operation, the grid is disconnected and grid impedance cannot be observed at PCC. Equivalent circuit in Fig. 3 can be simplified as Fig. 5. In this case the magnitude of NSI is equal to load impedance as (22). As stated above, because the load impedance is greater than grid impedance in islanding condition, the magnitude of NSI is large enough to differentiate the islanding condition from normal condition. The change of the magnitude of NSI from (21) to (22) can be used as the indicator of the islanding mode of operation.

|Zpcc, neg| = |Zload| k ⎛ r = T3 ⎜ ∑ ⎜ P = k − W (k ) + 1 q ⎝

Zload. Zgrid Zload + Zgrid

(20)

where Zpcc, neg , Vpcc, neg and Ipcc, neg refer respectively to negative sequence impedance, negative sequence voltage and negative sequence current at PCC. Usually, the NSI is one of the main parameter for detecting imbalanced statuses in the power system. Thus the islanding condition can be detected by investigation of the magnitude of NSI at PCC. 4

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Table 2 Local load R, L, C parameters for various Qf values. Detection time (Sec)

Active power, kW

Quality factor

R, Ω

L, mH

C, mF

0.0138 0.0166 0.019 0.0135 0.0201

100 100 100 100 100

0.5 1 1.5 2 2.5

0.676 0.676 0.676 0.676 0.676

3.586 1.793 1.195 0.896 0.717

1.961 3.923 5.885 7.847 9.809

A low pass RL filter is considered to eliminate the harmonics generated by the VSC. A parallel RLC load with constant impedance is considered as a local load that is connected to the grid at the PCC. In order to simulate islanding phenomenon, a three-phase circuit breaker on the utility grid side is placed in the open state. The main utility consists of an 120KV infinite bus that feeds a 25KV distribution feeder and two large loads ([30 MW + 2MVar ] and [2MW ]) via the step-down transformer (120KV / 25KV ). Fig. 6 presents a single-line diagram of a grid connected DG unit containing of a PV array, DC-AC converter, RL filter, PCC, parallel RLC load and the utility grid. 5. Simulation results In order to evaluate the performance of the proposed technique, various islanding and non-islanding operating conditions are implemented in a MATLAB/Simulink software environment, which are based on the UL-1741 and IEEE-1547 standards. The most commonly events, including islanding operation, induction motor starting, capacitor bank switching, load switching and short circuit faults are simulated to illustrate the accuracy and efficiency of the proposed method. All events occur individually at t = 0.4 s . According to the simulation results, an accurate threshold value (threshold= 0.7 ) is experimentally determined in order to identify islanding condition from non-islanding events. When the magnitude of the phasor of NSI exceeds from the preset threshold value, islanding condition is detected in a very short time. The process of implementing the phaselet-based method is depicted in the flowchart of Fig. 7. 5.1. Various islanding condition 5.1.1. Various load quality factor In order to evaluate the performance of islanding detection methods, there are various standards and test conditions including different load quality factor. For example, in UL-1741 and IEEE-1547 test conditions offer the use of Qf < 1.8 and Qf = 1 respectively; however, in IEEE Std-929, the use of Qf ≤ 2.5 is suggested [8–10]. The load quality factor is defined as the ratio of the reactive power consumption of the load to the rated real power output of the DG unit. Any change in the load quality factor affects the voltage, frequency and power parameters, which leads to undesirable performance of conventional methods. In fact, for high values of quality factor, many existing techniques are unable to detect islanding. In this part, in order to proving that the proposed passive method is effective under all test requirements determined by different standards, the system under study is simulated for a large range of Qf variations, change from 0.5 to 2.5. The local load R, L, C parameters for various Qf values, is exhibited in Table 2. For all scenarios mentioned in Table 2, islanding phenomenon is simulated by opening the circuit breaker at t = 0.4 s . The quality factor for parallel RLC load is defined as (23).

Fig. 7. The general scheme of phaselet-based islanding detection technique.

VSC control system includes two control loops: an internal control loop which adjusts Id and Iq grid currents that are active and reactive current components respectively and an external control loop which adjusts DC link voltage. The output of the DC voltage external controller determines reference setting for active current component. In order to keep unity power factor, the reactive current component is set to zero.

Qf = R

C R = 2πf0 RC = L 2πf0 L 1

(23)

where f0 = 2π LC is the resonance frequency of the parallel RLC load. As shown in Fig. 8, the various quality factors do not have any effect on the performance of the proposed method and immediately after 5

Electric Power Systems Research 182 (2020) 106226

A. Taheri Kolli and N. Ghaffarzadeh

Fig. 8. Performance of the proposed technique in terms of NSI during islanding with various value of load quality factor.

where ΔP and ΔQ are the active and reactive power taken from the utility grid respectively. Also Pload and Qload respectively denote the active and reactive power consumed by the local load, and Pinv and Qinv are the active and reactive power generated by the DG unit respectively. As stated before, DG unit operates at unity power factor with the rated real power of 100 kW. Regarding to the UL-1741Std, the load active power is set at 25%, 50%, 100%, and 125% of the rated output active power of the inverter. The load reactive power is also set from −5% to +5% of the rated active power with 1% steps. The worst case of islanding occurrence is in situations that the power imbalance is negligible, especially for the perfect balance between the power generated by inverter and the power consumed by local load (ΔP = 0 , ΔQ = 0 ). In this case, variations of the system parameters are very small that causes most of available islanding detection methods not to be able to detect islanding phenomena. Therefore, according to UL1741Std, five typical worst case scenarios are considered to demonstrate the effectiveness of our proposed technique. As mentioned in the previous section, for all cases stated in Table 3, islanding phenomenon occur at t = 0.4 s . The simulation results are depicted in Fig. 9. As show in this figure, it is clear that the proposed technique can rapidly detect islanding conditions at various values of power imbalances and immediately after the magnitude of the NSI exceeds from the threshold value, a trip signal is activated to shut down the DG unit. Moreover, this figure demonstrates the main advantage of our approach compared with other methods that is ability to detect islanding occurrence in less than two cycles even in the case of perfect power match. Therefore, the NDZ of our proposed approach is zero. The exact islanding detection times after its occurrence are given in Table 3.

Table 3 Local load R, L, C parameters for UL-1741 standard. Detection time (Sec)

Q load %

P load %

R, Ω

L, mH

C, mF

0.0116 0.0201 0.0201 0.194 0.0202

100 100 100 101 99

125 100 50 100 100

0.540 0.676 1.352 0.676 0.676

0.717 0.717 0.717 0.714 0.720

9.809 9.809 9.809 9.809 9.809

islanding, the magnitude of the NSI exceeds from the threshold value and a trip signal is activated to shut down the DG unit. As illustrated in Fig. 8, islanding phenomenon is detected in less than two cycles, which is considerably less than the detection time determined by the standards. The exact islanding detection times after its occurrence for various Qf values are given in Table 2. Due to the detection times, it can be concluded that the proposed method has a very fast speed of response. 5.1.2. Islanding detection according to UL-1741 standard In this section, according to UL-1741 standard, the operation of the presented method is evaluated with various real and reactive power imbalances as illustrated in Table 3 [10]. Regarding to the Fig. 3, the power imbalance can be defined as follows:

ΔP (%) =

Pload − Pinv × 100 Pinv

(24)

ΔQ (%) =

Qload − Qinv × 100 Pinv

(25) 6

Electric Power Systems Research 182 (2020) 106226

A. Taheri Kolli and N. Ghaffarzadeh

Fig. 9. Performance of the proposed technique in terms of NSI during islanding with various value of power mismatches.

Fig. 10. Response of the proposed technique in terms of NSI during starting of induction motor.

Fig. 11. Response of the proposed technique in terms of NSI during switching of capacitor.

Due to the detection times, it can be concluded that the proposed method has a very fast speed of response.

causes significant changes in voltage and current. These abrupt variations may cause effects similar to islanding condition, which may result in nuisance tripping in the conventional methods. In order to evaluate the performance of the proposed technique for the induction motor starting, the various induction motors are selected in the range of 5 HP to 500 HP. As shown in Fig. 10, the results illustrate that the proposed method identifies the induction motor starting events from the islanding condition.

5.2. Different non-islanding events 5.2.1. Induction motor starting scenario Most of the loads in the distribution network have an inductive nature. Induction motors are the most commonly used motors in the industries which have many applications. In instant of induction motor startup, a high amount of reactive power is taken from the grid which 7

Electric Power Systems Research 182 (2020) 106226

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performance of the proposed technique, all types of short circuit faults such as single phase to ground (L-G), phase to phase (L-L), phase to phase to ground (L-L-G),three phase (L-L-L) and three phase to ground (L-L-L-G) with fault resistance between 0.01 Ω to 100 Ω have been considered. All short circuit faults start at t = 0.4s and are cleared after 0.2s without any circuit breaker operation. The simulation results shown in Figs. 13a and b, illustrate that the proposed method accurately detects all short circuit faults with the minimum (Rf = 0.01 Ω ) and maximum (Rf = 100 Ω ) value of fault resistance as non-islanding events. 5.3. Comparison of the proposed method with the other available techniques In this section, the proposed approach is compared with other existing islanding detection schemes. Almost all conventional passive techniques are unable to detect islanding condition in the case of perfect power match and have large non-detection zone (NDZ). The proposed signal processing approach improves the performance of traditional techniques and significantly reduces the NDZ to zero and increase the speed of islanding detection. On the other hand, all active techniques reduce the power quality due to injecting distortions to the grid. It is possible using the phaselet algorithm to detect islanding situations without injecting any disturbance or high frequency signal into the power system which makes it more accurate and reliable because there are no power quality reduction problems. A comparison of the performance of the proposed method with other islanding detection techniques in terms of NDZ, detection time, and impact on power quality is exhibited in Table 4.

Fig. 12. Response of the proposed technique in terms of NSI during switching of various loads.

5.2.2. Capacitor bank switching scenario Capacitor banks, which are installed in parallel to the utility grid, are generally applied for voltage sag compensation, power factor correction and etc. In the moment of capacitor switching, the electrical parameters of the system vary, which may lead to nuisance tripping of the traditional islanding detection methods. In this section, the proposed technique is assessed for capacitor switching as a non-islanding case. For this aim, a wide range of capacitor banks with different capacities in the range of 0.01 MVar to 70 MVar has been considered. The simulation results of the capacitor bank switching have been shown in Fig. 11, which verify the appropriate performance of the proposed technique.

6. Conclusion 5.2.3. Load switching scenario Load switching events are one of perturbations, which some of the islanding detection schemes commonly operate false. In this section, the performance of the proposed technique is assessed under various load switching events in the grid connected condition. These loads are considered in the wide range of 0.4 MVA to 40 MVA. As shown in Fig.12, such load switching occurrences do not have any signatures on the proposed method. In other word, the proposed approach is able to identify between load switching events and islanding conditions and does not send any nuisance trip.

This study proposes a novel approach of islanding detection for inverter-based distributed generation (DG) units based on phaselet algorithm. In this technique, first, the negative sequence components of the voltage and current signals are extracted at the point of common coupling (PCC) between the DG and the grid. Then, a powerful time-frequency analysis method called phaselet processing approach is employed to estimate phasors in a recursive manner over variable-length windows of voltage and current signals. The phasors obtained on these signals are used to compute the negative sequence impedance (NSI) as an index for islanding detection. Finally, islanding condition can be detected by investigation of the magnitude of NSI at PCC so that, when the magnitude of the phasor of NSI exceeds from the preset threshold value, islanding condition is identified. The most commonly events, including islanding operation, induction motor starting, capacitor bank switching, load switching and short circuit faults are simulated to illustrate the accuracy and efficiency of the proposed method. The simulation results verify that our approach is able to effectively detect islanding condition in less than two cycles even for the worst case scenario of perfect power balance and avoid sending nuisance trip signal for non-islanding events.

5.2.4. Short circuit fault scenario One of the most common events which may happen in utility grid and cause the false performance in the islanding detection methods are short circuit faults. These events cause voltage and frequency deviation from their nominal values. In the case of small fault resistance, fault current increases that causes the voltage and frequency deviate from the pre-set threshold of voltage and frequency relays. However, in the case of large fault resistance, voltage and frequency do not go beyond relays’ boundaries. Islanding detection methods may confuse these conditions with the islanding situation, and trip wrongly. To assess the

Fig. 13. Response of the proposed technique in terms of NSI during various types of fault with (a) Rf = 0.01 Ω and (b) Rf = 100 Ω . 8

Electric Power Systems Research 182 (2020) 106226

A. Taheri Kolli and N. Ghaffarzadeh

Table 4 Comparison of islanding detection techniques. Islanding detection technique

NDZ

Detection time (Sec)

Power quality degradation

Proposed method Over under voltage/ over under frequency OUV/OUF [41] Voltage and current harmonic detection [41]

Zero Large Large with a large value of Qf

0.02 0.4 to 2 0.2 to 0.3

NO NO NO

Rate of change of power (ROCOP) [41] Phase Jump Detection (PJD) [41] Voltage Unbalance (VU) [41] Active ROCOF relay for islanding detection [42] Two level islanding detection method [18]

Smaller than OUV/OUF Large Large Zero Almost zero

0.4 0.1 to 0.2 0.1 0.2 0.32

NO NO NO Yes Yes

Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

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