A proposal for μP prototyping systems

Euromicro, North-Holland

1976 Publishing Co., Amsterdam

A PROPOSAL FOR PROTOTYPING

~P

SYSTEMS

G.Conte - D. Del Corso - M.Giordana Istituto di Elettronica e Telecomunicazioni Politecnico Torino - Italy

In this paper we describe the hardware

tors for external devices

standards that we use in our laboratory

The motherboard

for the realization of developmental

similar to

~P systems. Our interest

in

8 bit

~P concerns

The complete

(See Fig.l).

can be structured

in a way

[I] Fig.4. structure

is shown in Fig. 2.

m ~ n l y data acquisition and instrumentation

One 5" high rack unit can accomodate up to

control;

6 cards, plus the power supply and the hard

for this reason we have selected

control signals and hardware

supports in

ware consolle.

Order to obtain an easy interfacing towards any peripheral device. This paper is intended as a contribution to define hard ware standards for

~P.

PHISICAL HARDWARE We use 12 x 20 cm cards with 2 x 22 con tacts connector.

Since we are interested

only in prototyping, we use wire-wrap make on-the-board

connections.

to

The printed

FUNCTIONAL HARDWARE:

THE BUS

The bus lines are divided into 4 sections: a) -

Gontrols

b) -

Power supply

c) -

Data and addresses

a) Controls: when we started in u s i n g ~ P

we

defined some particular control lines; recently we modified them only to get full compatibility with the standard propose~ by

circuit on the card is limited to connec-

prof.Nicoud

tors and supply lines. This allows high

small changes on the memory and I/O cards.

packaging

Table I specifies the assignements

Namely,

density, when required.

each card can accomodate up to 42

~2]

[3] •

This required only

on the

bus. Table II shows the correspondence

x 16 pin packages plus up to 3 x 40 pin

ween the labels of each line.

packages.

nics are shorther than prof.Nicoud's!).

Some frequently used circuits

(clock generators;

TTY level converter

etc), are implemented as independent ted circuits modules,

pri M

and wrapped on the

bet

(Our mnemo-

We reserved four lines for interrupt han d ling INR, INA plus INO (interrupt enable out) and INI (interrupt enable in), the

card. Each card has its own 5 volt regu-

last two for chained interrupt

lator,

INO line of card I goes to INI of card 2

placed on an

sluminium bracket.

capability.

This bracket works both as extractor and

and so on (fig.2). The priority level of a

heathsink and can also accomodate

peripheral device depends upon the phisical

connec-

8

G. CONTE - D. DEL CORSO - M. GIORDANA

position on the bus of the card. This al-

Microprocessors and Peripherals-Eurom~

lows unlimited hardware prioritizing of in_

cro Newsletter-April 1975-Vol.l-n.3

terrupts and has been proved to be a quite

~3]

J.D.Nicoud - Hardware Choises for Mi-

versatile method of handling interrupts.

croprocessors-Euromicro Workshop on

The C P U o a r d

Microarchitecture of Computer Systems

is placed in the last right

position on the bus. This allows an easy connection to the hardware consolle. Fig.3

Nice-June 1975

[4]

G.Conte-D.Del Corso-M.Giordana-Sistema

s h o w s h o w e o m e lines are used by the addi-

per la gestione di strumentazione ed

tional signals reguired for CPU/consolle

acquisizione dati realizzato con un mi

interfacing

croprocessore INTEL8080 - Elettronica

[4].

These signals are used

for peculiar operations (e.g. single step). b) The power supply lines are defined as follows: *) + 15 V and - 15 V regulated. These supplies can be directly used for analog interface circuits. The bias voltagesrequired for MOS circuits (+ 12 V, - 12 V and -5 V) are obtained from these lines by on-card regulators. *) + 8 V unregulated. Each card has its own regulator to get the + 5 V logic supply. The on-card regulators simplify the problem of supply decoupling and reduce the amount of heath produced at the main power supply. c) Bidirectional data bus is controlled by tBi'ee state buffers on each card. A card represents a I TTL unit load on the bus or less, and has a fan out of 20 TTL units. The address lines can be driven by CPU or by DMA devices. REFERENCES [I]

J.P.Vuille - Standards for

~P

Systems (II) - Euromicro News Letter, 0ct.1975, Vol. I, n.5 [2]

J.D.Nicoud - Hardware Standards for

3-3 ° Convegno Internazionale di Elettronica Industriale~-Torino 0ct.1975

A PROPOSAL FOR ~P PROTOTYPING SYSTEMS

TABLE I: Bus connector Pinning

I

2 3 4 5 6 7 8 9 I0 11 12 13 14 15 16 17 18 ~9 2O 21 22

Side A

Side B

+8V +15V GND - 15 V INO INA VPA* RST* WR * VMA* INR* RDY HLDR* HLDA ADO7 ADO6 ADO5 ADO4 ADO3 ADO2 ADO1 ADO0

+8V + 15V GND -15V INI SCK DAO DAI DA2 DA3 DA4 DA5 DA6 DA7 ADI 5 AD14 ADI 3 ADI 2 ADI I ADI 0 ADO9 ADO8

Supply lines

Controls (A) Data (D)

Address lines

(active low)

* means inverted signal

TABLE II: Bus labels INI

interrupt enable in

INO

interrupt enable out

INA

interrupt acknowledge

INTACK

INR*

interrupt request

INT RE QLOW

VPA*

valid peripheral address

ADPERLOW

VMA*

valid memory address

ADMEN[LOW

WR*

write/read

WRITELOW

RDY

ready

NOTYETLOW

RST*

restart

RESETLOW

HLDR*

hold request

HOLDREQLOW

HLDA

hold acknowledge

HOLDACK

SCK

system clock

* means inverted signal ** See

[2]

(active low)

9

i0

G.

CONTE

-

D.

DEL

CORSO

- M.

GIORDANA

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*'f5V GN~

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FIG

2

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