- Email: [email protected]
A protocol converter for nonblocking protocols
INTEGRATION, the VLSI journal 33 (2002) 71–88
A protocol converter for nonblocking protocols Young Moo Leea,*, Kyu Ho Parkb b
a Telecommunications Network Laboratory, KT 463-1, Jeonmindong, Yusungku, Taejon 305-811, South Korea Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, 373-1, Kusungdong, Yusungku, Taejon 305-701, South Korea
Abstract A protocol converter must interface two communicating components if their protocols are incompatible. This paper presents a method to implement a protocol converter for nonblocking protocols since previous protocol converters insisted that both their input protocols be blocking protocols with a unlimited blocking period although many protocols in use are nonblocking protocols or blocking protocols whose blocking period is limited. Since a protocol converter for nonblocking protocols of a read operation may not exist, the existence must be determined by examining whether two input protocols satisfy several temporal constraints. If it can exist, the duals of the input protocols must be implemented to execute the input protocols because a protocol and its dual match for communication. We present algorithms that schedule the execution of the duals of the two input protocols. A circuit for a control signal must also be implemented to trigger the execution of the dual of the slave protocol when the master protocol is executed. If necessary, message buffers must be implemented to resolve the timing mismatch of the message transfer periods of the two scheduled input protocols. The experimental results show that our protocol converter supports nonblocking protocols. The same method can be applied to blocking protocols with a limited blocking period. The result in this paper widens the application of protocol converters. r 2002 Published by Elsevier Science B.V. Keywords: CMOS digital integrated circuit; Protocol converter; Nonblocking protocol
1. Introduction In hardware system design, some parts may be implemented with components that have a fixed communication protocol. If communicating components have incompatible protocols, a protocol converter [1–10] must be interposed. In Fig. 1, the protocol converter is interposed because the external communication protocols of the ISA bus master [11] (iMasterWrite, iMasterRead, *Corresponding author. E-mail addresses: [email protected] (Y.M. Lee), [email protected] (K.H. Park). 0167-9260/02/$ - see front matter r 2002 Published by Elsevier Science B.V. PII: S 0 1 6 7 - 9 2 6 0 ( 0 2 ) 0 0 0 4 9 - 4
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Y.M. Lee, K.H. Park / INTEGRATION, the VLSI journal 33 (2002) 71–88 SCSI I/O Processor
ISA bus iMasterWrite
pSlaveWrite
Protocol Converter
pSlaveRead
…
…
iMasterRead
bale a[31:2] d[31:0]
bale smemw# D(iMasterWrite) bale smemr#
D(pSlaveWrite)
ads# D(pSlaveRead) w_r# readyi#
D(iMasterRead)
…
smemw#
ads# w_r# readyi#
smemr# sa[ ] sd[ ]
Message buffer buf_a[ ] buf_d[ ]
SCSI bus
ads# a[31:2] d[31:0]
w_r# readyi#
a[ ] d[ ]
Fig. 1. A protocol converter.
Fig. 2. (a) A nonblocking protocol and (b) a blocking protocol.
etc.) are incompatible with those of the SCSI I/O processor [12] (pSlaveWrite, pSlaveRead, etc.). The four protocols shown in Fig. 1 (iMasterWrite, iMasterRead, pSlaveWrite, pSlaveRead) are nonblocking protocols. A communication protocol is a nonblocking protocol if its message transfer is executed in sequence and finishes in a fixed period without the acknowledgment of the other communication party as illustrated in Fig. 2(a). A blocking protocol is different in that its
Y.M. Lee, K.H. Park / INTEGRATION, the VLSI journal 33 (2002) 71–88
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message transfer is conditionally executed if the other communication party acknowledges the transfer as illustrated in Fig. 2(b). Many communication protocols in use are nonblocking protocols: ISA bus master protocols [11], the slave protocols of the SCSI I/O processor [12], the protocols of many memory chips such as an SRAM [14] and video processors such as an MPEG-2 Encoder [15], etc. To support protocol conversion in many applications, nonblocking protocols must also be supported by a protocol converter. Supporting nonblocking protocols is important because they have an advantage in that they can be statically scheduled. A statically scheduled communication is faster than the equivalent communication dynamically scheduled. Another advantage is that the time for the communication is predictable. Thus, it is prefered in real-time applications where a certain performance must be guaranteed even in a worst case. In many blocking protocols, the blocking period is limited. For example, in the PCI bus [13], either a master device or a slave device cannot block a data transfer more than eight clock cycles. This kind of limitation is often introduced to prevent deadlock, livelock, starvation and to guarantee a fairness in a bus. However, because of the limited blocking period, such a blocking protocol cannot be supported in a protocol converter that assumes that the protocol’s blocking period is unlimited. Although there have been many studies on protocol converters, one of their common limitations is that they assume that input protocols must be blocking protocols. Their protocol converters do not support even blocking protocols with a limited blocking period. Okumura [1] used a communicating finite state machine (CFSM) model (similar to that of Lam’s [2]) and proposed an algorithm to construct a converter between two CFSMs that use blocking transfers. Akella and McMillan [3] proposed a similar protocol conversion technique between a pair of finite state machines that communicate in a blocking mode. Narayan and Gajski [4] transformed the protocol description in a hardware description language into combinations of five atomic operations: data signal in, data signal out, control signal in, control signal out, and time delay. The combinations were grouped into blocks whose execution was guarded by a condition on one of the control signals or by a time delay. The blocks of two protocols were matched to transfer the same amount of data by blocking the transfer. Madsen and Hald [5] proposed a converter between a pair of components that communicate by blocking messages for a data-only write operation. Kumar et al. [6] provided a protocol converter between a pair of discrete event systems communicating by blocking messages. Passerone et al. [7] built a protocol converter between two components, described in a derivative of regular expression, that communicate by blocking messages for a data-only write operation. Smith and De Michelli [8] assumed that every communicating component has the same buffer that uses the same predefined, simple communication protocol. The buffers have the same protocol so that they can communicate with each other. Then they presented a technique that maps the communication protocol of the component described in a hardware description language to the communication protocol of the buffer. The components exchange messages in a blocking mode through their buffers. In this paper, we present a protocol converter that supports nonblocking protocols. A protocol converter for nonblocking protocols must be different from a protocol converter for blocking protocols because nonblocking protocols and blocking protocols have different constraints for protocol conversion.
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The rest of this paper is organized as follows. Section 2 explains how a protocol converter for complex protocols can be modularly constructed as a set of smaller protocol converters for atomic protocols. In Section 3, we define the temporal model of a protocol and formulate the problem of constructing a protocol converter for nonblocking atomic protocols. Section 4 presents our method to implement a protocol converter for nonblocking protocols. Experimental results of the proposed method with input protocols in a real system are given in Section 5. The last section gives the conclusion.
2. Background From our experience in designing a protocol converter [9,10], we have found that an arbitrarily complex protocol of a communicating VLSI component can be hierarchically decomposed into a set of simpler protocols and a protocol converter for such complex protocols can be constructed modularly as a set of protocol converters for those simpler protocols. For example, Fig. 3(a) shows the protocol hierarchy of the processor [12] in Fig. 1. The lowest protocols in the hierarchy are atomic protocols which are numbered from (1) to (7). Fig. 3(b) shows the state graph representation of the processor’s protocol. An atomic protocol is a protocol whose signal in/out operations with regard to the other communication party form an independent, indivisible ordered set so that all the operations in the set are performed in one sequence if the protocol is executed. An operation that is not in the set cannot intervene in between the operations in the set during the protocol execution. The operations in the set are not performed at all if the protocol is not executed. Thus, the state graph
Idle pProcessor Req
Tt
Asi
Ack
Aso
Cs
pArbiter(1) pMaster pMasterWrite(2)
(1 ) Mdo
pMasterWriteBurst(3)
Mdi
Sdo
Sdi
Sro
Sri
(6)
(7)
pMasterRead(4) Mro
pMasterReadBurst(5)
Mri
pSlave pSlaveWrite(6) pSlaveRead(7)
(a) protocol hierarchy
Tbo
Mor
Tbi
Mir
(4)
(2) Cbo
Cbi
(3)
(5)
(b) state graph
Fig. 3. A hierarchical protocol.
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Idle Idle
Req
Ack
Idle
clk
Req hold#
hldai#
Ack (a) timing diagram
(b) state graph
Fig. 4. An atomic protocol, pArbiter.
of an atomic protocol is a cycle since an atomic protocol begins its execution at the initial state, performs signal operations in one sequence of states and returns to the initial state. For example, Fig. 4 shows the timing diagram and the state graph of the atomic protocol, pArbiter. Each signal followed by # is active low. The state graph is a cycle. Its origin and terminus are in the same state, ‘Idle’. The hold# output signal is asserted in the ‘Req’ state and the hldai# input signal is also asserted in the ‘Ack’ state. Both signals are deasserted in the ‘Idle’ state. All the signal operations are performed in one sequence. The seven leaf-states labeled (1)–(7) in Fig. 3(b) represent distinct state graphs of the seven atomic protocols. The left dashed-polygon indicates the state graph of the pArbiter protocol which is also in Fig. 4 for the illustration of an atomic protocol. The right dashed-polygon also indicates one of the atomic protocols, pMasterWriteBurst labeled (3). Although the pMasterWriteBurst protocol shares many states with the pMasterWrite protocol, they are distinct atomic protocols. The state graph of all the atomic protocols is a cycle. For simplicity, the return transition from the leaf-state to the initial state is not shown in Fig. 3(b). A higher protocol contains several sub-protocols as the processor’s protocol contains seven atomic protocols. The state graph of a higher protocol contains the state graphs of its subprotocols. If the sub-protocols have a common state, the common state is shared by the state graphs of the sub-protocols in the state graph of the higher protocol. In Fig. 3(b), pArbiter and pMasterWriteBurst protocols share only the initial state labeled ‘Idle’ while pMasterWrite and pMasterWriteBurst protocols share many states. In Fig. 3, the pMaster protocol is a sub-protocol of the processor’s protocol and it is also a higher protocol that contains four atomic protocols: pMasterWrite, pMasterWriteBurst, pMasterRead and pMasterReadBurst. The four branches containing four leaf-states numbered (2)–(5) in Fig. 3(b) represent the state graph of the pMaster protocol. Another feature of an atomic protocol is that its states have only one outgoing transition except for a self-looping transition. In other words, it supports only a one-way choice for possible
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branching to the next state except the current state itself. This feature of an atomic protocol reduces the exploration space and complexity for scheduling communications in our protocol converter which is modularly constructed as a set of protocol converters for atomic protocols as presented in our previous work [10]. 3. Problem formulation Our converter is assumed to be inserted among processors, controllers, memories and application-specific integrated circuits (ASIC) that communicate in a memory-mapped way. The communications between those components can be characterized by two message transfers: an address transfer and a data transfer. Around each message transfer, there may be exchanges of control signals that guide the message transfer. Let a phase be a set of bus cycles that have some common characteristics in a communication. Then, we can model a communication as five phases: the first control phase, an address transfer phase, the second control phase, a data transfer phase and the third control phase. The five-phase model emphasizes the address and data transfers and relatively ignores control phases because synchronizing message transfers is the essential task in the protocol conversion. The temporal model of a protocol can be modeled as a five-tuple and each tuple represents the number of clock cycles for each of the five phases, respectively. Definition 1 (Temporal model of a protocol). The temporal model of a protocol of a communicating VLSI component, C; is a 5-tuple: ð1Þ C ¼ ðc1 ; c2 ; c3 ; c4 ; c5 Þ; where c1 is the number of clock cycles for a control phase before an address transfer phase, c2 the number of clock cycles for an address transfer phase, c3 the number of clock cycles for a control phase between the address transfer phase and a data transfer phase, c4 the number of clock cycles for a data transfer phase, and c5 is the number of clock cycles for the last control phase after the data transfer phase. Example 1. The temporal model of the iMasterRead protocol, CiMasterRead in Fig. 1 of the ISA bus [11] is ð2Þ CiMasterRead ¼ ð0; 1; 4; 1; 0Þ: As shown in the timing diagram of the protocol in the upper division of Fig. 5, the address transfer phase begins without a preceding control phase. Thus, c1 is 0. After an address message is produced from the ISA bus port named sa, four bus cycles are necessary until a data message is returned to the port named sd. Thus, c3 is 4. c5 is also 0 as is c1 because the data transfer phase ends without any following control phase after the transfer. Example 2. The temporal model of the pSlaveRead protocol, CpSlaveRead in Fig. 1, of the processor [12] is ð3Þ CpSlaveRead ¼ ð0; 1; 2; 3; 0Þ:
Y.M. Lee, K.H. Park / INTEGRATION, the VLSI journal 33 (2002) 71–88 t1
t2
t3
t4
t5
t6
77
t7
iMasterRead
clk sa sd bale smemr#
pSlaveRead
a d ads# cs# w_r# readyi# time
Fig. 5. Experimental result of protocol conversion between the pair of protocol, (iMasterRead, pSlaveRead).
As shown in the timing diagram of the protocol in the lower division of Fig. 5, the address transfer phase begins without a preceding control phase. Thus, c1 is 0. After an address message is produced from the processor’s port named a, two bus cycles are necessary until a data transfer begins. The data message is valid for three bus cycles which results in c4 being 3. c5 is 0 because the data transfer ends without a following control phase. For a nonblocking protocol, every phase in the temporal model has a fixed period. In Examples 1 and 2, every phase has a fixed period because both the iMasterRead protocol and the pSlaveRead protocol are nonblocking protocols. A blocking protocol always has a variable in its temporal model because the blocking period must be modeled as a variable. For example, if a protocol has a blocking data transfer, the corresponding tuple, c4 ; in the temporal model of the protocol is not a constant but a variable. In general, a tuple in our temporal model of a protocol has the form u þ v; where u is a nonnegative integer constant that represents a fixed period and v is a nonnegative integer variable that represents a variable period. Because a nonblocking protocol does not have any blocking phase, every tuple is a fixed period and v is always zero. There is a blocking phase in a blocking protocol. Thus, v of the corresponding tuple in the temporal model of the protocol must be greater than zero while u of the tuple must be zero. If the blocking period of the phase is not limited, v is also unlimited. If the blocking period of the phase is limited, the limitation must be reflected on the range of the variable v: For instance, for the protocols of the PCI bus [13], the maximum range of the variable v for the data transfer phase is eight because the blocking period of the phase is limited to up to eight bus cycles as described in Section 1. We have discussed our temporal model of a protocol. Now, we formulate the problem of protocol conversion on the basis of the above discussion. Section 2 showed that a protocol converter between two arbitrarily complex protocols can be modularly constructed as a set of protocol converters between pairs of atomic protocols. The
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modular architecture of such a protocol converter has been introduced in our previous study [10]. In [10], each module in the converter is the dual protocol implementation of an atomic protocol of a communicating component. If we can construct a protocol converter between a pair of nonblocking atomic protocols, we can construct a protocol converter for arbitrarily complex nonblocking protocols with a modular architecture as proposed in [10] and explained in Section 2. When two atomic protocols of a master and a slave component are given, we can obtain the temporal model of those protocols. Let the temporal model of a master protocol be M where M is (m1 ; m2 ; m3 ; m4 ; m5 ) and let the temporal model of a slave protocol be S where S is (s1 ; s2 ; s3 ; s4 ; s5 ). According to Definition 1, mj and sk (for j; kAf1; 2; 3; 4; 5g) in M and S; represent the tuple for the ith phase of master and slave protocols, respectively. Let ti (i is a natural number) be the ith time slot for scheduling two protocols in a protocol converter. The problem in this paper is implementing a protocol converter that maps mj and sk (j; kAf1; 2; 3; 4; 5g) to fti ji is a natural numberg to make the protocol converter guarantee correct message transfers between the two input protocols. Definition 2 (Problem). Implement a protocol converter that realizes a function F : fmj j j ¼ 1; 2; 3; 4; 5g,fsk j k ¼ 1; 2; 3; 4; 5g-fti j i is a natural numbergn such that messages between a master protocol and a slave protocol are correctly transferred.
4. Protocol converter The basic architecture of a converter is the implementation of dual protocols of its input protocols [3,4,7,8] because a protocol and its dual protocol match for the communication. A product machine of two finite state machines was proposed to operate as a converter in [3,7] where the two finite state machines represented the duals of two communicating protocols. The dual of a protocol is a protocol that is equivalent to the original protocol except that all its signals have the opposite direction in relation to the corresponding signals of the original protocol when a signal has only two directions in its definition, either an input or an output. In the architecture based on the implementation of the dual protocols of input protocols, only messages are exchanged between the two duals within the converter. Other control signals of the input protocols are exchanged locally at the boundary of the converter between a given input protocol of a component outside the converter and its dual protocol implemented within the converter. For example, a master protocol and its dual implemented in a protocol converter exchange control signals locally at the boundary of the protocol converter. The signals must not be seen by a slave protocol and the dual of the slave protocol. Similarly, a slave protocol and its dual exchange their control signals locally at the boundary of the protocol converter and the signals are not seen by the master protocol and the dual of the master protocol. The implementation of the dual protocols ensure that the input protocols can be executed without stop. However, the dual protocols do not ensure correct message transfers between input protocols. Because the dual of a protocol is already explained in previous studies [1–8] including ours [9,10], this section explains in detail how to ensure correct message transfers in our protocol converter for nonblocking protocols.
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The overall execution of our protocol converter starts from the execution of the master protocol. The first bus cycle of a master protocol always occupies the first available time slot for the scheduling ðt1 Þ; i.e. F ðm1 Þ*ft1 g in our Definition 2 if m1 is not zero. If m1 is zero, then Fðm2 Þ*ft1 g: If a master protocol begins its execution, its dual in the protocol converter is also executed because they are connected and matched for communication by the definition of a dual of a protocol. The slave protocol can be executed if the dual of the slave protocol is executed because they are connected and matched for communication. However, the slave protocol and its dual do not know when to execute if there is no external triggering. Thus, the message transfers between the dual of the master protocol and the dual of the slave protocol require a circuit that can trigger the execution of the dual of the slave protocol. The triggering signal must be produced from the dual of the master protocol because the master protocol determines when to execute the message transfers. For triggering execution of the slave protocol, the following constraint exists because the slave protocol cannot know when to begin its execution until the master protocol begins its execution. Let min½A be the smallest element in the set named A: Then, min½Fðmx Þ (x is 1 if m1 is not zero. Otherwise x is 2) must be less than or equal to min½F ðsy Þ (y is 1 if s1 is not zero. Otherwise, y is 2) where F is the function defined in Definition 2 and ti is less than tiþ1 for all i: Constraint 1. For the initiation of a slave protocol, min½F ðmx Þ pmin½Fðsy Þ
ð4Þ
must be satisfied where x is 1 if m1 is not zero and y is 1 if s1 is not zero while if m1 is zero, x is 2 and if s1 is zero, y is 2. The signal must be made of a combination of the control signals of the master protocol. This forces the triggering signal to be produced only after the control signals of the master protocol are asserted. Thus, the dual of the slave protocol can be executed only after the control signals of the master protocol are asserted. The slave protocol is also executed by the execution of its dual. Therefore, our protocol converter always satisfies Constraint 1. The implementation of the triggering circuit will be explained later in this section because it depends on the direction of protocols’ message transfers. If the execution of the slave protocol is triggered, both the master protocol and the slave protocol try to transfer messages. Generally, an address message is transferred from a master protocol to a slave protocol. For a write operation, a data message is also transferred from the master protocol to the slave protocol. But, for a read operation, the data message is transferred from the slave protocol to the master protocol. Thus, protocol converters must be different for protocols of a write operation and protocols of a read operation. In a write operation where an address message and a data message are transferred in the same direction, Constraint 2 must be satisfied to transfer the messages correctly. The address phase of the slave protocol must be executed after the address phase of the master protocol as specified in (5). Similarly, the data phase of the slave protocol must be executed after the data phase of the master protocol as specified in (6).
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Constraint 2. For message transfers in a write operation, min½F ðm2 Þ pmin½Fðs2 Þ
ð5Þ
and min½F ðm4 Þ pmin½Fðs4 Þ
ð6Þ
must be satisfied. For protocols of a write operation in our method, let the dual of the slave protocol begin to execute after the master’s data message is produced. Formally, our converter must satisfy (7). If (7) is satisfied, Constraint 2 is also satisfied. Thus, our converter can satisfy Constraint 2. min½F ðm2 Þ pmin½F ðm4 Þ pmin½F ðs2 Þ pmin½F ðs4 Þ :
ð7Þ
For our converter to satisfy (7), the triggering signal for the dual of the slave protocol must be produced at tP4 m : The exact timing of the triggering signal can be implemented directly from a j
j¼1
control signal of the master protocol which has the same timing as the triggering signal. It can also be implemented indirectly from a combination of the master protocol’s control signals and a counter circuit. A master’s control signal whose timing is the nearest to the timing of the necessary triggering signal must be selected as an input signal to the counter circuit that adjusts the timing of the control signal to the timing of the triggering signal. Then the dual of the slave protocol can be executed at t1þP4 m : Algorithm 1 implements a protocol converter that satisfies the constraint j j¼1 in (7). Algorithm 1 (Scheduling protocols of a write operation). If mj ðj ¼ 1; 2; 3; 4; 5Þ is zero, then F ðmj Þ is fg: Otherwise, Fðm1 Þ ¼ ft1 ; y; tm1 g; Fðm2 Þ ¼ t1þm1 ; y; tP
j¼1
Fðm3 Þ ¼ t1þP2
j¼1
;
m2j
; y; tP3 m j
j¼1
Fðm4 Þ ¼ t1þP3
mj
Fðm5 Þ ¼ t1þP4
; y; tP5 m
j¼1
j¼1
j
; y; tP4 j¼1
j¼1
;
mj
; m j
: m j
If sk ðk ¼ 1; 2; 3; 4; 5Þ is zero, then Fðsk Þ is : Otherwise, P P Fðs1 Þ ¼ t1þ 4 m ; y; t 4 m þs ; j¼1
j
j¼1
j
1
Y.M. Lee, K.H. Park / INTEGRATION, the VLSI journal 33 (2002) 71–88
Fðs2 Þ ¼ Fðs3 Þ ¼ Fðs4 Þ ¼
t1þP4
j¼1
t1þP4
j¼1
t1þP4
j¼1
Fðs5 Þ ¼
t1þP4
j¼1
mj þs1
mj þ
; y; tP4 j¼1
P2 k¼1
mj þ
P3
mj þ
P4
k¼1
k¼1
sk
mj þ
P2 k¼1
; y; tP4 j¼1
sk
; y; tP4
sk
; y; tP4
j¼1
j¼1
81
sk
mj þ
;
P3 k¼1
mj þ
P4
mj þ
P5
k¼1
k¼1
sk
sk
sk
; ; :
For protocols of a read operation whose address and data transfers are in the opposite directions, our converter must satisfy a constraint that is different from Constraint 2. For the address transfer, the constraint in (8) which is the same as (5) applies. However, for the data transfer, the data phase of the master protocol must be scheduled at the same time as or after the data phase of the slave protocol as in (9) because the master protocol must receive the data message that the slave protocol sends. Constraint 3. For message transfers in a read operation, min½F ðm2 Þ pmin½Fðs2 Þ
ð8Þ
min½F ðm4 Þ Xmin½Fðs4 Þ
ð9Þ
and
must be satisfied. For a slave protocol related to Constraint 3, min½Fðs2 Þ pmin½F ðs4 Þ by the definition of the temporal model of a protocol. Combining this constraint with Constraint 3, our converter must satisfy the following constraint in (10): min½F ðm2 Þ pmin½F ðs2 Þ pmin½F ðs4 Þ pmin½F ðm4 Þ :
ð10Þ
To satisfy (10), the triggering signal for the dual of the slave protocol must be produced as early as possible because a nonblocking protocol has a fixed period for its data transfer and the master protocol cannot wait for a data message from the slave protocol for more than the fixed period. The constraint in (10) can be rewritten as in (11). min½F ðm4 Þ min½Fðm2 Þ Xmin½Fðs4 Þ min½Fðs2 Þ :
ð11Þ
The constraint in (11) says that a protocol converter for nonblocking protocols of a read operation cannot exist if the master protocol’s fixed period between the beginning of the address phase and the beginning of the data phase must be greater than or equal to the slave protocol’s fixed period between the beginning of the address phase and the beginning of the data phase.
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Let a be the delay that may occur during the synchronization of message transfers between two input protocols. Then, (11) can be rewritten as (12). min½F ðm4 Þ min½Fðm2 Þ Xmin½Fðs4 Þ min½Fðs2 Þ þ a:
ð12Þ
Because both ðmin½Fðm4 Þ min½F ðm2 Þ Þ and ðmin½F ðs4 Þ min½F ðs2 Þ Þ in (12) are fixed time constants, a must be reduced to the minimum to enable a protocol converter to exist. For this reason, we exploit the advantage of static scheduling in the implementation of a protocol converter and do not use dynamic scheduling which increases a: The triggering signal for the dual of the slave protocol must be produced at t1þmx where x is 1 if m1 is not zero, and x is 2 if m1 is zero. Algorithm 2 implements a protocol converter that satisfies the constraint in (12). Algorithm 2 (Scheduling protocols of a read operation). If mj ðj ¼ 1; 2; 3; 4; 5Þ is zero, then F ðmj Þ is : Otherwise, Fðm1 Þ ¼ t1 ; y; tm1 ; Fðm2 Þ ¼ t1þm1 ; y; tP2 j¼1
;
mj
t1þP2
; y; tP3 m
; m
Fðm4 Þ ¼ t1þP3
; y; tP4 m
; m
Fðm5 Þ ¼ t1þP4
; y; tP5 m
: m
Fðm3 Þ ¼
j¼1
j¼1
j¼1
j
j¼1
j
j¼1
j
j¼1
j
j
j
If sk ðk ¼ 1; 2; 3; 4; 5Þ is zero, then Fðsk Þ is : Otherwise, Fðs1 Þ ¼ t1þmx ; y; tmx þs1 ; Fðs2 Þ ¼ t1þmx þs1 ; y; tm þP2 x
Fðs3 Þ ¼
t1þm þP2 x
Fðs4 Þ ¼
t1þm
Fðs5 Þ ¼
k¼1
P3
xþ
k¼1
t1þm þP4 x
k¼1
k¼1
;
sk
sk
; y; tm þP3
sk
P4
sk
x
; y; tm
k¼1
xþ
k¼1
; y; tm þP5 x
k¼1
;
sk
;
sk
sk
;
where x is 1 if m1 is not zero, and x is 2 if m1 is zero.
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If both the master protocol and the slave protocol are in execution, each performs its own message transfers because they are incompatible. The transfers may fail if the period of their message transfers are not overlapped, i.e. F ðm2 Þ-Fðs2 Þ ¼ fg
ð13Þ
F ðm4 Þ-Fðs4 Þ ¼ fg:
ð14Þ
and
In that case, message buffers must be introduced between the two input protocols to resolve the mismatch of their message transfer periods. Let B be a message buffer that holds a message until a new message arrives. Then, B can be modeled as a function that extends the message transfer period of the message sender. B½F ðmj Þ ¼ Fðmj Þ,F ðmjþ1 Þ,?,F ðm5 Þ
ð15Þ
B½F ðsk Þ ¼ Fðsk Þ,F ðskþ1 Þ,?,F ðs5 Þ:
ð16Þ
and
If message buffers are implemented in the converter, the two message transfer periods of the two nonblocking input protocols overlap. For protocols of a write operation, the message buffer holds an address message and a data message of the master protocol as summarized in the following equations: B½F ðm2 Þ -F ðs2 Þafg
ð17Þ
B½F ðm4 Þ -F ðs4 Þafg:
ð18Þ
and
For protocols of a read operation, the message buffer holds an address message of the master protocol and a data message of the slave protocol as summarized in the following equations: B½F ðm2 Þ -F ðs2 Þafg
ð19Þ
F ðm4 Þ-B½Fðs4 Þ afg:
ð20Þ
and
5. Experimental results Our method is tested on the converter in [10]. It is implemented on an Altera FPGA (EPF10K50VBC356-2) which is also shown in Fig. 6. The Altera MaxPlusII software compiles its design in AHDL, performs the technology mapping and reports the results on which our analysis is based. As in [9,10], our converter is a hierarchical structure that is a set of modular converters. Each modular converter supports a point-to-point communication between a pair of atomic protocols.
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Fig. 6. A system for our experiment.
In the experiment on the system shown in Fig. 6, the protocol converter (PC) must support communications among the four communicating components: the ISA bus interface (ISA), the SRAM buffer (SRAM), the SCSI I/O processor(SP), and the stripping buffer controller (SBC). Each component has several atomic protocols. Many of the atomic protocols are nonblocking protocols. Among the four components, ISA has nonblocking atomic protocols that act as a master protocol; they are iMasterWrite and iMasterRead which were depicted in Fig. 1. SRAM, SBC and SP have nonblocking atomic protocols that act as a slave protocol; they are mSlaveWrite and mSlaveRead of SRAM, bSlaveWrite and bSlaveRead of SBC, pSlaveWrite and pSlaveRead of SP. We discuss in detail the experimental results for the example nonblocking protocols of the read operation shown in Fig. 1. The converter must interface the iMasterRead protocol of ISA and the pSlaveRead protocol of SP in Fig. 1. The temporal model of the master protocol M is the temporal model of iMasterRead protocol CiMasterRead which is given in (2) of Example 1. The temporal model of the slave protocol S is the temporal model of pSlaveRead protocol CpSlaveRead which is given in (3) of Example 2. Thus, the temporal models of input protocols are summarized as follows: M ¼ CiMasterRead S ¼ CpSlaveRead
ðm1 ; m2 ; m3 ; m4 ; m5 Þ ¼ ð0; 1; 4; 1; 0Þ; ðs1 ; s2 ; s3 ; s4 ; s5 Þ ¼ ð0; 1; 2; 3; 0Þ:
ð21Þ
If mj is zero, F(mj ) is an empty set by Algorithm 2. Similarly, Fðsk ) is an empty set if sk is zero. Because m1 ; m5 ; s1 and s5 are zero, F ðm1 Þ ¼ fg; F ðm5 Þ ¼ fg; F ðs1 Þ ¼ fg; F ðs5 Þ ¼ fg:
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The first bus cycle of a master protocol always begins the overall execution. It occupies the first available time slot t1 : Because m1 is zero and m2 is one, which means the address phase requires only one bus cycle, i.e. only one time slot, F ðm2 Þ ¼ ft1 g: The master protocol is a nonblocking protocol. If it begins to execute, it executes without stop for a fixed period. Thus, if Fðm2 Þ is obtained, F ðm3 Þ and F ðm4 Þ can be obtained in sequence. Because m3 is four and m4 is one as in (21), F ðm3 Þ ¼ ft2 ; t3 ; t4 ; t5 g; F ðm4 Þ ¼ ft6 g: Because both m1 and s1 are zero, Constraint 1 becomes (22). min½F ðm2 Þ pmin½Fðs2 Þ :
ð22Þ
Because m1 is zero, mx is m2 in Algorithm 2, which results in F ðs2 Þ ¼ ft2 g: The result satisfies (22). The slave protocol is also a nonblocking protocol that executes without stop to the end of the protocol if it begins to execute. If F ðs2 Þ is obtained, F ðs3 Þ and F ðs4 Þ can be obtained in sequence as the following because s3 is two and s4 is three as in (21): F ðs3 Þ ¼ ft3 ; t4 g; F ðs4 Þ ¼ ft5 ; t6 ; t7 g: The scheduling result by Function F for the example input protocols in (21) is summarized in Table 1. If the message transfer periods of the two protocols do not match, message buffers must be implemented. For the address message, a message buffer is necessary because F ðm2 Þ-Fðs2 Þ ¼ fg:
ð23Þ
Table 1 Scheduling result for the example protocols (iMasterRead, pSlaveRead) F m1 m2 m3 m4 m5 s1 s2 s3 s4 s5
t1
t2
t3
t4
t5
*
*
*
*
t6
t7
* *
* *
* *
*
*
t8
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Table 2 Pairs of protocols supported by our method in the system of Fig. 6, which were unsupported in the previous work Protocol pairs (master, slave) (iMasterWrite of ISA, mSlaveWrite of SRAM) (iMasterRead of ISA, mSlaveRead of SRAM) (iMasterWrite of ISA, bSlaveWrite of SBC) (iMasterRead of ISA, bSlaveRead of SBC) (iMasterWrite of ISA, pSlaveWrite of SP) (iMasterRead of ISA, pSlaveRead of SP)
A message buffer for the data message is not necessary because the data message period of the two scheduled input protocols overlap in t6 as follows: F ðm4 Þ-Fðs4 Þ ¼ ft6 g:
ð24Þ
The resulting timing diagram of the communication through our converter is depicted in Fig. 5. The converter obtained above is one of the modular converters of the protocol converter in Fig. 6, which interfaces many pairs of atomic protocols of four components. For the operation of the system, each atomic protocol has its corresponding atomic protocols of the other components. The corresponding atomic protocols are determined by the system designer. Blocking protocols are not concerned in this paper because the previous methods have already supported blocking protocols. Table 2 listed pairs of nonblocking atomic protocols of the communicating components in our system of Fig. 6. The previous methods cannot support the protocols in Table 2. Because our method can implement a protocol converter that supports nonblocking protocols, our method makes our protocol converter support communications between all corresponding pairs of components in Fig. 6. This is a big improvement over the previous methods that support only blocking protocols.
6. Conclusion A protocol converter must be interposed between two communicating components if the two components have incompatible protocols. Previous studies on the protocol converter required that both the input protocols be blocking protocols whose blocking period is unlimited. However, many components have nonblocking protocols. For example, the components in the system of [9,10], which is depicted in Fig. 6, use many nonblocking atomic protocols. Their nonblocking protocols are summarized in Table 2. Even if a component has a blocking protocol, the blocking period of the protocol may be limited in some range in many cases to prevent deadlock or unfair monopolizing of communication resources. In the PCI bus [13], the blocking period of the blocking atomic protocols are limited to up to eight bus cycles. In this paper, we have presented a protocol converter for nonblocking protocols. The constraints of a nonblocking protocol are different in its protocol conversion than the constraints of a blocking protocol that the protocol converters of previous studies assumed as their input
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protocol. Especially for protocols of a read operation, a protocol converter for nonblocking protocols does not always exist. It can exist only if the constraints on the relative length of some periods in temporal models of the two protocols are satisfied. If the constraints are not satisfied, two incompatible protocols cannot communicate and the only possible solution is to change protocols. The satisfaction of the constraints depends not on the one protocol, but on the difference of the two input protocols. Even in the case that one of the input protocol must be fixed, a system designer has the flexibility to choose the other protocol whose difference with the first protocol satisfies the constraints. If the constraints are satisfied and a protocol converter can exist for given input protocols, we implement the duals of the input protocols because a protocol and its dual match for communication. It is a basic scheme in implementing a protocol converter to use a dual of the input protocol to execute the input protocol when the input protocol is incompatible with the other input protocol. However, using dual protocols is the only similarity between the protocol converter for blocking protocols and the protocol converter for nonblocking protocols. Given that the duals of input protocols, a control signal must be implemented that triggers the execution of the dual of the slave protocol when the master protocol executes. Then, our Algorithms 1 and 2 implement a protocol converter for nonblocking protocols of a write operation or a read operation, respectively. If the message transfer periods of the two scheduled input protocols do not overlap, message buffers must be implemented within the protocol converter to resolve a timing mismatch of the message transfers. An experimental result of our method is presented in Fig. 5 and Table 1 for the example input protocols shown in Fig. 1. Because our proposed method implements a protocol converter that supports nonblocking protocols, we could support all the protocols in Table 2, which are protocols of the components in the system shown in Fig. 6 [9,10]. Although we illustrated the case of nonblocking input protocols, our method can be easily applied to blocking input protocols with a limited blocking period. It is possible because such a blocking protocol can be modeled as a nonblocking protocol if we make the dual of the blocking input protocol execute up to the limitation of the blocking period all the time. The result of this research widens the application of protocol converters since it can be applied even if either of the input protocols is a nonblocking protocol or a blocking protocol with a limited blocking period.
References [1] K. Okumura, A formal protocol conversion method, in: Proceedings of the SIGCOMM, 1986, pp. 30–37. [2] S. Lam, Protocol conversion, IEEE Trans. Software Eng. 14 (3) (1988) 353–362. [3] J. Akella, K. McMillan, Synthesizing converters between finite state protocols, in: Proceedings of the IEEE International Conference on Computer-Aided Design, 1991, pp. 410–413. [4] S. Narayan, D. Gajski, Interfacing incompatible protocols using interface process generation, in: Proceedings of the ACM/IEEE Design Automation Conference, 1995, pp. 468–473. [5] J. Madson, B. Hald, An approach to interface synthesis, in: Proceedings of the International Symposium on System Synthesis, 1995, pp. 16–21. [6] R. Kumar, S. Nelvagal, S. Marcus, A discrete event systems approach for protocol conversion, in: Discrete Event Dynamic Systems: Theory and Applications, Vol. 7, Kluwer Academic Publishers, Dordrecht, 1997, pp. 295–315.
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[7] R. Passerone, J. Rowson, A. Sangiovanni-Vincentelli, Automatic synthesis of interfaces between incompatible protocols, in: Proceedings of the ACM/IEEE Design Automation Conference, 1998, pp. 8–13. [8] J. Smith, G. De Micheli, Automated composition of hardware components, in: Proceedings of the ACM/IEEE Design Automation Conference, 1998, pp. 14–19. [9] S. Park, Y. Lee, K. Kim, Y. Kim, J. Hwang, C. Lee, S. Baek, J. Yeo, K. Park, A video disk array for uncompressed HDTV signal, in: Proceedings of the International Workshop on HDTV, 1998, pp. 211–218. [10] Y. Lee, K. Park, Selective clock suppression of protocol modules for a low power protocol converter, IEICE Trans. Inform. Syst. E84-D (7) (2001) 196–199. [11] T. Shanley, D. Anderson, ISA System Architecture, 3rd Edition, Addison-Wesley, Reading, MA, 1995. [12] Manual, SYM53C770 SCSI I/O processor with Fast-20, rev. 1.0, Symbios Logic Inc., USA, 1995. [13] PCI local bus specification revision 2.1, 1995. [14] Data Sheet, KM6164002A, rev. 2.0, Samsung Electronics Co. Ltd., Korea, 1998. [15] Data Sheet, AT2021 MPEG-2 Video Encoder, rev. 3.0, Pentamicro Inc., Korea, 2001.
Young Moo Lee received B.S. degree, M.S. degree and Ph.D. degree in Electrical Engineering and Computer Science from the Korea Advanced Institute of Science and Technology (KAIST) in 1995, 1996, 2001. He is now a senior researcher at Telecommunications Network Laboratory of KT. His research interests include computer network, computer architecture, design automation. Kyu Ho Park received B.S. degree in Electronics Engineering from Seoul National University, Korea in 1973; M.S. degree in Electrical Engineering from KAIST in 1975; Dr. Ing. degree in Electrical Engineering from the Universite de Paris, France in 1983. He is now a professor at the department of Electrical Engineering and Computer Science, KAIST. His major interests include computer architecture, parallel processing and design automation. Dr. Park is a member of KISS, KITE, ACM, and IEEE.
A protocol converter for nonblocking protocols Young Moo Leea,*, Kyu Ho Parkb b
a Telecommunications Network Laboratory, KT 463-1, Jeonmindong, Yusungku, Taejon 305-811, South Korea Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology, 373-1, Kusungdong, Yusungku, Taejon 305-701, South Korea
Abstract A protocol converter must interface two communicating components if their protocols are incompatible. This paper presents a method to implement a protocol converter for nonblocking protocols since previous protocol converters insisted that both their input protocols be blocking protocols with a unlimited blocking period although many protocols in use are nonblocking protocols or blocking protocols whose blocking period is limited. Since a protocol converter for nonblocking protocols of a read operation may not exist, the existence must be determined by examining whether two input protocols satisfy several temporal constraints. If it can exist, the duals of the input protocols must be implemented to execute the input protocols because a protocol and its dual match for communication. We present algorithms that schedule the execution of the duals of the two input protocols. A circuit for a control signal must also be implemented to trigger the execution of the dual of the slave protocol when the master protocol is executed. If necessary, message buffers must be implemented to resolve the timing mismatch of the message transfer periods of the two scheduled input protocols. The experimental results show that our protocol converter supports nonblocking protocols. The same method can be applied to blocking protocols with a limited blocking period. The result in this paper widens the application of protocol converters. r 2002 Published by Elsevier Science B.V. Keywords: CMOS digital integrated circuit; Protocol converter; Nonblocking protocol
1. Introduction In hardware system design, some parts may be implemented with components that have a fixed communication protocol. If communicating components have incompatible protocols, a protocol converter [1–10] must be interposed. In Fig. 1, the protocol converter is interposed because the external communication protocols of the ISA bus master [11] (iMasterWrite, iMasterRead, *Corresponding author. E-mail addresses: [email protected] (Y.M. Lee), [email protected] (K.H. Park). 0167-9260/02/$ - see front matter r 2002 Published by Elsevier Science B.V. PII: S 0 1 6 7 - 9 2 6 0 ( 0 2 ) 0 0 0 4 9 - 4
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Y.M. Lee, K.H. Park / INTEGRATION, the VLSI journal 33 (2002) 71–88 SCSI I/O Processor
ISA bus iMasterWrite
pSlaveWrite
Protocol Converter
pSlaveRead
…
…
iMasterRead
bale a[31:2] d[31:0]
bale smemw# D(iMasterWrite) bale smemr#
D(pSlaveWrite)
ads# D(pSlaveRead) w_r# readyi#
D(iMasterRead)
…
smemw#
ads# w_r# readyi#
smemr# sa[ ] sd[ ]
Message buffer buf_a[ ] buf_d[ ]
SCSI bus
ads# a[31:2] d[31:0]
w_r# readyi#
a[ ] d[ ]
Fig. 1. A protocol converter.
Fig. 2. (a) A nonblocking protocol and (b) a blocking protocol.
etc.) are incompatible with those of the SCSI I/O processor [12] (pSlaveWrite, pSlaveRead, etc.). The four protocols shown in Fig. 1 (iMasterWrite, iMasterRead, pSlaveWrite, pSlaveRead) are nonblocking protocols. A communication protocol is a nonblocking protocol if its message transfer is executed in sequence and finishes in a fixed period without the acknowledgment of the other communication party as illustrated in Fig. 2(a). A blocking protocol is different in that its
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message transfer is conditionally executed if the other communication party acknowledges the transfer as illustrated in Fig. 2(b). Many communication protocols in use are nonblocking protocols: ISA bus master protocols [11], the slave protocols of the SCSI I/O processor [12], the protocols of many memory chips such as an SRAM [14] and video processors such as an MPEG-2 Encoder [15], etc. To support protocol conversion in many applications, nonblocking protocols must also be supported by a protocol converter. Supporting nonblocking protocols is important because they have an advantage in that they can be statically scheduled. A statically scheduled communication is faster than the equivalent communication dynamically scheduled. Another advantage is that the time for the communication is predictable. Thus, it is prefered in real-time applications where a certain performance must be guaranteed even in a worst case. In many blocking protocols, the blocking period is limited. For example, in the PCI bus [13], either a master device or a slave device cannot block a data transfer more than eight clock cycles. This kind of limitation is often introduced to prevent deadlock, livelock, starvation and to guarantee a fairness in a bus. However, because of the limited blocking period, such a blocking protocol cannot be supported in a protocol converter that assumes that the protocol’s blocking period is unlimited. Although there have been many studies on protocol converters, one of their common limitations is that they assume that input protocols must be blocking protocols. Their protocol converters do not support even blocking protocols with a limited blocking period. Okumura [1] used a communicating finite state machine (CFSM) model (similar to that of Lam’s [2]) and proposed an algorithm to construct a converter between two CFSMs that use blocking transfers. Akella and McMillan [3] proposed a similar protocol conversion technique between a pair of finite state machines that communicate in a blocking mode. Narayan and Gajski [4] transformed the protocol description in a hardware description language into combinations of five atomic operations: data signal in, data signal out, control signal in, control signal out, and time delay. The combinations were grouped into blocks whose execution was guarded by a condition on one of the control signals or by a time delay. The blocks of two protocols were matched to transfer the same amount of data by blocking the transfer. Madsen and Hald [5] proposed a converter between a pair of components that communicate by blocking messages for a data-only write operation. Kumar et al. [6] provided a protocol converter between a pair of discrete event systems communicating by blocking messages. Passerone et al. [7] built a protocol converter between two components, described in a derivative of regular expression, that communicate by blocking messages for a data-only write operation. Smith and De Michelli [8] assumed that every communicating component has the same buffer that uses the same predefined, simple communication protocol. The buffers have the same protocol so that they can communicate with each other. Then they presented a technique that maps the communication protocol of the component described in a hardware description language to the communication protocol of the buffer. The components exchange messages in a blocking mode through their buffers. In this paper, we present a protocol converter that supports nonblocking protocols. A protocol converter for nonblocking protocols must be different from a protocol converter for blocking protocols because nonblocking protocols and blocking protocols have different constraints for protocol conversion.
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The rest of this paper is organized as follows. Section 2 explains how a protocol converter for complex protocols can be modularly constructed as a set of smaller protocol converters for atomic protocols. In Section 3, we define the temporal model of a protocol and formulate the problem of constructing a protocol converter for nonblocking atomic protocols. Section 4 presents our method to implement a protocol converter for nonblocking protocols. Experimental results of the proposed method with input protocols in a real system are given in Section 5. The last section gives the conclusion.
2. Background From our experience in designing a protocol converter [9,10], we have found that an arbitrarily complex protocol of a communicating VLSI component can be hierarchically decomposed into a set of simpler protocols and a protocol converter for such complex protocols can be constructed modularly as a set of protocol converters for those simpler protocols. For example, Fig. 3(a) shows the protocol hierarchy of the processor [12] in Fig. 1. The lowest protocols in the hierarchy are atomic protocols which are numbered from (1) to (7). Fig. 3(b) shows the state graph representation of the processor’s protocol. An atomic protocol is a protocol whose signal in/out operations with regard to the other communication party form an independent, indivisible ordered set so that all the operations in the set are performed in one sequence if the protocol is executed. An operation that is not in the set cannot intervene in between the operations in the set during the protocol execution. The operations in the set are not performed at all if the protocol is not executed. Thus, the state graph
Idle pProcessor Req
Tt
Asi
Ack
Aso
Cs
pArbiter(1) pMaster pMasterWrite(2)
(1 ) Mdo
pMasterWriteBurst(3)
Mdi
Sdo
Sdi
Sro
Sri
(6)
(7)
pMasterRead(4) Mro
pMasterReadBurst(5)
Mri
pSlave pSlaveWrite(6) pSlaveRead(7)
(a) protocol hierarchy
Tbo
Mor
Tbi
Mir
(4)
(2) Cbo
Cbi
(3)
(5)
(b) state graph
Fig. 3. A hierarchical protocol.
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Idle Idle
Req
Ack
Idle
clk
Req hold#
hldai#
Ack (a) timing diagram
(b) state graph
Fig. 4. An atomic protocol, pArbiter.
of an atomic protocol is a cycle since an atomic protocol begins its execution at the initial state, performs signal operations in one sequence of states and returns to the initial state. For example, Fig. 4 shows the timing diagram and the state graph of the atomic protocol, pArbiter. Each signal followed by # is active low. The state graph is a cycle. Its origin and terminus are in the same state, ‘Idle’. The hold# output signal is asserted in the ‘Req’ state and the hldai# input signal is also asserted in the ‘Ack’ state. Both signals are deasserted in the ‘Idle’ state. All the signal operations are performed in one sequence. The seven leaf-states labeled (1)–(7) in Fig. 3(b) represent distinct state graphs of the seven atomic protocols. The left dashed-polygon indicates the state graph of the pArbiter protocol which is also in Fig. 4 for the illustration of an atomic protocol. The right dashed-polygon also indicates one of the atomic protocols, pMasterWriteBurst labeled (3). Although the pMasterWriteBurst protocol shares many states with the pMasterWrite protocol, they are distinct atomic protocols. The state graph of all the atomic protocols is a cycle. For simplicity, the return transition from the leaf-state to the initial state is not shown in Fig. 3(b). A higher protocol contains several sub-protocols as the processor’s protocol contains seven atomic protocols. The state graph of a higher protocol contains the state graphs of its subprotocols. If the sub-protocols have a common state, the common state is shared by the state graphs of the sub-protocols in the state graph of the higher protocol. In Fig. 3(b), pArbiter and pMasterWriteBurst protocols share only the initial state labeled ‘Idle’ while pMasterWrite and pMasterWriteBurst protocols share many states. In Fig. 3, the pMaster protocol is a sub-protocol of the processor’s protocol and it is also a higher protocol that contains four atomic protocols: pMasterWrite, pMasterWriteBurst, pMasterRead and pMasterReadBurst. The four branches containing four leaf-states numbered (2)–(5) in Fig. 3(b) represent the state graph of the pMaster protocol. Another feature of an atomic protocol is that its states have only one outgoing transition except for a self-looping transition. In other words, it supports only a one-way choice for possible
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branching to the next state except the current state itself. This feature of an atomic protocol reduces the exploration space and complexity for scheduling communications in our protocol converter which is modularly constructed as a set of protocol converters for atomic protocols as presented in our previous work [10]. 3. Problem formulation Our converter is assumed to be inserted among processors, controllers, memories and application-specific integrated circuits (ASIC) that communicate in a memory-mapped way. The communications between those components can be characterized by two message transfers: an address transfer and a data transfer. Around each message transfer, there may be exchanges of control signals that guide the message transfer. Let a phase be a set of bus cycles that have some common characteristics in a communication. Then, we can model a communication as five phases: the first control phase, an address transfer phase, the second control phase, a data transfer phase and the third control phase. The five-phase model emphasizes the address and data transfers and relatively ignores control phases because synchronizing message transfers is the essential task in the protocol conversion. The temporal model of a protocol can be modeled as a five-tuple and each tuple represents the number of clock cycles for each of the five phases, respectively. Definition 1 (Temporal model of a protocol). The temporal model of a protocol of a communicating VLSI component, C; is a 5-tuple: ð1Þ C ¼ ðc1 ; c2 ; c3 ; c4 ; c5 Þ; where c1 is the number of clock cycles for a control phase before an address transfer phase, c2 the number of clock cycles for an address transfer phase, c3 the number of clock cycles for a control phase between the address transfer phase and a data transfer phase, c4 the number of clock cycles for a data transfer phase, and c5 is the number of clock cycles for the last control phase after the data transfer phase. Example 1. The temporal model of the iMasterRead protocol, CiMasterRead in Fig. 1 of the ISA bus [11] is ð2Þ CiMasterRead ¼ ð0; 1; 4; 1; 0Þ: As shown in the timing diagram of the protocol in the upper division of Fig. 5, the address transfer phase begins without a preceding control phase. Thus, c1 is 0. After an address message is produced from the ISA bus port named sa, four bus cycles are necessary until a data message is returned to the port named sd. Thus, c3 is 4. c5 is also 0 as is c1 because the data transfer phase ends without any following control phase after the transfer. Example 2. The temporal model of the pSlaveRead protocol, CpSlaveRead in Fig. 1, of the processor [12] is ð3Þ CpSlaveRead ¼ ð0; 1; 2; 3; 0Þ:
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t2
t3
t4
t5
t6
77
t7
iMasterRead
clk sa sd bale smemr#
pSlaveRead
a d ads# cs# w_r# readyi# time
Fig. 5. Experimental result of protocol conversion between the pair of protocol, (iMasterRead, pSlaveRead).
As shown in the timing diagram of the protocol in the lower division of Fig. 5, the address transfer phase begins without a preceding control phase. Thus, c1 is 0. After an address message is produced from the processor’s port named a, two bus cycles are necessary until a data transfer begins. The data message is valid for three bus cycles which results in c4 being 3. c5 is 0 because the data transfer ends without a following control phase. For a nonblocking protocol, every phase in the temporal model has a fixed period. In Examples 1 and 2, every phase has a fixed period because both the iMasterRead protocol and the pSlaveRead protocol are nonblocking protocols. A blocking protocol always has a variable in its temporal model because the blocking period must be modeled as a variable. For example, if a protocol has a blocking data transfer, the corresponding tuple, c4 ; in the temporal model of the protocol is not a constant but a variable. In general, a tuple in our temporal model of a protocol has the form u þ v; where u is a nonnegative integer constant that represents a fixed period and v is a nonnegative integer variable that represents a variable period. Because a nonblocking protocol does not have any blocking phase, every tuple is a fixed period and v is always zero. There is a blocking phase in a blocking protocol. Thus, v of the corresponding tuple in the temporal model of the protocol must be greater than zero while u of the tuple must be zero. If the blocking period of the phase is not limited, v is also unlimited. If the blocking period of the phase is limited, the limitation must be reflected on the range of the variable v: For instance, for the protocols of the PCI bus [13], the maximum range of the variable v for the data transfer phase is eight because the blocking period of the phase is limited to up to eight bus cycles as described in Section 1. We have discussed our temporal model of a protocol. Now, we formulate the problem of protocol conversion on the basis of the above discussion. Section 2 showed that a protocol converter between two arbitrarily complex protocols can be modularly constructed as a set of protocol converters between pairs of atomic protocols. The
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modular architecture of such a protocol converter has been introduced in our previous study [10]. In [10], each module in the converter is the dual protocol implementation of an atomic protocol of a communicating component. If we can construct a protocol converter between a pair of nonblocking atomic protocols, we can construct a protocol converter for arbitrarily complex nonblocking protocols with a modular architecture as proposed in [10] and explained in Section 2. When two atomic protocols of a master and a slave component are given, we can obtain the temporal model of those protocols. Let the temporal model of a master protocol be M where M is (m1 ; m2 ; m3 ; m4 ; m5 ) and let the temporal model of a slave protocol be S where S is (s1 ; s2 ; s3 ; s4 ; s5 ). According to Definition 1, mj and sk (for j; kAf1; 2; 3; 4; 5g) in M and S; represent the tuple for the ith phase of master and slave protocols, respectively. Let ti (i is a natural number) be the ith time slot for scheduling two protocols in a protocol converter. The problem in this paper is implementing a protocol converter that maps mj and sk (j; kAf1; 2; 3; 4; 5g) to fti ji is a natural numberg to make the protocol converter guarantee correct message transfers between the two input protocols. Definition 2 (Problem). Implement a protocol converter that realizes a function F : fmj j j ¼ 1; 2; 3; 4; 5g,fsk j k ¼ 1; 2; 3; 4; 5g-fti j i is a natural numbergn such that messages between a master protocol and a slave protocol are correctly transferred.
4. Protocol converter The basic architecture of a converter is the implementation of dual protocols of its input protocols [3,4,7,8] because a protocol and its dual protocol match for the communication. A product machine of two finite state machines was proposed to operate as a converter in [3,7] where the two finite state machines represented the duals of two communicating protocols. The dual of a protocol is a protocol that is equivalent to the original protocol except that all its signals have the opposite direction in relation to the corresponding signals of the original protocol when a signal has only two directions in its definition, either an input or an output. In the architecture based on the implementation of the dual protocols of input protocols, only messages are exchanged between the two duals within the converter. Other control signals of the input protocols are exchanged locally at the boundary of the converter between a given input protocol of a component outside the converter and its dual protocol implemented within the converter. For example, a master protocol and its dual implemented in a protocol converter exchange control signals locally at the boundary of the protocol converter. The signals must not be seen by a slave protocol and the dual of the slave protocol. Similarly, a slave protocol and its dual exchange their control signals locally at the boundary of the protocol converter and the signals are not seen by the master protocol and the dual of the master protocol. The implementation of the dual protocols ensure that the input protocols can be executed without stop. However, the dual protocols do not ensure correct message transfers between input protocols. Because the dual of a protocol is already explained in previous studies [1–8] including ours [9,10], this section explains in detail how to ensure correct message transfers in our protocol converter for nonblocking protocols.
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The overall execution of our protocol converter starts from the execution of the master protocol. The first bus cycle of a master protocol always occupies the first available time slot for the scheduling ðt1 Þ; i.e. F ðm1 Þ*ft1 g in our Definition 2 if m1 is not zero. If m1 is zero, then Fðm2 Þ*ft1 g: If a master protocol begins its execution, its dual in the protocol converter is also executed because they are connected and matched for communication by the definition of a dual of a protocol. The slave protocol can be executed if the dual of the slave protocol is executed because they are connected and matched for communication. However, the slave protocol and its dual do not know when to execute if there is no external triggering. Thus, the message transfers between the dual of the master protocol and the dual of the slave protocol require a circuit that can trigger the execution of the dual of the slave protocol. The triggering signal must be produced from the dual of the master protocol because the master protocol determines when to execute the message transfers. For triggering execution of the slave protocol, the following constraint exists because the slave protocol cannot know when to begin its execution until the master protocol begins its execution. Let min½A be the smallest element in the set named A: Then, min½Fðmx Þ (x is 1 if m1 is not zero. Otherwise x is 2) must be less than or equal to min½F ðsy Þ (y is 1 if s1 is not zero. Otherwise, y is 2) where F is the function defined in Definition 2 and ti is less than tiþ1 for all i: Constraint 1. For the initiation of a slave protocol, min½F ðmx Þ pmin½Fðsy Þ
ð4Þ
must be satisfied where x is 1 if m1 is not zero and y is 1 if s1 is not zero while if m1 is zero, x is 2 and if s1 is zero, y is 2. The signal must be made of a combination of the control signals of the master protocol. This forces the triggering signal to be produced only after the control signals of the master protocol are asserted. Thus, the dual of the slave protocol can be executed only after the control signals of the master protocol are asserted. The slave protocol is also executed by the execution of its dual. Therefore, our protocol converter always satisfies Constraint 1. The implementation of the triggering circuit will be explained later in this section because it depends on the direction of protocols’ message transfers. If the execution of the slave protocol is triggered, both the master protocol and the slave protocol try to transfer messages. Generally, an address message is transferred from a master protocol to a slave protocol. For a write operation, a data message is also transferred from the master protocol to the slave protocol. But, for a read operation, the data message is transferred from the slave protocol to the master protocol. Thus, protocol converters must be different for protocols of a write operation and protocols of a read operation. In a write operation where an address message and a data message are transferred in the same direction, Constraint 2 must be satisfied to transfer the messages correctly. The address phase of the slave protocol must be executed after the address phase of the master protocol as specified in (5). Similarly, the data phase of the slave protocol must be executed after the data phase of the master protocol as specified in (6).
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Constraint 2. For message transfers in a write operation, min½F ðm2 Þ pmin½Fðs2 Þ
ð5Þ
and min½F ðm4 Þ pmin½Fðs4 Þ
ð6Þ
must be satisfied. For protocols of a write operation in our method, let the dual of the slave protocol begin to execute after the master’s data message is produced. Formally, our converter must satisfy (7). If (7) is satisfied, Constraint 2 is also satisfied. Thus, our converter can satisfy Constraint 2. min½F ðm2 Þ pmin½F ðm4 Þ pmin½F ðs2 Þ pmin½F ðs4 Þ :
ð7Þ
For our converter to satisfy (7), the triggering signal for the dual of the slave protocol must be produced at tP4 m : The exact timing of the triggering signal can be implemented directly from a j
j¼1
control signal of the master protocol which has the same timing as the triggering signal. It can also be implemented indirectly from a combination of the master protocol’s control signals and a counter circuit. A master’s control signal whose timing is the nearest to the timing of the necessary triggering signal must be selected as an input signal to the counter circuit that adjusts the timing of the control signal to the timing of the triggering signal. Then the dual of the slave protocol can be executed at t1þP4 m : Algorithm 1 implements a protocol converter that satisfies the constraint j j¼1 in (7). Algorithm 1 (Scheduling protocols of a write operation). If mj ðj ¼ 1; 2; 3; 4; 5Þ is zero, then F ðmj Þ is fg: Otherwise, Fðm1 Þ ¼ ft1 ; y; tm1 g; Fðm2 Þ ¼ t1þm1 ; y; tP
j¼1
Fðm3 Þ ¼ t1þP2
j¼1
;
m2j
; y; tP3 m j
j¼1
Fðm4 Þ ¼ t1þP3
mj
Fðm5 Þ ¼ t1þP4
; y; tP5 m
j¼1
j¼1
j
; y; tP4 j¼1
j¼1
;
mj
; m j
: m j
If sk ðk ¼ 1; 2; 3; 4; 5Þ is zero, then Fðsk Þ is : Otherwise, P P Fðs1 Þ ¼ t1þ 4 m ; y; t 4 m þs ; j¼1
j
j¼1
j
1
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Fðs2 Þ ¼ Fðs3 Þ ¼ Fðs4 Þ ¼
t1þP4
j¼1
t1þP4
j¼1
t1þP4
j¼1
Fðs5 Þ ¼
t1þP4
j¼1
mj þs1
mj þ
; y; tP4 j¼1
P2 k¼1
mj þ
P3
mj þ
P4
k¼1
k¼1
sk
mj þ
P2 k¼1
; y; tP4 j¼1
sk
; y; tP4
sk
; y; tP4
j¼1
j¼1
81
sk
mj þ
;
P3 k¼1
mj þ
P4
mj þ
P5
k¼1
k¼1
sk
sk
sk
; ; :
For protocols of a read operation whose address and data transfers are in the opposite directions, our converter must satisfy a constraint that is different from Constraint 2. For the address transfer, the constraint in (8) which is the same as (5) applies. However, for the data transfer, the data phase of the master protocol must be scheduled at the same time as or after the data phase of the slave protocol as in (9) because the master protocol must receive the data message that the slave protocol sends. Constraint 3. For message transfers in a read operation, min½F ðm2 Þ pmin½Fðs2 Þ
ð8Þ
min½F ðm4 Þ Xmin½Fðs4 Þ
ð9Þ
and
must be satisfied. For a slave protocol related to Constraint 3, min½Fðs2 Þ pmin½F ðs4 Þ by the definition of the temporal model of a protocol. Combining this constraint with Constraint 3, our converter must satisfy the following constraint in (10): min½F ðm2 Þ pmin½F ðs2 Þ pmin½F ðs4 Þ pmin½F ðm4 Þ :
ð10Þ
To satisfy (10), the triggering signal for the dual of the slave protocol must be produced as early as possible because a nonblocking protocol has a fixed period for its data transfer and the master protocol cannot wait for a data message from the slave protocol for more than the fixed period. The constraint in (10) can be rewritten as in (11). min½F ðm4 Þ min½Fðm2 Þ Xmin½Fðs4 Þ min½Fðs2 Þ :
ð11Þ
The constraint in (11) says that a protocol converter for nonblocking protocols of a read operation cannot exist if the master protocol’s fixed period between the beginning of the address phase and the beginning of the data phase must be greater than or equal to the slave protocol’s fixed period between the beginning of the address phase and the beginning of the data phase.
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Let a be the delay that may occur during the synchronization of message transfers between two input protocols. Then, (11) can be rewritten as (12). min½F ðm4 Þ min½Fðm2 Þ Xmin½Fðs4 Þ min½Fðs2 Þ þ a:
ð12Þ
Because both ðmin½Fðm4 Þ min½F ðm2 Þ Þ and ðmin½F ðs4 Þ min½F ðs2 Þ Þ in (12) are fixed time constants, a must be reduced to the minimum to enable a protocol converter to exist. For this reason, we exploit the advantage of static scheduling in the implementation of a protocol converter and do not use dynamic scheduling which increases a: The triggering signal for the dual of the slave protocol must be produced at t1þmx where x is 1 if m1 is not zero, and x is 2 if m1 is zero. Algorithm 2 implements a protocol converter that satisfies the constraint in (12). Algorithm 2 (Scheduling protocols of a read operation). If mj ðj ¼ 1; 2; 3; 4; 5Þ is zero, then F ðmj Þ is : Otherwise, Fðm1 Þ ¼ t1 ; y; tm1 ; Fðm2 Þ ¼ t1þm1 ; y; tP2 j¼1
;
mj
t1þP2
; y; tP3 m
; m
Fðm4 Þ ¼ t1þP3
; y; tP4 m
; m
Fðm5 Þ ¼ t1þP4
; y; tP5 m
: m
Fðm3 Þ ¼
j¼1
j¼1
j¼1
j
j¼1
j
j¼1
j
j¼1
j
j
j
If sk ðk ¼ 1; 2; 3; 4; 5Þ is zero, then Fðsk Þ is : Otherwise, Fðs1 Þ ¼ t1þmx ; y; tmx þs1 ; Fðs2 Þ ¼ t1þmx þs1 ; y; tm þP2 x
Fðs3 Þ ¼
t1þm þP2 x
Fðs4 Þ ¼
t1þm
Fðs5 Þ ¼
k¼1
P3
xþ
k¼1
t1þm þP4 x
k¼1
k¼1
;
sk
sk
; y; tm þP3
sk
P4
sk
x
; y; tm
k¼1
xþ
k¼1
; y; tm þP5 x
k¼1
;
sk
;
sk
sk
;
where x is 1 if m1 is not zero, and x is 2 if m1 is zero.
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If both the master protocol and the slave protocol are in execution, each performs its own message transfers because they are incompatible. The transfers may fail if the period of their message transfers are not overlapped, i.e. F ðm2 Þ-Fðs2 Þ ¼ fg
ð13Þ
F ðm4 Þ-Fðs4 Þ ¼ fg:
ð14Þ
and
In that case, message buffers must be introduced between the two input protocols to resolve the mismatch of their message transfer periods. Let B be a message buffer that holds a message until a new message arrives. Then, B can be modeled as a function that extends the message transfer period of the message sender. B½F ðmj Þ ¼ Fðmj Þ,F ðmjþ1 Þ,?,F ðm5 Þ
ð15Þ
B½F ðsk Þ ¼ Fðsk Þ,F ðskþ1 Þ,?,F ðs5 Þ:
ð16Þ
and
If message buffers are implemented in the converter, the two message transfer periods of the two nonblocking input protocols overlap. For protocols of a write operation, the message buffer holds an address message and a data message of the master protocol as summarized in the following equations: B½F ðm2 Þ -F ðs2 Þafg
ð17Þ
B½F ðm4 Þ -F ðs4 Þafg:
ð18Þ
and
For protocols of a read operation, the message buffer holds an address message of the master protocol and a data message of the slave protocol as summarized in the following equations: B½F ðm2 Þ -F ðs2 Þafg
ð19Þ
F ðm4 Þ-B½Fðs4 Þ afg:
ð20Þ
and
5. Experimental results Our method is tested on the converter in [10]. It is implemented on an Altera FPGA (EPF10K50VBC356-2) which is also shown in Fig. 6. The Altera MaxPlusII software compiles its design in AHDL, performs the technology mapping and reports the results on which our analysis is based. As in [9,10], our converter is a hierarchical structure that is a set of modular converters. Each modular converter supports a point-to-point communication between a pair of atomic protocols.
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Fig. 6. A system for our experiment.
In the experiment on the system shown in Fig. 6, the protocol converter (PC) must support communications among the four communicating components: the ISA bus interface (ISA), the SRAM buffer (SRAM), the SCSI I/O processor(SP), and the stripping buffer controller (SBC). Each component has several atomic protocols. Many of the atomic protocols are nonblocking protocols. Among the four components, ISA has nonblocking atomic protocols that act as a master protocol; they are iMasterWrite and iMasterRead which were depicted in Fig. 1. SRAM, SBC and SP have nonblocking atomic protocols that act as a slave protocol; they are mSlaveWrite and mSlaveRead of SRAM, bSlaveWrite and bSlaveRead of SBC, pSlaveWrite and pSlaveRead of SP. We discuss in detail the experimental results for the example nonblocking protocols of the read operation shown in Fig. 1. The converter must interface the iMasterRead protocol of ISA and the pSlaveRead protocol of SP in Fig. 1. The temporal model of the master protocol M is the temporal model of iMasterRead protocol CiMasterRead which is given in (2) of Example 1. The temporal model of the slave protocol S is the temporal model of pSlaveRead protocol CpSlaveRead which is given in (3) of Example 2. Thus, the temporal models of input protocols are summarized as follows: M ¼ CiMasterRead S ¼ CpSlaveRead
ðm1 ; m2 ; m3 ; m4 ; m5 Þ ¼ ð0; 1; 4; 1; 0Þ; ðs1 ; s2 ; s3 ; s4 ; s5 Þ ¼ ð0; 1; 2; 3; 0Þ:
ð21Þ
If mj is zero, F(mj ) is an empty set by Algorithm 2. Similarly, Fðsk ) is an empty set if sk is zero. Because m1 ; m5 ; s1 and s5 are zero, F ðm1 Þ ¼ fg; F ðm5 Þ ¼ fg; F ðs1 Þ ¼ fg; F ðs5 Þ ¼ fg:
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The first bus cycle of a master protocol always begins the overall execution. It occupies the first available time slot t1 : Because m1 is zero and m2 is one, which means the address phase requires only one bus cycle, i.e. only one time slot, F ðm2 Þ ¼ ft1 g: The master protocol is a nonblocking protocol. If it begins to execute, it executes without stop for a fixed period. Thus, if Fðm2 Þ is obtained, F ðm3 Þ and F ðm4 Þ can be obtained in sequence. Because m3 is four and m4 is one as in (21), F ðm3 Þ ¼ ft2 ; t3 ; t4 ; t5 g; F ðm4 Þ ¼ ft6 g: Because both m1 and s1 are zero, Constraint 1 becomes (22). min½F ðm2 Þ pmin½Fðs2 Þ :
ð22Þ
Because m1 is zero, mx is m2 in Algorithm 2, which results in F ðs2 Þ ¼ ft2 g: The result satisfies (22). The slave protocol is also a nonblocking protocol that executes without stop to the end of the protocol if it begins to execute. If F ðs2 Þ is obtained, F ðs3 Þ and F ðs4 Þ can be obtained in sequence as the following because s3 is two and s4 is three as in (21): F ðs3 Þ ¼ ft3 ; t4 g; F ðs4 Þ ¼ ft5 ; t6 ; t7 g: The scheduling result by Function F for the example input protocols in (21) is summarized in Table 1. If the message transfer periods of the two protocols do not match, message buffers must be implemented. For the address message, a message buffer is necessary because F ðm2 Þ-Fðs2 Þ ¼ fg:
ð23Þ
Table 1 Scheduling result for the example protocols (iMasterRead, pSlaveRead) F m1 m2 m3 m4 m5 s1 s2 s3 s4 s5
t1
t2
t3
t4
t5
*
*
*
*
t6
t7
* *
* *
* *
*
*
t8
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Table 2 Pairs of protocols supported by our method in the system of Fig. 6, which were unsupported in the previous work Protocol pairs (master, slave) (iMasterWrite of ISA, mSlaveWrite of SRAM) (iMasterRead of ISA, mSlaveRead of SRAM) (iMasterWrite of ISA, bSlaveWrite of SBC) (iMasterRead of ISA, bSlaveRead of SBC) (iMasterWrite of ISA, pSlaveWrite of SP) (iMasterRead of ISA, pSlaveRead of SP)
A message buffer for the data message is not necessary because the data message period of the two scheduled input protocols overlap in t6 as follows: F ðm4 Þ-Fðs4 Þ ¼ ft6 g:
ð24Þ
The resulting timing diagram of the communication through our converter is depicted in Fig. 5. The converter obtained above is one of the modular converters of the protocol converter in Fig. 6, which interfaces many pairs of atomic protocols of four components. For the operation of the system, each atomic protocol has its corresponding atomic protocols of the other components. The corresponding atomic protocols are determined by the system designer. Blocking protocols are not concerned in this paper because the previous methods have already supported blocking protocols. Table 2 listed pairs of nonblocking atomic protocols of the communicating components in our system of Fig. 6. The previous methods cannot support the protocols in Table 2. Because our method can implement a protocol converter that supports nonblocking protocols, our method makes our protocol converter support communications between all corresponding pairs of components in Fig. 6. This is a big improvement over the previous methods that support only blocking protocols.
6. Conclusion A protocol converter must be interposed between two communicating components if the two components have incompatible protocols. Previous studies on the protocol converter required that both the input protocols be blocking protocols whose blocking period is unlimited. However, many components have nonblocking protocols. For example, the components in the system of [9,10], which is depicted in Fig. 6, use many nonblocking atomic protocols. Their nonblocking protocols are summarized in Table 2. Even if a component has a blocking protocol, the blocking period of the protocol may be limited in some range in many cases to prevent deadlock or unfair monopolizing of communication resources. In the PCI bus [13], the blocking period of the blocking atomic protocols are limited to up to eight bus cycles. In this paper, we have presented a protocol converter for nonblocking protocols. The constraints of a nonblocking protocol are different in its protocol conversion than the constraints of a blocking protocol that the protocol converters of previous studies assumed as their input
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protocol. Especially for protocols of a read operation, a protocol converter for nonblocking protocols does not always exist. It can exist only if the constraints on the relative length of some periods in temporal models of the two protocols are satisfied. If the constraints are not satisfied, two incompatible protocols cannot communicate and the only possible solution is to change protocols. The satisfaction of the constraints depends not on the one protocol, but on the difference of the two input protocols. Even in the case that one of the input protocol must be fixed, a system designer has the flexibility to choose the other protocol whose difference with the first protocol satisfies the constraints. If the constraints are satisfied and a protocol converter can exist for given input protocols, we implement the duals of the input protocols because a protocol and its dual match for communication. It is a basic scheme in implementing a protocol converter to use a dual of the input protocol to execute the input protocol when the input protocol is incompatible with the other input protocol. However, using dual protocols is the only similarity between the protocol converter for blocking protocols and the protocol converter for nonblocking protocols. Given that the duals of input protocols, a control signal must be implemented that triggers the execution of the dual of the slave protocol when the master protocol executes. Then, our Algorithms 1 and 2 implement a protocol converter for nonblocking protocols of a write operation or a read operation, respectively. If the message transfer periods of the two scheduled input protocols do not overlap, message buffers must be implemented within the protocol converter to resolve a timing mismatch of the message transfers. An experimental result of our method is presented in Fig. 5 and Table 1 for the example input protocols shown in Fig. 1. Because our proposed method implements a protocol converter that supports nonblocking protocols, we could support all the protocols in Table 2, which are protocols of the components in the system shown in Fig. 6 [9,10]. Although we illustrated the case of nonblocking input protocols, our method can be easily applied to blocking input protocols with a limited blocking period. It is possible because such a blocking protocol can be modeled as a nonblocking protocol if we make the dual of the blocking input protocol execute up to the limitation of the blocking period all the time. The result of this research widens the application of protocol converters since it can be applied even if either of the input protocols is a nonblocking protocol or a blocking protocol with a limited blocking period.
References [1] K. Okumura, A formal protocol conversion method, in: Proceedings of the SIGCOMM, 1986, pp. 30–37. [2] S. Lam, Protocol conversion, IEEE Trans. Software Eng. 14 (3) (1988) 353–362. [3] J. Akella, K. McMillan, Synthesizing converters between finite state protocols, in: Proceedings of the IEEE International Conference on Computer-Aided Design, 1991, pp. 410–413. [4] S. Narayan, D. Gajski, Interfacing incompatible protocols using interface process generation, in: Proceedings of the ACM/IEEE Design Automation Conference, 1995, pp. 468–473. [5] J. Madson, B. Hald, An approach to interface synthesis, in: Proceedings of the International Symposium on System Synthesis, 1995, pp. 16–21. [6] R. Kumar, S. Nelvagal, S. Marcus, A discrete event systems approach for protocol conversion, in: Discrete Event Dynamic Systems: Theory and Applications, Vol. 7, Kluwer Academic Publishers, Dordrecht, 1997, pp. 295–315.
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[7] R. Passerone, J. Rowson, A. Sangiovanni-Vincentelli, Automatic synthesis of interfaces between incompatible protocols, in: Proceedings of the ACM/IEEE Design Automation Conference, 1998, pp. 8–13. [8] J. Smith, G. De Micheli, Automated composition of hardware components, in: Proceedings of the ACM/IEEE Design Automation Conference, 1998, pp. 14–19. [9] S. Park, Y. Lee, K. Kim, Y. Kim, J. Hwang, C. Lee, S. Baek, J. Yeo, K. Park, A video disk array for uncompressed HDTV signal, in: Proceedings of the International Workshop on HDTV, 1998, pp. 211–218. [10] Y. Lee, K. Park, Selective clock suppression of protocol modules for a low power protocol converter, IEICE Trans. Inform. Syst. E84-D (7) (2001) 196–199. [11] T. Shanley, D. Anderson, ISA System Architecture, 3rd Edition, Addison-Wesley, Reading, MA, 1995. [12] Manual, SYM53C770 SCSI I/O processor with Fast-20, rev. 1.0, Symbios Logic Inc., USA, 1995. [13] PCI local bus specification revision 2.1, 1995. [14] Data Sheet, KM6164002A, rev. 2.0, Samsung Electronics Co. Ltd., Korea, 1998. [15] Data Sheet, AT2021 MPEG-2 Video Encoder, rev. 3.0, Pentamicro Inc., Korea, 2001.
Young Moo Lee received B.S. degree, M.S. degree and Ph.D. degree in Electrical Engineering and Computer Science from the Korea Advanced Institute of Science and Technology (KAIST) in 1995, 1996, 2001. He is now a senior researcher at Telecommunications Network Laboratory of KT. His research interests include computer network, computer architecture, design automation. Kyu Ho Park received B.S. degree in Electronics Engineering from Seoul National University, Korea in 1973; M.S. degree in Electrical Engineering from KAIST in 1975; Dr. Ing. degree in Electrical Engineering from the Universite de Paris, France in 1983. He is now a professor at the department of Electrical Engineering and Computer Science, KAIST. His major interests include computer architecture, parallel processing and design automation. Dr. Park is a member of KISS, KITE, ACM, and IEEE.