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A silicon pixel detector with routing for external VLSI readout
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Nuclear Instruments and Methods in Physics Research A275 (1989) 564-573 North-Holland, Amsterdam
A SILICON PIXEL DETECTOR WITH ROUTING FOR EXTERNAL VLSI READOUT S.L . THOMAS and P. SELLER Rutherford Appleton Laboratory, Chilton, Didcot, OXON, OXII OQX, UK
A silicon pixel detector with an array of 32 X 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector . Metal routing connects the pixels to a pad configuration optimised for bonding to an existing VLSI readout chip . Detectors have been laid out with two sizes of pixels, approximately 1 mm2 and 0.01 mm2. The detailed design of the pixels, their layout and method of readout are discussed. A number of test structures have been incorporated into the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future . 1. Introduction In the disciplines of high energy physics, life sciences and space science there is a need for a new type of two dimensional solid state detector for ionising radiation. The requirement is for a large active area device with fast readout together with unambiguous signal position information for events which occur over a small number of pixels . This has not been met by any of the presently available solid state detectors. CCDs are slow and of limited area, crossed silicon strip detectors have ambiguity problems and silicon drift detectors may have both ambiguity and slow readout for some applications . The advantage of the pixel detectors now under development is that each individual pixel has some level of signal processing . This parallel signal processing could be quite sophisticated or very simple . It could provide a trigger and address to indicate that a specific pixel or pattern of pixels have a signal above a certain threshold. Alternatively it could be a simple signal routing structure with some filtering. The challenge is to tie together the signal processing with the detector elements . The aim of the present work is to integrate active circuitry on a silicon detector . This active circuitry may eventually take the form of an amplifier-discriminator with hit-pixel addresses being fed out from the array. At present, however, there is a need for a technology on which to build the detectors and to investigate integrating the active devices. Southampton University have a fabrication facility and are developing a process that can be used to build silicon strip detectors on high resistivity (5 kQ cm) n-type (111) silicon. This process is being used to fabricate pixel detectors and test structures. The pixel detectors are very simple p-n diode arrays of 16 x 32 elements . They are routed on a metal layer to rows of 0168-9002/89/$03 .50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
bonding pad connections . These pads can be bonded to a 128 channel amplifier readout chip which already exists. Two sizes of detectors have been designed, one with 100 Wm hexagonal pixels and one with 1 mm pixels . These cover an important range of sizes. Ref. [1] shows why 100 [ m is a good size for high energy physics and this is also a convenient size for many life science applications . These first detectors are an attempt to get a feel for the problems involved with diode arrays and pixel routing structures on the process. Measurements of the arrays will also help develop the process before going on to the active device fabrication or bump technology . To investigate these possibilities extensive test structures have been designed on the wafers and will feed back into the simulation work being performed. 2. Layout of pixel detectors Arrays of hexagonal pixels of width 1 and 0.1 mm have been laid out on the wafer shown in fig. 1 . The pixels in both cases comprise p-implants in n-type bulk material, shown in fig. 2. The p-implants are reverse biased to a negative voltage with respect to the back of the wafer. The wafer is 500 [Lm thick and totally depleted to the back surface. Pixels are fabricated by cutting holes in the 2000 Á field oxide then growing a thin oxide through which boron is implanted. Contact is made to the pixel by cutting through the thin oxide and connecting to metal. Contact is not made over the whole pixel area partly due to routing requirements but also in order to reduce the risk of pin-hole defects in the implant shorting metal to the depleted substrate . The large array, shown in fig. 3, contain 512 pixels in an array 32 long and 16 wide at a separation of 10 pm .
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Fig. 1 . The 4 in . wafer (metal routing not shown).
thick oxide metal
contact
active pixel p type implant 4 kohm cm n type silicon fully depleted + ! R n type contact to back surface biased positive
Fig . 2. Cross-section of implant and metal (not to scale) .
The whole array occupies an area 33 mm x 14 mm . In principle the detector could be extended in width, up to around 80 pixels, limited only by the area of the 4 in . wafer . Each pixel is connected to metal routing at a number of points along its diameter. This reduces the series resistance that collected charge has to pass through before it reaches the metal . The implant sheet resistance is expected to be several hundred St/O, so this is an important consideration for low noise readout . In future designs, an additional level of metal will contact the implant at several points over the whole of its surface area, to further reduce the resistance. The width of metal routing is 8 [,m which results in a low series resistance (less than 50 S2 for routing covering 20 mm) . Thicker tracks are not used as they would II . CONTRIBUTED PAPERS
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Fig. 3. One half of large pixel array with routing.
have a higher capacitance to pixels over which they have to cross. The capacitance values are comparable with interstrip capacitances for strip detectors, but it must be remembered that in the pixel array, there is cross-talk between pixels which are -widely separated . The pixels connect to bond pads arranged in two rows at pitches of 88 pm. The Microplex readout chips (MX2) are bonded onto these pads and are placed side by side at both ends of the detector such that four chips
can read out the one array of 512 elements . The operation of the Microplex chip is discussed in ref. [2]. The small array consists of 256 pixels in an area roughly 1 .6 mm X 1 .6 mm, as shown in fig. 4. The spacing between the hexagonal implants is chosen to be 12 p m which gives low interpixel capacitance and good uniformity of charge collection over the whole active area . In order to route out the pixels, narrow tracks of 5 Wm width and spacing are required. The same bond
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Fig. 4. Small pixel array with routing. pads are used as in the large array, but in this case it is not the intention to place detectors side by side . The 6 x 5 mm area required for the bonding and routing contains a large dead area where no pixels are located, as shown in fig. 5. Both detectors have guard rings surrounding the pixels arrays in order to prevent leakage currents from the sawn edges of the silicon reaching the detector . The rings are biased separately from the pixels to allow the optimum bias to be found such that edge leakage is removed without upsetting the charge collection of outer pixels .
3. Description of the diode process Work on this high resistivity silicon process has only recently started and the process is being developed in parallel with the detector structures . Prior to this work the process was being used to investigate fabrication of silicon strip detectors. These were the simplest form of detectors that could be used to test the characteristics of process in this type of application . This work has continued on the present wafers to assess the effect of process changes and to look at process uniformity. Three 5 in . masks are used in the process, with an II . CONTRIBUTED PAPERS
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S. L. Thomas, P. Seller / A silicon pixel detector with routing
Fig . 5 . Small array with routing and bond pads . optional passivation mask, and have been made at the Electron Beam Lithography Facility at The Rutherford Appleton Laboratory . Mask 1 is used to define cuts through the 2000 .4 thermally grown field oxide. The 4 in . wafers are then oxidized to produce 200 i1 thin oxide over the cut active areas . Boron is implanted through the thin oxide which is then activated to produce the p-type pixel elements . Mask 2 defines the contact cuts through the oxide to the underlying silicon . For some devices contact to the substrate as well as the p-implants will be needed. As
the field oxide mask defines the p-implants, contacts to the substrate will necessarily have to be through thick oxide. The resultant over etching around the thin oxide contact holes may affect the p-type silicon and this is being investigated. Mask 3 defines the single metal layer used for routing and contact. A few percent silicon is dissolved in the aluminium which is sputtered onto the wafer. This is a common precaution to stop aluminium dissolving silicon and creating diode shorts . Although this metal should be patterned using ion etching, careful wet etch-
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S.L . Thomas, P. Seller /A silicon pixel detector with routing
ing is used to avoid a potential problem . Ion etching does not 100% specifically etch metal in preference to oxide. A problem has been observed where the thin oxide covering the edges of the diodes can be etched away causing large leakage currents . The wet etch process is sufficiently specific not to cause this problem . Future developments of the process will be aimed at allowing an extra metal routing layer to be fabricated. This will make building ac coupled detectors feasible. Also the work on field oxide transistors and local area conditioning will be used to bias the pixels and make active devices .
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4 . Design of test structures Previous runs of the process have emphasised the need for comprehensive test structures to monitor process parameters . The layout includes capacitors, resistors and diodes in a variety of sizes up to 5 mm square . Two types of 5 mm MOS capacitors have been fabricated ; one consisting of metal over implant (with thin oxide) and the other over substrate (thick oxide). These will give information on the two surface conditions . Smaller 1 mm square capacitors have separate connections to the implant and substrate so that biases can be applied . Van der Pauw structures are incorporated to measure sheet resistances . The 5 mm square diodes should be large enough for accurate measurements of leakage currents, and will additionally give an indication of the yield of devices which have large metal to implant contact windows . If the implant mask were to have dark areas on it due to small defects, then there could be a direct connection from the substrate to metal at these points, as the implant would be missing . The leakage current from these pin-hole contacts will be proportional to their area, so an estimate of area can be made. A direct metal to substrate contact of 5 mm square has been included to facilitate this estimate . The smaller diodes and the pixels themselves will not suffer from pin-hole shorts as the area of the contact window is much smaller. In addition to the process monitoring structures, a variety of active devices have been laid out. Metal gate field-oxide FETs with a wide range of gate dimensions will give information on the punchthrough characteristics of high resistivity devices . Substrate connections are made on the top surface of the silicon near to the devices, in addition to the back surface connection, to provide more control over the depletion regions. The intention is to bias the devices such that both sourceto-substrate and drain-to-substrate diodes are strongly reverse biased . If drain-induced lowering of the source potential barrier can be reduced, then punchthrough will be minimised even for short gates. Once transistor parameters have been extracted from the present test
Fig. 6 . Metal gate FET with pixel as source. structures, designs of simple amplifiers or switching circuits can be considered for future layouts. Particular importance has been given to understanding the behaviour of transistors which are in close proximity to a fully depleted pixel . In this case, the top surface substrate connections must not disrupt the charge collection of the pixel, so it may be more difficult to prevent punchthrough. In fig . 6, a metal gate FET uses the pixel implant as its source and has no additional substrate connection . If the FET works as a switch, then it could be used as the basis of multiplexed readout in future designs (where additional metal layers will be available for the routing of x-y address lines). If a punchthrough current cannot be prevented, the device can be used in a different application, as a bias resistor for pixels which are ac coupled to the readout electronics . The effective resistance can be controlled by the gate voltage, and the need for large polysilicon resistors is obviated . Thus large ac pixel arrays become practical, provided an extra metal layer is available . In the present design, ac pixels are tested individually to avoid the routing problems associated with arrays . 5 . Simulations of test structures Simulations have been carried out in order to estimate capacitances between routing and pixels, and also to investigate the behaviour of active devices . A number of modelling programs are available which can solve the potential distributions in silicon, but the assumptions and simplifications made by the programs vary widely. Care has to be taken to ensure that models are applicaII . CONTRIBUTED PAPERS
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Strip 2
10 .000 8 .000 6.00 1 .00 1 .00
.ó
o.0000 00
5.000
10 000
15 .000 Implant 2
Implant 1
Fig. 7. Equipotentials around two implants. Implants at 0 V, back surface at 20 V, contours at 0.1 V steps. ble in each case before meaningful results can be obtained . The test structures were laid out with this in mind, such that measurements will allow the testing of simulations under a wide range of conditions . In the case where the silicon is fully depleted, the calculation of potentials is straightforward as a uniform charge density can be assumed (equal to the doping density) and the solution of Poisson's equation readily found [3]. In the example of fig. 7, the equipotentials are plotted around two p-implants under reverse bias. The potential along the surface (fig. 8) shows a characteristic parabolic potential barrier between the strips . In order to evaluate capacitance, the potential solution is found with the charge density set to zero . The stored energy (and hence capacitance) is obtained by integration over the appropriate regions. For simple geometries, the results can be compared with analytical (conformal mapping) solutions and the accuracy of the modelling evaluated. In fig. 9, a voltage has been applied between two 5 lint strips at 5 pm spacing. Boundary conditions are set at a suitably large distance from the strips such that the fields near the strips are not disturbed. Provided the fields are low at the Potential (V)
1 .00010.800 0.600 0.10a0.10010.00o , _M 00 Y coord 0.000
0.000 0.000
0.o00 0.000
0.000 0.000
i1 .000 O. 00O
Fig. 8. Potential along surface between implants .
15 .000 0.000
30 .000 +0 .000 lo .ooo 20 .000 Fig. 9. Equipotentials between two 5 [1-m metal strips . Estimated capacitance 77 pF/m, analytical solution 81 pF/m . 0.0006 .000
boundaries, the stored energy will give a good estimate of the capacitance . In this example, the analytical solution is about 4% higher than the estimate . In the case where there are regions of nondepleted silicon, an iterative solution of Poisson's equation is required . The charge density at any point now depends on the shift in Fermi level, so must be recalculated at each stage until convergence is obtained . A program has been written [4] to solve these off-state problems and is currently being developed to handle more complex geometries. In real semiconductor devices, the flow of current can change the potential and carrier densities in the silicon. The above off-state solutions can be used only when the currents are very small (such as leakage currents) when the perturbation of the field is negligible. An on-state solution of FET structures is available from MINIMOS [5], although the accuracy of its modelling is expected to be low for high-resistivity silicon. (A number of default material parameters are likely to need adjustment, and the mesh becomes rather coarse near the surface when large depletion regions exist.) MINIMOS solutions are shown in figs . 10-13 for a metal gate FET which could be used in the readout of pixels in future designs. It is important to know how punchthrough will affect its switching characteristics and whether the substrate bias will improve its performance. In order to bring MINIMOS closer to its normal regime of operation the substrate doping has been set 100 times higher than the actual doping. The solutions for a gate length of 1 l.Lm illustrate behaviour which would be expected in a real device of 10 lint length (as depletion depths depend inversely on the square root of doping density) . In these plots, the x axis is along the surface and the y axis is into the silicon. Potential (in V) and log (hole concentration/cm3) are
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S. L. Thomas, P. Seller / A silicon pixel detector with routing
1 -.75.25
- .25
-2 .25-2 .75-3 .253 .50 3 .00 2 .50 2.00 1 .50 1 .00
'i'uliuiiiiiill~_ ' .1
T AXIS .19 -4
50 .001-.0
.
Z AXIS -10 X AXIS -10
Fig. 10. Potential distribution and hole concentration for FET. Substrate at 0 V, gate at 0 V . on the z axis . The gate extends from x = 0 to x = 1 .0 Wm with a gate oxide thickness of 2000 f1 (not shown in the plots) . In all the examples the source is at 0 V and the drain is at - 3 V . In the absence of the back surface bias (fig . 10), a high hole concentration under the gate is observed . There is only a small potential barrier between source and drain, so a significant punchthrough current can flow by diffusion. Increasing the gate voltage has little effect on the current (fig. 11) as the current extends several microns into the bulk where the gate has little effect . In fig . 12, the increase in substrate reverse bias reduces the depth of punchthrough to 0 .8 W m, as holes are swept towards the surface by the applied field . When the gate voltage is increased (fig . 13) the device is switched off. There is now a large barrier to the diffusion current, both along the surface (due to the gate) and in the bulk (due to the substrate reverse bias) . It can be seen that the device would be useful as a switch or amplifier, provided the back surface is maintained at a large positive voltage. An important consideration for future designs involving ac coupling is the behaviour of p-implants which
are allowed to float in potential close to a biased implant. Floating strips have already been incorporated into designs of strip detectors where the strips are intended to improve the linearity of capacitive charge division . Measurements on these strips have shown that large voltage drops can occur across small distances at the surface (typically, 5 V across 12 ~tm) when a large back surface bias is applied. A static off-state solution of Poisson's equation predicts voltages of this order, but this technique ignores the floating p-n junction . A better technique is to regard the biased and floating implants as the drain and source of a transistor which has no gate . For a given source potential, Vds, there will be two components of source current. Firstly, a component of the leakage current from the bulk silicon will be collected at the source . This current will increase if Vds decreases, as more electric field lines will end on the source . Secondly, there is the punchthrough diffusion current from source to drain . If Vds decreases, this current will decrease. At some value of Vds the two components of current will become equal (and opposite) and the source will reach a steady floating voltage . This voltage will depend on the relative sizes of punchthrough
.25 -25- .75-1 .25 ~ -1 .75-2 .25-2 .75-3 .25-
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3.50 3.00 2.50 2.00 1 .50 '1 1111111111w'r 1 .00 .50 -1 T AXIS -10 .001- .0
' .1
Z AXIS -10 X AXIS -10 -1
Fig . 11 . Potential distribution and hole concentration for FET . Substrate at 0 V, gate at 4 V. 11 . CONTRIBUTED PAPERS
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3 .50 3 .00 2 .50 2 .00 1 .50 1 .00 T AXIS -10 -4
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X
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Fig. 12 . Potential distribution and hole concentration for FET. Substrate at 20 V, gate at 0 V.
and leakage currents . For example, if large leakages are present the floating voltage will be high, and the potential distribution will be close to the that obtained for the off-state.
Further work is needed to understand the punch-
through characteristics in the absence of the gate . It is
clear that the substrate bias will have a significant effect as holes will be swept towards the top surface by the large applied field. The volume over which punchthrough occurs will reduce, as was observed for the
MOSFETs in figs . 10-13 . In addition, the potential barrier along the surface between source and drain may be increased if a suitable overbias is applied. A potential distribution, similar to that shown in fig. 7, will add linearly to that already present in the silicon if a bias voltage above that required for full depletion is applied.
The increased parabolic barrier between source and drain will tend to sweep holes towards the implants, reducing the punchthrough current.
It was mentioned earlier that top surface connections to the substrate have been made at points around certain devices. It will be possible to locally modify the
3 .50 3 .00 2 .50 2 .00 1 .50 1 .00 .50
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fields in the substrate in order to ensure that a large potential barrier is maintained around source regions, to reduce the diffusion current. The additional control over the potential distribution should allow the devices to work under a wider range of operating conditions .
6. Conclusions It has been demonstrated that pixel arrays can be laid out using a simple three mask process. The use of a VLSI readout chip has simplified the routing such that large areas of silicon can be covered with pixels . Ideas for future techniques of readout have been discussed,
and the need for more detailed simulations has been emphasised . The development of new programs must
reflect the particular demands of high resistivity device simulation, and will need to be linked to the results from test structures . Future pixel layouts will include ac
coupled pixel arrays and multiplexed arrays, when additional metal routing becomes available.
3 .50 3 .00 2 .50 2 .00 1 .50 1 .00 .50 T AXIS .10 -1 .00 T- .0
Z AXIS -10 X AXIS -le -1
Fig. 13. Potential distribution and hole concentration for FET. Substrate at 20 V, gate at 4 V.
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Acknowledgements
Questions
The authors would like to thank G . Ensell at Southampton University and G . Hall at Imperial College for their work on the development of the diode process, and J . Ellison at Imperial College for contributions to the test structures.
Q . (E. Heijne, CERN) : Why do you use metal gate transistors? Are such transistors satisfactory? A . : There is no polysilicon available in the processing . We will have to make different devices for high performance electronics .
References [1] H . Spieler, Semiconductor Detector and Integrated Electronics Development (SSC Detector R&D proposal) LBL (July 1987) . [2] P . Seller, P .P . Allport and M . Tyndel, IEEE Trans . Nucl . Sci . NS-35 (1) (1988) 176 . [3] C .S. Biddlecome, N .S. Diserens and C .P . Riley, PE2D User Guide. 2d/axisymmetric static and dynamic electromagnetic analysis package (Version 6) RAL 81089. [4] C. Hunt and C. Greenough, Examples in the use of the Finite Element Library : Non-linear Electrostatic Solution, RAL 85113 . [5] S . Selberherr, A . Schutz and H .W . Potzl, IEEE Trans . Electron Devices ED-27 (1980) 1540 .
Q . (S . Audet, TU Delft) : Is there no problem with parasitic capacitances related to the metal lines which run over the other pixels? A . : Yes, this will be one of the main problems .
Q. (E .R. Fossum, Columbia) : Why are the pixels hexagonal? Comment (P. Seller, RAL) : We wanted to investigate how charge is shared between multiple pixels . In a hexagonal array in any point one may share at most between three nodes, which is simpler than sharing between four nodes . Also reconstruction afterwards should be easier, and finally, hexagons are easier to route .
II . CONTRIBUTED PAPERS
Nuclear Instruments and Methods in Physics Research A275 (1989) 564-573 North-Holland, Amsterdam
A SILICON PIXEL DETECTOR WITH ROUTING FOR EXTERNAL VLSI READOUT S.L . THOMAS and P. SELLER Rutherford Appleton Laboratory, Chilton, Didcot, OXON, OXII OQX, UK
A silicon pixel detector with an array of 32 X 16 hexagonal pixels has been designed and is being built on high resistivity silicon. The detector elements are reverse biased diodes consisting of p-implants in an n-type substrate and are fully depleted from the front to the back of the wafer. They are intended to measure high energy ionising particles traversing the detector . Metal routing connects the pixels to a pad configuration optimised for bonding to an existing VLSI readout chip . Detectors have been laid out with two sizes of pixels, approximately 1 mm2 and 0.01 mm2. The detailed design of the pixels, their layout and method of readout are discussed. A number of test structures have been incorporated into the wafer to enable measurements to be made on individual pixels together with a variety of active devices. The results will give a better understanding of the operation of the pixel array, and will allow testing of computer simulations of more elaborate structures for the future . 1. Introduction In the disciplines of high energy physics, life sciences and space science there is a need for a new type of two dimensional solid state detector for ionising radiation. The requirement is for a large active area device with fast readout together with unambiguous signal position information for events which occur over a small number of pixels . This has not been met by any of the presently available solid state detectors. CCDs are slow and of limited area, crossed silicon strip detectors have ambiguity problems and silicon drift detectors may have both ambiguity and slow readout for some applications . The advantage of the pixel detectors now under development is that each individual pixel has some level of signal processing . This parallel signal processing could be quite sophisticated or very simple . It could provide a trigger and address to indicate that a specific pixel or pattern of pixels have a signal above a certain threshold. Alternatively it could be a simple signal routing structure with some filtering. The challenge is to tie together the signal processing with the detector elements . The aim of the present work is to integrate active circuitry on a silicon detector . This active circuitry may eventually take the form of an amplifier-discriminator with hit-pixel addresses being fed out from the array. At present, however, there is a need for a technology on which to build the detectors and to investigate integrating the active devices. Southampton University have a fabrication facility and are developing a process that can be used to build silicon strip detectors on high resistivity (5 kQ cm) n-type (111) silicon. This process is being used to fabricate pixel detectors and test structures. The pixel detectors are very simple p-n diode arrays of 16 x 32 elements . They are routed on a metal layer to rows of 0168-9002/89/$03 .50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)
bonding pad connections . These pads can be bonded to a 128 channel amplifier readout chip which already exists. Two sizes of detectors have been designed, one with 100 Wm hexagonal pixels and one with 1 mm pixels . These cover an important range of sizes. Ref. [1] shows why 100 [ m is a good size for high energy physics and this is also a convenient size for many life science applications . These first detectors are an attempt to get a feel for the problems involved with diode arrays and pixel routing structures on the process. Measurements of the arrays will also help develop the process before going on to the active device fabrication or bump technology . To investigate these possibilities extensive test structures have been designed on the wafers and will feed back into the simulation work being performed. 2. Layout of pixel detectors Arrays of hexagonal pixels of width 1 and 0.1 mm have been laid out on the wafer shown in fig. 1 . The pixels in both cases comprise p-implants in n-type bulk material, shown in fig. 2. The p-implants are reverse biased to a negative voltage with respect to the back of the wafer. The wafer is 500 [Lm thick and totally depleted to the back surface. Pixels are fabricated by cutting holes in the 2000 Á field oxide then growing a thin oxide through which boron is implanted. Contact is made to the pixel by cutting through the thin oxide and connecting to metal. Contact is not made over the whole pixel area partly due to routing requirements but also in order to reduce the risk of pin-hole defects in the implant shorting metal to the depleted substrate . The large array, shown in fig. 3, contain 512 pixels in an array 32 long and 16 wide at a separation of 10 pm .
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Fig. 1 . The 4 in . wafer (metal routing not shown).
thick oxide metal
contact
active pixel p type implant 4 kohm cm n type silicon fully depleted + ! R n type contact to back surface biased positive
Fig . 2. Cross-section of implant and metal (not to scale) .
The whole array occupies an area 33 mm x 14 mm . In principle the detector could be extended in width, up to around 80 pixels, limited only by the area of the 4 in . wafer . Each pixel is connected to metal routing at a number of points along its diameter. This reduces the series resistance that collected charge has to pass through before it reaches the metal . The implant sheet resistance is expected to be several hundred St/O, so this is an important consideration for low noise readout . In future designs, an additional level of metal will contact the implant at several points over the whole of its surface area, to further reduce the resistance. The width of metal routing is 8 [,m which results in a low series resistance (less than 50 S2 for routing covering 20 mm) . Thicker tracks are not used as they would II . CONTRIBUTED PAPERS
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Fig. 3. One half of large pixel array with routing.
have a higher capacitance to pixels over which they have to cross. The capacitance values are comparable with interstrip capacitances for strip detectors, but it must be remembered that in the pixel array, there is cross-talk between pixels which are -widely separated . The pixels connect to bond pads arranged in two rows at pitches of 88 pm. The Microplex readout chips (MX2) are bonded onto these pads and are placed side by side at both ends of the detector such that four chips
can read out the one array of 512 elements . The operation of the Microplex chip is discussed in ref. [2]. The small array consists of 256 pixels in an area roughly 1 .6 mm X 1 .6 mm, as shown in fig. 4. The spacing between the hexagonal implants is chosen to be 12 p m which gives low interpixel capacitance and good uniformity of charge collection over the whole active area . In order to route out the pixels, narrow tracks of 5 Wm width and spacing are required. The same bond
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Fig. 4. Small pixel array with routing. pads are used as in the large array, but in this case it is not the intention to place detectors side by side . The 6 x 5 mm area required for the bonding and routing contains a large dead area where no pixels are located, as shown in fig. 5. Both detectors have guard rings surrounding the pixels arrays in order to prevent leakage currents from the sawn edges of the silicon reaching the detector . The rings are biased separately from the pixels to allow the optimum bias to be found such that edge leakage is removed without upsetting the charge collection of outer pixels .
3. Description of the diode process Work on this high resistivity silicon process has only recently started and the process is being developed in parallel with the detector structures . Prior to this work the process was being used to investigate fabrication of silicon strip detectors. These were the simplest form of detectors that could be used to test the characteristics of process in this type of application . This work has continued on the present wafers to assess the effect of process changes and to look at process uniformity. Three 5 in . masks are used in the process, with an II . CONTRIBUTED PAPERS
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S. L. Thomas, P. Seller / A silicon pixel detector with routing
Fig . 5 . Small array with routing and bond pads . optional passivation mask, and have been made at the Electron Beam Lithography Facility at The Rutherford Appleton Laboratory . Mask 1 is used to define cuts through the 2000 .4 thermally grown field oxide. The 4 in . wafers are then oxidized to produce 200 i1 thin oxide over the cut active areas . Boron is implanted through the thin oxide which is then activated to produce the p-type pixel elements . Mask 2 defines the contact cuts through the oxide to the underlying silicon . For some devices contact to the substrate as well as the p-implants will be needed. As
the field oxide mask defines the p-implants, contacts to the substrate will necessarily have to be through thick oxide. The resultant over etching around the thin oxide contact holes may affect the p-type silicon and this is being investigated. Mask 3 defines the single metal layer used for routing and contact. A few percent silicon is dissolved in the aluminium which is sputtered onto the wafer. This is a common precaution to stop aluminium dissolving silicon and creating diode shorts . Although this metal should be patterned using ion etching, careful wet etch-
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S.L . Thomas, P. Seller /A silicon pixel detector with routing
ing is used to avoid a potential problem . Ion etching does not 100% specifically etch metal in preference to oxide. A problem has been observed where the thin oxide covering the edges of the diodes can be etched away causing large leakage currents . The wet etch process is sufficiently specific not to cause this problem . Future developments of the process will be aimed at allowing an extra metal routing layer to be fabricated. This will make building ac coupled detectors feasible. Also the work on field oxide transistors and local area conditioning will be used to bias the pixels and make active devices .
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l'OI' VIEW
DRAIN (ONI'ACT
4 . Design of test structures Previous runs of the process have emphasised the need for comprehensive test structures to monitor process parameters . The layout includes capacitors, resistors and diodes in a variety of sizes up to 5 mm square . Two types of 5 mm MOS capacitors have been fabricated ; one consisting of metal over implant (with thin oxide) and the other over substrate (thick oxide). These will give information on the two surface conditions . Smaller 1 mm square capacitors have separate connections to the implant and substrate so that biases can be applied . Van der Pauw structures are incorporated to measure sheet resistances . The 5 mm square diodes should be large enough for accurate measurements of leakage currents, and will additionally give an indication of the yield of devices which have large metal to implant contact windows . If the implant mask were to have dark areas on it due to small defects, then there could be a direct connection from the substrate to metal at these points, as the implant would be missing . The leakage current from these pin-hole contacts will be proportional to their area, so an estimate of area can be made. A direct metal to substrate contact of 5 mm square has been included to facilitate this estimate . The smaller diodes and the pixels themselves will not suffer from pin-hole shorts as the area of the contact window is much smaller. In addition to the process monitoring structures, a variety of active devices have been laid out. Metal gate field-oxide FETs with a wide range of gate dimensions will give information on the punchthrough characteristics of high resistivity devices . Substrate connections are made on the top surface of the silicon near to the devices, in addition to the back surface connection, to provide more control over the depletion regions. The intention is to bias the devices such that both sourceto-substrate and drain-to-substrate diodes are strongly reverse biased . If drain-induced lowering of the source potential barrier can be reduced, then punchthrough will be minimised even for short gates. Once transistor parameters have been extracted from the present test
Fig. 6 . Metal gate FET with pixel as source. structures, designs of simple amplifiers or switching circuits can be considered for future layouts. Particular importance has been given to understanding the behaviour of transistors which are in close proximity to a fully depleted pixel . In this case, the top surface substrate connections must not disrupt the charge collection of the pixel, so it may be more difficult to prevent punchthrough. In fig . 6, a metal gate FET uses the pixel implant as its source and has no additional substrate connection . If the FET works as a switch, then it could be used as the basis of multiplexed readout in future designs (where additional metal layers will be available for the routing of x-y address lines). If a punchthrough current cannot be prevented, the device can be used in a different application, as a bias resistor for pixels which are ac coupled to the readout electronics . The effective resistance can be controlled by the gate voltage, and the need for large polysilicon resistors is obviated . Thus large ac pixel arrays become practical, provided an extra metal layer is available . In the present design, ac pixels are tested individually to avoid the routing problems associated with arrays . 5 . Simulations of test structures Simulations have been carried out in order to estimate capacitances between routing and pixels, and also to investigate the behaviour of active devices . A number of modelling programs are available which can solve the potential distributions in silicon, but the assumptions and simplifications made by the programs vary widely. Care has to be taken to ensure that models are applicaII . CONTRIBUTED PAPERS
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Fig. 7. Equipotentials around two implants. Implants at 0 V, back surface at 20 V, contours at 0.1 V steps. ble in each case before meaningful results can be obtained . The test structures were laid out with this in mind, such that measurements will allow the testing of simulations under a wide range of conditions . In the case where the silicon is fully depleted, the calculation of potentials is straightforward as a uniform charge density can be assumed (equal to the doping density) and the solution of Poisson's equation readily found [3]. In the example of fig. 7, the equipotentials are plotted around two p-implants under reverse bias. The potential along the surface (fig. 8) shows a characteristic parabolic potential barrier between the strips . In order to evaluate capacitance, the potential solution is found with the charge density set to zero . The stored energy (and hence capacitance) is obtained by integration over the appropriate regions. For simple geometries, the results can be compared with analytical (conformal mapping) solutions and the accuracy of the modelling evaluated. In fig. 9, a voltage has been applied between two 5 lint strips at 5 pm spacing. Boundary conditions are set at a suitably large distance from the strips such that the fields near the strips are not disturbed. Provided the fields are low at the Potential (V)
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Fig. 8. Potential along surface between implants .
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boundaries, the stored energy will give a good estimate of the capacitance . In this example, the analytical solution is about 4% higher than the estimate . In the case where there are regions of nondepleted silicon, an iterative solution of Poisson's equation is required . The charge density at any point now depends on the shift in Fermi level, so must be recalculated at each stage until convergence is obtained . A program has been written [4] to solve these off-state problems and is currently being developed to handle more complex geometries. In real semiconductor devices, the flow of current can change the potential and carrier densities in the silicon. The above off-state solutions can be used only when the currents are very small (such as leakage currents) when the perturbation of the field is negligible. An on-state solution of FET structures is available from MINIMOS [5], although the accuracy of its modelling is expected to be low for high-resistivity silicon. (A number of default material parameters are likely to need adjustment, and the mesh becomes rather coarse near the surface when large depletion regions exist.) MINIMOS solutions are shown in figs . 10-13 for a metal gate FET which could be used in the readout of pixels in future designs. It is important to know how punchthrough will affect its switching characteristics and whether the substrate bias will improve its performance. In order to bring MINIMOS closer to its normal regime of operation the substrate doping has been set 100 times higher than the actual doping. The solutions for a gate length of 1 l.Lm illustrate behaviour which would be expected in a real device of 10 lint length (as depletion depths depend inversely on the square root of doping density) . In these plots, the x axis is along the surface and the y axis is into the silicon. Potential (in V) and log (hole concentration/cm3) are
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Fig. 10. Potential distribution and hole concentration for FET. Substrate at 0 V, gate at 0 V . on the z axis . The gate extends from x = 0 to x = 1 .0 Wm with a gate oxide thickness of 2000 f1 (not shown in the plots) . In all the examples the source is at 0 V and the drain is at - 3 V . In the absence of the back surface bias (fig . 10), a high hole concentration under the gate is observed . There is only a small potential barrier between source and drain, so a significant punchthrough current can flow by diffusion. Increasing the gate voltage has little effect on the current (fig. 11) as the current extends several microns into the bulk where the gate has little effect . In fig . 12, the increase in substrate reverse bias reduces the depth of punchthrough to 0 .8 W m, as holes are swept towards the surface by the applied field . When the gate voltage is increased (fig . 13) the device is switched off. There is now a large barrier to the diffusion current, both along the surface (due to the gate) and in the bulk (due to the substrate reverse bias) . It can be seen that the device would be useful as a switch or amplifier, provided the back surface is maintained at a large positive voltage. An important consideration for future designs involving ac coupling is the behaviour of p-implants which
are allowed to float in potential close to a biased implant. Floating strips have already been incorporated into designs of strip detectors where the strips are intended to improve the linearity of capacitive charge division . Measurements on these strips have shown that large voltage drops can occur across small distances at the surface (typically, 5 V across 12 ~tm) when a large back surface bias is applied. A static off-state solution of Poisson's equation predicts voltages of this order, but this technique ignores the floating p-n junction . A better technique is to regard the biased and floating implants as the drain and source of a transistor which has no gate . For a given source potential, Vds, there will be two components of source current. Firstly, a component of the leakage current from the bulk silicon will be collected at the source . This current will increase if Vds decreases, as more electric field lines will end on the source . Secondly, there is the punchthrough diffusion current from source to drain . If Vds decreases, this current will decrease. At some value of Vds the two components of current will become equal (and opposite) and the source will reach a steady floating voltage . This voltage will depend on the relative sizes of punchthrough
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Fig . 11 . Potential distribution and hole concentration for FET . Substrate at 0 V, gate at 4 V. 11 . CONTRIBUTED PAPERS
S. L. Thomas, P. Seller / A silicon pixel detector with routing
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Fig. 12 . Potential distribution and hole concentration for FET. Substrate at 20 V, gate at 0 V.
and leakage currents . For example, if large leakages are present the floating voltage will be high, and the potential distribution will be close to the that obtained for the off-state.
Further work is needed to understand the punch-
through characteristics in the absence of the gate . It is
clear that the substrate bias will have a significant effect as holes will be swept towards the top surface by the large applied field. The volume over which punchthrough occurs will reduce, as was observed for the
MOSFETs in figs . 10-13 . In addition, the potential barrier along the surface between source and drain may be increased if a suitable overbias is applied. A potential distribution, similar to that shown in fig. 7, will add linearly to that already present in the silicon if a bias voltage above that required for full depletion is applied.
The increased parabolic barrier between source and drain will tend to sweep holes towards the implants, reducing the punchthrough current.
It was mentioned earlier that top surface connections to the substrate have been made at points around certain devices. It will be possible to locally modify the
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fields in the substrate in order to ensure that a large potential barrier is maintained around source regions, to reduce the diffusion current. The additional control over the potential distribution should allow the devices to work under a wider range of operating conditions .
6. Conclusions It has been demonstrated that pixel arrays can be laid out using a simple three mask process. The use of a VLSI readout chip has simplified the routing such that large areas of silicon can be covered with pixels . Ideas for future techniques of readout have been discussed,
and the need for more detailed simulations has been emphasised . The development of new programs must
reflect the particular demands of high resistivity device simulation, and will need to be linked to the results from test structures . Future pixel layouts will include ac
coupled pixel arrays and multiplexed arrays, when additional metal routing becomes available.
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Fig. 13. Potential distribution and hole concentration for FET. Substrate at 20 V, gate at 4 V.
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Acknowledgements
Questions
The authors would like to thank G . Ensell at Southampton University and G . Hall at Imperial College for their work on the development of the diode process, and J . Ellison at Imperial College for contributions to the test structures.
Q . (E. Heijne, CERN) : Why do you use metal gate transistors? Are such transistors satisfactory? A . : There is no polysilicon available in the processing . We will have to make different devices for high performance electronics .
References [1] H . Spieler, Semiconductor Detector and Integrated Electronics Development (SSC Detector R&D proposal) LBL (July 1987) . [2] P . Seller, P .P . Allport and M . Tyndel, IEEE Trans . Nucl . Sci . NS-35 (1) (1988) 176 . [3] C .S. Biddlecome, N .S. Diserens and C .P . Riley, PE2D User Guide. 2d/axisymmetric static and dynamic electromagnetic analysis package (Version 6) RAL 81089. [4] C. Hunt and C. Greenough, Examples in the use of the Finite Element Library : Non-linear Electrostatic Solution, RAL 85113 . [5] S . Selberherr, A . Schutz and H .W . Potzl, IEEE Trans . Electron Devices ED-27 (1980) 1540 .
Q . (S . Audet, TU Delft) : Is there no problem with parasitic capacitances related to the metal lines which run over the other pixels? A . : Yes, this will be one of the main problems .
Q. (E .R. Fossum, Columbia) : Why are the pixels hexagonal? Comment (P. Seller, RAL) : We wanted to investigate how charge is shared between multiple pixels . In a hexagonal array in any point one may share at most between three nodes, which is simpler than sharing between four nodes . Also reconstruction afterwards should be easier, and finally, hexagons are easier to route .
II . CONTRIBUTED PAPERS