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A simple dead-time compensation strategy for grid-connected voltage-sourced converters semiconductor switches
Electric Power Systems Research 174 (2019) 105853
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A simple dead-time compensation strategy for grid-connected voltagesourced converters semiconductor switches
T
Gabriel A. Foglia,b, , Rodolfo L. Vallea, Pedro M. de Almeidaa, Pedro G. Barbosaa ⁎
a b
Electrical Engineering Program, Federal University of Juiz de For a, Juiz de Fora, Brazil Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil
ARTICLE INFO
ABSTRACT
Keywords: Dead-time compensation strategy Time-delay compensation scheme Average value compensation Voltage sourced converter Grid-connected power converter
This paper presents a simple strategy to compensate the distorted currents synthesized by a grid-connected voltage source converter due to dead-time, turn-on and turn-off time delays of the semiconductor switches. The algorithm consider only the polarity of the fundamental component of the currents flowing through the converter terminals and the values of the time delays and voltage drops supplied by the manufacturers to the semiconductors devices. The presented compensation belongs to the group classified as average value compensation technique methodology since it does not change the pulse pattern of the converter's semiconductor switches. A simplified mathematical description of the effects caused by these unwanted time delays is presented and used to derive a correction factor to be added, in real time, to the converter output controller in order to compensate for its terminal voltages. The asymptotic stability and robustness of the proposed methodology is investigated redrawing the converter current controllers, designed in dq-reference frame, as proportional-resonant ones, in the abc coordinates, and adding the effect of the compensating signal in the feedback loop using the concept of describing function. In addition, the minimum value of the DC bus voltage necessary is also evaluated to ensure the operation of the converter in the linear modulation region when the compensation algorithm is active. Experimental results are presented to validate the theoretical analysis and to demonstrate the effectiveness of the proposed strategy for three different operation conditions of a grid-connected converter: (i) active power injection; (ii) active power consumption and (iii) reactive power support.
1. Introduction Voltage sourced converters (VSC) have been widely used in industrial and grid-connected applications. Kerkman et al. [1] demonstrated how some of non-linearities such as semiconductor switches dead-time, time-delays of the gate drives, as well as the voltage drops of switches and diodes, distort the currents synthesized by the VSC. These non-linear characteristics have its effects increased when the converters are driven by high frequency pulse width modulation (PWM) techniques. The dead-time is the delay during a VSC semiconductor switch activation, used to guarantee that the complementary switch of the same branch is fully deactivated. Different compensation methods have been proposed in literature to reduce or mitigate the effects of the dead-time [1–3]. They can be classified according to the way that the converter's output voltage waveforms compensation is performed. Direct methods model the non–linearities of VSC semiconductor switches. Thus, the mathematical understanding of how the dead-time affects the output
⁎
voltages and currents allows changing the pulse-pattern in order to compensate for undesired effects [4,5]. Lewicki [3] divided the direct compensation methods into two groups. The first one was named as pulse-based compensation strategies. In this group, the gate-pulses of the converters’ semiconductors have its commutation instants changed to compensate the dead-time and control delays effects. Abronzini et al. [6] proposed a steady-state compensation technique for a current-controlled grid-connected converter. Their algorithm is based on step-by-step voltage compensation according to the current error evaluated within each control interval. Despite of low computational effort, the aforementioned compensation method has the disadvantage of only be effective for slow-dynamic applications (e.g. photovoltaic generation systems). Another pulsebased compensation strategy was proposed by Lee and Ahn [4]. The authors modify the switching patterns of the space vector modulation (SVM), according to the converter's output current polarity, compensating the dead-time effect. Modifying only the SVM switching intervals is a simple strategy without any additional circuitry or sensor. The main
Corresponding author at: Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil. E-mail address: [email protected] (G.A. Fogli).
https://doi.org/10.1016/j.epsr.2019.04.031 Received 24 July 2018; Received in revised form 7 March 2019; Accepted 25 April 2019 Available online 17 May 2019 0378-7796/ © 2019 Elsevier B.V. All rights reserved.
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disadvantage it is the reduction of the modulation linear region. Consequently the system may operate in the overmodulation region, injecting current harmonics into the grid. Besides, this strategy only presented satisfactory results under open-loop tests. The second group of direct compensating methods gather the strategies in which the voltage error due to the dead-time is compensated by the addition of a factor in the reference voltage signal [7–9]. These methods are named volt-second or average value compensation. Zhang and Xu [10] describes the effects of snubber and parasitic capacitance on the switching patterns of a VSC. The voltage error due to dead-time is compensated taking into account the snubber and parasitic capacitance of the switch. The method is effective, in steady-state, if specific parameters, such as parasitic capacitances, are known. On the other hand there are the indirect compensation methods. These methods do not focus on the cause of the voltage distortions but on their consequences. An error between the reference and the output voltage or current is fed back to dedicated controllers whose outputs regulate the output signals to minimize the harmonics content and indirectly eliminating the dead–time effects. The studies presented in [11–13] can be included in this group. They are also called feedback compensation strategies. Tang and Akin [14] propose the use of revised repetitive controller (RRC) to reduce current harmonics caused by dead-time, improving the efficiency in permanent-magnet synchronous motor (PMSM) drives. Despite of good performance in transient and steady states, the additional harmonic compensation structures increases the complexity of the design and the computational effort of the whole control algorithm. This work presents a simple and effective direct method to compensate the dead-time and time-delays of the VSC switches based on the modelling of these non-linear effects. The compensation strategy uses the polarity of the converter's output currents to generate a compensation signal to be added to the reference signals supplied by current controllers. A stability analysis through description function due to nonlinear system is developed to demonstrate the asymptotically stability and robustness. The minimum value of the DC voltage bus required to guarantee that the converter operates in the linear region of the PWM modulation is also presented. The lower computational effort and the plug-in characteristic of the proposed scheme makes its use possible together with any type of controller, without the need of any additional hardware or sensors. Experimental results are presented to validate the proposed strategy.
fictitious dc-centre tap, for a positive current flow is given by:
vao =
Vdc 2
Vce,
when S1 is on
(1)
and,
Vdc 2
vao =
Vd,
when S4 is on
(2)
where the Vdc is the total dc-voltage, Vce is the semiconductor switch voltage drop, Vd is the diode voltage drop. On the other hand, considering that the current polarity is negative, the phase “a” terminal voltage can be written as follows:
vao =
Vdc + Vd, 2
when S1 is on
(3)
and,
vao =
Vdc + Vce, 2
when S4 is on
(4)
Fig. 2 shows the waveforms for the phase “a” when a real switching pattern is considered. The gate signals S1 and S4 were drawn for two consecutive switching periods Ts [15]. The effect of dead-time (tΔ) is illustrated by the dashed rectangles in Fig. 2(a) and (b). It is also possible to evaluate how tΔ, the turn-on (ton) and turn-off (toff) time–delays affect the output voltage vao .1 The ton time is composed by the turn-on delay time (td(on)), the current rise time (tri) and the voltage fall time (tfv), while the toff is given by the turn-off delay time (td(off)) plus the voltage rise-time (trv) plus the current fall time (tfi) [16]. It is clear from Fig. 2(c) that when ia > 0, the voltage drops Vce and Vd reduce the “average instantaneous value”2 of vao when S1 and S4 are high, respectively. The voltage vao also has its averaged instantaneous value reduced during the (tΔ + ton) period and increased during the toff period. On the other hand, when ia is negative, vao has its averaged instantaneous value increased by the voltage drops Vce and Vd when S1 and S4 are low, as well as its average value is increased and decreased during the (tΔ + ton) and toff periods as shown in Fig. 2(d). Based on Fig. 2, the reduction of the VSC output voltage due to the aforementioned time-delays can be estimated as follows,
V=
t + ton 2Ts
toff
(Vdc
Vce + Vd ).
(5)
where ΔV is the output voltage reduction averaged value for two consecutive switching periods. Although the modelling of the dead-time was performed for the phase “a”, the methodology presented here can be easily extend to the other legs of the converter. Thus, assuming that the VSC synthesize sinusoidal currents at its terminals, the three-phase distortion voltages due the time delays, with respect to the dc-centre tap of Fig. 1, are given by:
2. Mathematical modelling Fig. 1 shows a schematic diagram of the three-phase VSC connected to the ac electric network through a three-phase first-order low-pass harmonic filter. Where Rf and Lf are the resistance and inductance per phase, respectively. The input terminals of the converter is connected to a generic dc-source. The resistance Rp models the losses and self-discharge of the converter's dc-capacitor. The power on the dc-side can be provided by any conventional or alternative energy source (e.g. wind, photovoltaic, micro-turbine, etc.) which requires an inverter as the interface between the primary energy source and the grid. The dc capacitor is shown split into two parts to make the theoretical analysis easier to understand. This fictitious point is not accessible in most of commercial and experimental prototypes. Ideally, the semiconductor switches of the same leg of the VSC are commutated in a complementary way. It means that, when the upper semiconductor is switched on, the lower one is switched off and viceversa. However, in real applications, there is a short period of time, called dead-time, in which both switches are kept open. The dead-time prevents the short-circuit of the converter dc-side capacitor. During this period, the current flows through the lower or upper diode of the VSC leg in accordance with the current polarity. If it is positive, the current flows through the lower diode, otherwise it flows through the upper one. Thus, the phase “a” terminal voltage vao , with respect to the
v ko, =
V sign (ik ),
(6)
where sign (·) represents the signal function and k {a, b , c } . Fig. 3(a)–(c) show the three-phase distortion voltages according to the output current polarity. Notice that the voltages vao, , v bo, and vco, are π rad phase-lagged with respect to the phase currents, respectively. The output currents were plotted normalized in relation to the VSC rated value. The high frequency harmonics due to commutation were neglected. That is, it was considered that the output filter effectively attenuate those harmonics. The previous voltage waveforms are similar to those from a sixpulse inverter. Thus, assuming a balanced operation, the phase-toneutral voltages are given by [16], 1
The dead-time tΔ should be chosen greater than ton and toff. The terminology average instantaneous value is used here to denote the average value calculated during one switching period Ts. 2
2
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Fig. 1. Three-phase grid-connected VSC system under study.
Fig. 2. Switching waveforms for phase “a”: (a) S1 gate signal, (b) S4 gate signal, (c) output voltage vao for ia > 0 and, (d) output voltage vao for ia < 0.
v kn, =
2 v ko, 3
1 v 3
o,
1 vmo, 3
Ih, =
(7)
{a, b , c } and ℓ ≠ k, m {a , b , c} and where k {a, b , c } , m ≠ ℓ ≠ k. Fig. 4 shows the phase-to-neutral distortion voltage for the phase “a” of the converter. Similarly voltage waveforms can be drawn for phases “b” and “c” by lagging van, of 2π/3 rad and 4π/3 rad, respectively. The characteristic harmonics of van, are given by 6h ± 1, while their amplitude can be calculated by expanding the voltage waveform depicted in Fig. 4 on its Fourier series as shown below,
Vˆh, =
4 3 V 3h
cos h
6
cos h
5 6
,
Vh, Zf , h
(9)
where |Zf , h | = Rf2 + (h Lf ) 2 and Zf ,h = tan 1 (h Lf / Rf ) are the interface low-pass filter magnitude and phase, respectively; ω is the system fundamental frequency. The analysis of (9) shows that the magnitude of the harmonic current Ih,Δ decreases as the harmonic order increases. The reduction occurs not only due the harmonic voltage reduction, but also by the increase of the interface filter impedance. Despite of the amplitude reduction of high order harmonics, the fifth and seventh order harmonics may not be neglected, depending on the switching frequency. Therefore, to reduce the output current distortion a compensation strategy is needed.
(8)
3. Dead-time compensation strategy
where Vˆh, is the peak-value of phase-to-neutral distortion voltage and h = 1, 2, 3, …. Considering the grid-voltages , vb and vc in Fig. 1 are balanced and free of harmonics, the distortion voltages van, , v bn, and vcn, forces an harmonic current flow through the interface filter. The rms value of each harmonic current component, for h ≠ 1, is given by,
In order to overcome the undesired effects of the dead-time, turn-on and turn-off time-delays in a grid-connected power converter, a simple control strategy is proposed. The compensation scheme is based on the cancellation of the distortion voltages caused by the aforementioned 3
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Fig. 3. Three-phase VSC distortion voltages and output currents: (a) phase “a”, (b) phase “b”, (c) phase “c”.
non-linearities by using its estimation modelled by (5) and (6). Where the measured value of Vdc is used for on-line calculations of ΔV. This strategy reduces the influence of Vdc variations on the compensation [13]. Fig. 5 shows the block diagram used to estimate in real time the distortion voltages caused by tΔ, ton and toff. Three notch filters N(s) (Appendix A) are used to extract the fundamental component of ia, ib and ic. This structure prevents problems regarding the signal function when the output currents have large ripple or phase shifted due to harmonics. Since the centre tap of the dc bus is not connected to the neutral point of electric system, the triplen harmonics of the VSC terminal voltages will be cancelled. Thus the compensation algorithm may use the terminal distorted voltages vao, , v bo, and vco, instead of the phase-to-neutral voltages van, , v bn, and vcn, . This choice reduces the computation effort of the algorithm. Fig. 6 shows the complete control block diagram of the grid-connected power converter. Two PI controllers, designed in synchronous reference frame, regulate the currents synthesized by the VSC [17]. This strategy is widely used in the literature to control the active and reactive powers flow at the terminals of grid-connected converters through the direct id and quadrature iq current components, respectively. The PLL circuit supplies the angle θ used to transform the
voltages and currents to synchronous reference frame [13]. Since the time-delays reduce the output voltages of the converter, the distortion voltages vao, , v bo, and vco, , estimated by the control algorithm shown in Fig. 5, are inverted and transformed to αβ-coordinates before being added to the reference voltages of the current controllers, v * . Then, the
resulting voltages are divided by 3 ( 2dc ) to generate the modulation signals mαβ that are sent to the space vector modulation (SVM) block. The factor (2/ 3 ) was associated with the Vdc/2 voltage to normalize mαβ, avoiding the over-modulation of control signals used generate the pulse pattern of the converter switches. Although the SVM has been used herein to control the VSC, other modulation techniques can be employed without modifications and loss of effectiveness. The time-delays tΔ, ton = (td (on) + tri + t fv ) and toff = (td (off) + trv + t fi) used in Fig. 5, as well as the voltage drops Vce and Vd, are obtained from the manufacturer data sheets of the drive circuits and the semiconductor switches, respectively. The analysis of (5) shows that the weight of tΔ, ton and toff times increases under higher frequencies operation, that is, small switching times Ts. On the other hand, the influence of Vce and Vd may be neglected in (5) due to their lower values in comparison to Vdc. Nevertheless a boost in the DC bus voltage may be require to avoid over-modulation as a result of the additional ΔV voltage generated by the compensation 2
V
Fig. 4. Phase-to-neutral voltage for phase “a” of the VSC.
4
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Fig. 5. Block diagram of algorithm used to estimate the distortion voltages.
method. Then, considering that the SVM strategy is used to generate the converter switching pattern, the following relation yields:
2 Vdc Vˆ1,max = 3 2 where Vˆ1,max
fundamental component peak value. The voltage given in (10) corresponds to the length of a rotating vector with amplitude equal to the radius of the circumference inscribed in the hexagon, formed by the switching converter voltages in the αβ-plane [15]. Thus, replacing h by 1 in (5) and substituting the result in (10) yields:
(10)
is the converter's output phase-to-neutral voltage
Fig. 6. Grid-connected converter with current controller in synchronous reference frame and time-delays compensation. 5
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Fig. 7. Layout of experimental setup: (1) DSP; (2) conditioning board; (3) buffer board; (4) SKHI22A H4 drivers; (5) Voltage-sourced converter (SKS50FB6U +B6CI32V12); (6) Voltage sensors (LV 25P); (7) Current sensors (HAS 50-S.
Vdc =
4 3
V
Table 2 VSC semiconductor parameters.
(11)
where ΔVdc is the value that the DC voltage level should be increased to avoid over-modulation when the compensation algorithm is used. 4. Experimental validation Fig. 7 shows the picture of the experimental set-up of the gridconnected converter built in laboratory to validate the proposed compensation strategy. The VSC was constructed using three Semikron modules SKM100GB128D driven by SKHI22A dual-hybrid IGBT driver. The control system was implemented in a TMS320F28335 DSP from Texas Instruments. Tables 1 and 2 show the parameters of the system and VSC, respectively. Fig. 8 shows the distortion voltages waveforms in the αβ-reference frame. These signals were generated by the compensating algorithm implemented in the DSP. Notice that the distortion voltages have waveforms in accordance with the theoretical analysis previously present. The use of different dc-bus voltage values, converter switching frequency, among other parameters only changes the amplitude of v , v , , not its waveform. The phase “a” modulation index considering the operation of the VSC without the dead-time compensation strategy is depicted in Fig. 9. The reference signals for the converter current controllers are id* = 7.0 A and iq* = 0 A . This condition implies in approximately 1.33 kW and 0 kvar of active and reactive powers at the converter's terminals. The modulation index is a control signal that varies slowly, compared with switching-frequency triangular waveform. It is the output controller signal used to determine the switching pattern [18].
Symbol
Value
AC rms phase-to-neutral voltage Fundamental frequency Interface filter inductance Interface filter resistance DC-link voltage DC-link capacitance Sampling frequency
Van f1 Lf Rf Vdc Ceq fs
127 V 60 Hz 1.25 mH 0.33 Ω 420 V 4700 μF 20 kHz
Symbol
Value
Dead-time Turn-on time-delay Turn-off time-delay Switch voltage-drop Diode voltage-drop
tΔ ton toff Vce Vd
4.3 μs 1.0 μs 1.0 μs 1.85 V 2.2 V
Commonly, for grid-connected applications, the magnitude and phase of inverter output voltage must be changed in accordance with the desired active and reactive power at its terminals. This is performed by changing the modulation signal. The modulation index is used to modulate the switch duty ratio and has a frequency f1, which is the desired fundamental frequency of the inverter voltage output. Fig. 10 shows the phase “a” modulation index for the operation modes given in Table 3, with the proposed dead-time compensation algorithm. Notice that the modulation index waveforms change according to the phase of the converter's output current, which is directly related to the operation mode. The modulation index has its peak decreased in Fig. 10(a). This behaviour can be explained by the fact the reference voltages v * are in phase with the voltages v , when the VSC drains active power from the grid (i.e. rectifier operation mode). On the other hand, during the active power supplying mode, Fig. 10(b), the voltages v * and v , are phase-shifted by π rad. The comparison between Fig. 10(a) and (b) shows that the modulation index has its amplitude increased in the second case. This condition should carefully evaluated by the designer to avoid over-modulation according to the following analysis. Substituting the phase-to-neutral peak voltage value taken from Table 1 into (10), it returns the minimum DC bus voltage for the SVM linear operation, which is 311 V. On the other hand, substituting the parameters given in Table 2 into (5), and assuming a switching frequency of 20 kHz, it results in ΔV = 18.08 V. Replacing the previous value for the distortion voltage in (11) it gives ΔVdc = 39.87 V. Then, the minimum DC bus voltage level, when the proposed compensation method is used, must be (Vdc + ΔVdc) = 350.87 V. Finally, considering a safety factor of 20% to compensate for voltage drops in the interface filter, as well as to avoid over-modulation during transients, the converter DC bus voltage was chosen equal to 420 V.
Table 1 System parameters. Parameter
Parameter
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Fig. 8. Experimental waveforms generated by the dead-time compensation algorithm.
Fig. 9. Phase “a” modulation index for active power injection id* = 7.0 A and iq* = 0 A without dead-time compensation.
Fig. 10. Phase “a” modulation index considering different operation modes for the VSC with dead-time compensation: (a) rectifier operation mode id* = 7.0 A and iq* = 0 A ; (b) active power supply id* = + 7.0 A and iq* = 0 A ; (c) reactive power support id* = 0 A and iq* = 7.0 A ; (d) reactive power support id* = 0 A and iq* = + 7.0 A .
The last two waveforms of Fig. 10 are obtained for the converter supporting reactive power to the mains. Fig. 10(c) and (d) show the modulation indexes for the cases when the reference direct current id* is zero and the reference quadrature current iq* is −7.0 A and +7.0 A, respectively. In order to analyse the switching frequency effects on the output current, Fig. 11 shows the phase “a” current waveform considering three different switching frequencies (10, 20 and 25 kHz). In the left and right columns of Fig. 11 is depicted the current injected into the grid for the operation of the VSC without and with the dead-time compensation, respectively. The reference currents are id* = 7 A and iq* = 0 A. In this operation mode the converter injects approximately 1.33 kW into the electric network. Notice that the synthesized current waveform become more distorted as the switching frequency is
Table 3 Operation modes for time-delays compensation tests. Operation mode Active power drain
Reference currents
Time-delay compensation
7.0 A
Enabled
Active power supply
id* = + 7.0 A iq* = 0 A
Enabled
Reactive power support
id* = 0 A iq* = 7.0 A
Enabled
Reactive power support
id* = 0 A iq* = + 7.0 A
Enabled
id* =
iq* = 0 A
7
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Fig. 11. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 7 A and iq* = 0 A and considering different switching frequencies: (a) without dead–time compensation; (b) with proposed compensation.
Fig. 12. Detail of the dynamic response of dead-time compensation scheme.
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Fig. 13. Frequency spectrum for the operation under 25 kHz switching frequency: (a) before compensation; (b) after compensation.
Fig. 12 shows the transient behaviour of the output current when the proposed algorithm is enabled. This waveform was obtained under a fs = 25 kHz switching frequency operation. The waveform presents a small overcurrent and the dead-time effect is fully compensated in approximately one period after the proposed is enabled. Fig. 13(a) and (b) show the harmonic spectra for the phase “a” current before and after the start of the dead time compensation. Note that the fifth and seventh harmonics have their magnitudes decreased, as expected by the theoretical analysis. The THD is reduced from 14% to 2.67% complying the requirements of IEEE-1547 [19]. Table 4 presents a comparison between the experimental values obtained from Fig. 13(a) and harmonic currents calculated using (9). The small difference between theoretical and experimental results corroborates to the validation of the mathematical model. Experimental results are obtained using a closed-loop current controller. Therefore, its influence should be taken into account during the analysis. Fig. 14 shows the Bode Diagram of the closed-loop current controller, highlighting the attenuation in fifth and seventh harmonic components. These attenuation need to be considered in the harmonic component calculation of the output current. The current controller closed-loop transfer function is designed to behave as a first order dynamic system, as follows
Table 4 Harmonic current based on theoretical analysis and experimental results. Order of harmonic
5th 7th
Magnitude of current Theoreticala (Eq. (9))
Experimental (Fig. 13)
0.94 A 0.36 A
0.91 A 0.33 A
a Values multiplied by attenuation of current closed-loop transfer function given in Fig. 14.
increased. This behaviour is due to the fact that the relative weight of the time-delays increases with the reduction of switching period Ts. From (5), and considering the parameters given in Tables 1 and 2, the distortion voltage ΔV increases from 18.08 V to 22.59 V when the switching frequency goes from 10 kHz to 25 kHz, respectively. The comparison between the left and right plots of Fig. 11 shows that the proposed compensation method improves the waveforms of the current synthesized by the converter, reducing its total harmonic distortion (THD). Nevertheless, although the switching frequency reduction decreases the magnitude of the distortion voltage ΔV, it increases the output current commutation ripple.
Fig. 14. Closed-loop current controller frequency response. 9
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Fig. 15. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 0 A and iq* = 7 A and considering different switching frequencies for the converter: (a) without dead-time compensation; (b) with proposed compensation.
Gi,CL (s ) =
* idq i dq
=
1 , 1 + is
and ωo = 2π60 rad/s. To perform stability analysis the signal function shown in Fig. 17 can be replaced by its describing function Yf(A) = 4/(πA) [21], where A is the amplitude of the input signal. Then, the block diagram can be redraw as shown in Fig. 17b). According to the Nyquist stability analysis there will be limit cycles if the equation
(12)
where τi is the chosen closed-loop time constant. A trade-off between fast response and attenuation characteristics is important when choosing an adequate time constant. Yazdani and Iravani [17] suggest a value between 0.5 ms and 5 ms. In this paper τi was chosen equal to 1.25 ms. Finally, to analyse the proposed compensation effectiveness under different operation modes, the system is tested under active power consumption and reactive power compensation. Figs. 15 and 16 show the phase “a” grid-voltage and the converter output current when the VSC compensates reactive power and drains active, respectively. Again, the results are shown for three different switching frequencies. The comparison between the left and right columns demonstrates that the proposed compensation strategy effectively reduces the output current harmonic distortion caused the time-delays. The stability analysis of the proposed compensation method can be performed redrawing the block diagram of Fig. 6 as shown in Fig. 17(a). The proportional integral controller, originally designed in dq-reference frame, was replaced by an equivalent proportional resonant controller Ci (s ) = kp + ki /(s 2 + o2) in abc–reference frame, as described in [20]. The gains kp = R/τi and ki = L/τi were chosen to guarantee a first-order dynamic behaviour, as shown in (12), for the VSC current closed-loop,
G (j ) =
1 , Yf (A)
(13)
is satisfied. Where
G (j ) = V
H (j ) [1 1 + Ci (j ) H (j )
N (j )].
(14)
The easiest way to solve (13) is to plot both sides of the equation in a complex plane and find the intersection points of the two curves as depicted in Fig. 18. As the curves does not intersect, no limit cycle is expected. Furthermore, as −1/Yf(A) lies completely outside the Nyquist curve the oscillations will vanish [21]. It should be pointed out that the oscillations will disappear regardless of the variations in ΔV. This is due the fact that the relative degree of the transfer function G(s) is two. Limit cycles only appear if the relative degree of the linear system is higher than three. 10
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Fig. 16. Phase “a” grid-voltage (Channel 1) and VSC-current (Channel 3) waveforms for id* = for the converter: (a) without dead-time compensation; (b) with proposed compensation.
12 A and iq* = 0 A and considering different switching frequencies
Fig. 17. (a) Simplified equivalent control block diagram for phase “a”. (b) Simplified equivalent block using describing function.
5. Conclusions
results were present to validate the proposed scheme. A method to refine the compensation voltage can be used. Although, by only using datasheet informations, it is possible to effectively reduce the harmonics currents caused by dead-time effect and voltage drops. An important point is to use the fundamental frequency of current to determine the polarity. Harmonic currents affect the process of estimating the distorting voltages. The use of proposed compensation strategy has the advantage of being independent of the switching frequency. This feature allows operating the converter with higher switching frequencies, limited only by the physical capacity of the semiconductor devices, without compromising the output current quality. As a consequence, smaller output
This work presented a simple and effective dead-time delay compensation for grid-connected converters. Based on lag times and voltage drop effects, it was possible to model the distortion voltage at VSC's terminals. The main idea of compensation strategy proposed here consists of adding the estimated distorting voltage due to the dead-time to the current controller output signal, reducing the undesired effects of the commutation time-delays. The compensation method was tested under different switching frequencies and operation modes: absorbing or supplying active power and supporting positive or negative reactive power. Experimental 11
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Fig. 18. Describing function analysis.
filters can be used, reducing the cost, volume and weight of the system. Further advantages are: independence of the operation mode; independence of control law used to regulate the output currents (plug-in characteristic); short transient and the fact the system's stability is not jeopardized when the compensation loop is added.
Acknowledgements The authors would like to thank the National Council for Scientific and Technological Development (CNPq), the Coordination for the Improvement of Higher Education Personnel (CAPES), the State Funding Agency of Minas Gerais (FAPEMIG), UFMG and UFJF for financial support for the development of this research.
Appendix A. Notch filter transfer function The transfer function of the notch-filter used by the dead-time compensating algorithm to estimate the fundamental frequency of the VSC currents is:
N (s ) =
s2
s 2 + c2 + s Qb +
2 c
(A.1)
where ωc is the cut-off frequency, Q is the quality-factor and ( b / Q ) defines the rejection band width of the filter. Fig. A.19 shows the notch filter frequency response for ωb = 2πfb, fb = 10 Hz, Q = 0.707, ωc = 2πf1 and f1 = 60 Hz.
Fig. A.19. Notch-filter frequency response. 12
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[11] G.A. Fogli, P.M. de Almeida, P.G. Barbosa, Modelling and control of an interface power converter for the operation of small diesel gen-sets in grid-connected and stand-alone modes, Electr. Power Syst. Res. 150 (2017) 177–187. [12] P.M. Almeida, P.G. Barbosa, J.G. Oliveira, J.L. Duarte, P.F. Ribeiro, Digital proportional multi-resonant current controller for improving grid-connected photovoltaic systems, Renew. Energy 76 (2015) 662–669. [13] P.M. de Almeida, J.L. Duarte, P.F. Ribeiro, P.G. Barbosa, Repetitive controller for improving grid-connected photovoltaic systems, IET Power Electron. 7 (2014) 1466–1474. [14] Z. Tang, B. Akin, Suppression of dead-time distortion through revised repetitive controller in PMSM drives, IEEE Trans. Energy Convers. 32 (2017) 918–930. [15] S. Buso, P. Mattavelli, Digital Control in Power Electronics vol. 5, Morgan & Claypool Publishers, 2015. [16] N. Mohan, T.M. Undeland, W.P. Robbins, Power Electronics: Converters, Applications, and Design, 3rd ed., Wiley, 2002. [17] A. Yazdani, R. Iravani, Voltage-Sourced Converters in Power Systems: Modeling, Control, and Applications, John Wiley & Sons, 2010. [18] N. Mohan, T.M. Undeland, Power Electronics: Converters, Applications, and Design, John Wiley & Sons, 2007. [19] IEEE, IEEE Recommended Practice for Interconnecting Distributed Resources with Electric Power Systems Distribution Secondary Networks, IEEE, 2011 Std. 1547.62011. [20] D. Zmood, D. Holmes, G. Bode, Frequency-domain analysis of three-phase linear current regulators, IEEE Trans. Ind. Appl. 37 (2001) 601–610. [21] J.-J.E. Slotine, W. Li, et al., Applied Nonlinear Control vol. 199, Prentice Hall Englewood Cliffs, NJ, 1991.
References [1] R.J. Kerkman, D. Leggate, D.W. Schlegel, C. Winterhalter, Effects of parasitics on the control of voltage source inverters, IEEE Trans. Power Electron. 18 (2003) 140–150. [2] Y. Murai, T. Watanabe, H. Iwasaki, Waveform distortion and correction circuit for PWM inverters with switching lag-times, IEEE Trans. Ind. Appl. IA-23 (1987) 881–886. [3] A. Lewicki, Dead-time effect compensation based on additional phase current measurements, IEEE Trans. Ind. Electron. 62 (2015) 4078–4085. [4] D.H. Lee, J.W. Ahn, A simple and direct dead-time effect compensation scheme in PWM-VSI, IEEE Trans. Ind. Appl. 50 (2014) 3017–3025. [5] P.J. Patel, V. Patel, P.N. Tekwani, Pulse-based dead-time compensation method for selfbalancing space vector pulse width-modulated scheme used in a three-level inverter-fed induction motor drive, IET Power Electron. 4 (2011) 624–631. [6] U. Abronzini, C. Attaianese, M. D’Arpino, M. Di Monaco, G. Tomasso, Steady-state dead-time compensation in VSI, IEEE Trans. Ind. Electron. 63 (2016) 5858–5866. [7] A.R. Munoz, T.A. Lipo, On-line dead-time compensation technique for open-loop PWM-VSI drives, IEEE Trans. Power Electron. 14 (1999) 683–689. [8] S.H. Hwang, J.M. Kim, Dead time compensation method for voltage-fed PWM inverter, IEEE Trans. Energy Convers. 25 (2010) 1–10. [9] M.A. Herran, J.R. Fischer, S.A. Gonzalez, M.G. Judewicz, D.O. Carrica, Adaptive dead-time compensation for grid-connected PWM inverters of single-stage PV systems, IEEE Trans. Power Electron. 28 (2013) 2816–2825. [10] Z. Zhang, L. Xu, Dead-time compensation of inverters considering snubber and parasitic capacitance, IEEE Trans. Power Electron. 29 (2014) 3179–3187.
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Electric Power Systems Research journal homepage: www.elsevier.com/locate/epsr
A simple dead-time compensation strategy for grid-connected voltagesourced converters semiconductor switches
T
Gabriel A. Foglia,b, , Rodolfo L. Vallea, Pedro M. de Almeidaa, Pedro G. Barbosaa ⁎
a b
Electrical Engineering Program, Federal University of Juiz de For a, Juiz de Fora, Brazil Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil
ARTICLE INFO
ABSTRACT
Keywords: Dead-time compensation strategy Time-delay compensation scheme Average value compensation Voltage sourced converter Grid-connected power converter
This paper presents a simple strategy to compensate the distorted currents synthesized by a grid-connected voltage source converter due to dead-time, turn-on and turn-off time delays of the semiconductor switches. The algorithm consider only the polarity of the fundamental component of the currents flowing through the converter terminals and the values of the time delays and voltage drops supplied by the manufacturers to the semiconductors devices. The presented compensation belongs to the group classified as average value compensation technique methodology since it does not change the pulse pattern of the converter's semiconductor switches. A simplified mathematical description of the effects caused by these unwanted time delays is presented and used to derive a correction factor to be added, in real time, to the converter output controller in order to compensate for its terminal voltages. The asymptotic stability and robustness of the proposed methodology is investigated redrawing the converter current controllers, designed in dq-reference frame, as proportional-resonant ones, in the abc coordinates, and adding the effect of the compensating signal in the feedback loop using the concept of describing function. In addition, the minimum value of the DC bus voltage necessary is also evaluated to ensure the operation of the converter in the linear modulation region when the compensation algorithm is active. Experimental results are presented to validate the theoretical analysis and to demonstrate the effectiveness of the proposed strategy for three different operation conditions of a grid-connected converter: (i) active power injection; (ii) active power consumption and (iii) reactive power support.
1. Introduction Voltage sourced converters (VSC) have been widely used in industrial and grid-connected applications. Kerkman et al. [1] demonstrated how some of non-linearities such as semiconductor switches dead-time, time-delays of the gate drives, as well as the voltage drops of switches and diodes, distort the currents synthesized by the VSC. These non-linear characteristics have its effects increased when the converters are driven by high frequency pulse width modulation (PWM) techniques. The dead-time is the delay during a VSC semiconductor switch activation, used to guarantee that the complementary switch of the same branch is fully deactivated. Different compensation methods have been proposed in literature to reduce or mitigate the effects of the dead-time [1–3]. They can be classified according to the way that the converter's output voltage waveforms compensation is performed. Direct methods model the non–linearities of VSC semiconductor switches. Thus, the mathematical understanding of how the dead-time affects the output
⁎
voltages and currents allows changing the pulse-pattern in order to compensate for undesired effects [4,5]. Lewicki [3] divided the direct compensation methods into two groups. The first one was named as pulse-based compensation strategies. In this group, the gate-pulses of the converters’ semiconductors have its commutation instants changed to compensate the dead-time and control delays effects. Abronzini et al. [6] proposed a steady-state compensation technique for a current-controlled grid-connected converter. Their algorithm is based on step-by-step voltage compensation according to the current error evaluated within each control interval. Despite of low computational effort, the aforementioned compensation method has the disadvantage of only be effective for slow-dynamic applications (e.g. photovoltaic generation systems). Another pulsebased compensation strategy was proposed by Lee and Ahn [4]. The authors modify the switching patterns of the space vector modulation (SVM), according to the converter's output current polarity, compensating the dead-time effect. Modifying only the SVM switching intervals is a simple strategy without any additional circuitry or sensor. The main
Corresponding author at: Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil. E-mail address: [email protected] (G.A. Fogli).
https://doi.org/10.1016/j.epsr.2019.04.031 Received 24 July 2018; Received in revised form 7 March 2019; Accepted 25 April 2019 Available online 17 May 2019 0378-7796/ © 2019 Elsevier B.V. All rights reserved.
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disadvantage it is the reduction of the modulation linear region. Consequently the system may operate in the overmodulation region, injecting current harmonics into the grid. Besides, this strategy only presented satisfactory results under open-loop tests. The second group of direct compensating methods gather the strategies in which the voltage error due to the dead-time is compensated by the addition of a factor in the reference voltage signal [7–9]. These methods are named volt-second or average value compensation. Zhang and Xu [10] describes the effects of snubber and parasitic capacitance on the switching patterns of a VSC. The voltage error due to dead-time is compensated taking into account the snubber and parasitic capacitance of the switch. The method is effective, in steady-state, if specific parameters, such as parasitic capacitances, are known. On the other hand there are the indirect compensation methods. These methods do not focus on the cause of the voltage distortions but on their consequences. An error between the reference and the output voltage or current is fed back to dedicated controllers whose outputs regulate the output signals to minimize the harmonics content and indirectly eliminating the dead–time effects. The studies presented in [11–13] can be included in this group. They are also called feedback compensation strategies. Tang and Akin [14] propose the use of revised repetitive controller (RRC) to reduce current harmonics caused by dead-time, improving the efficiency in permanent-magnet synchronous motor (PMSM) drives. Despite of good performance in transient and steady states, the additional harmonic compensation structures increases the complexity of the design and the computational effort of the whole control algorithm. This work presents a simple and effective direct method to compensate the dead-time and time-delays of the VSC switches based on the modelling of these non-linear effects. The compensation strategy uses the polarity of the converter's output currents to generate a compensation signal to be added to the reference signals supplied by current controllers. A stability analysis through description function due to nonlinear system is developed to demonstrate the asymptotically stability and robustness. The minimum value of the DC voltage bus required to guarantee that the converter operates in the linear region of the PWM modulation is also presented. The lower computational effort and the plug-in characteristic of the proposed scheme makes its use possible together with any type of controller, without the need of any additional hardware or sensors. Experimental results are presented to validate the proposed strategy.
fictitious dc-centre tap, for a positive current flow is given by:
vao =
Vdc 2
Vce,
when S1 is on
(1)
and,
Vdc 2
vao =
Vd,
when S4 is on
(2)
where the Vdc is the total dc-voltage, Vce is the semiconductor switch voltage drop, Vd is the diode voltage drop. On the other hand, considering that the current polarity is negative, the phase “a” terminal voltage can be written as follows:
vao =
Vdc + Vd, 2
when S1 is on
(3)
and,
vao =
Vdc + Vce, 2
when S4 is on
(4)
Fig. 2 shows the waveforms for the phase “a” when a real switching pattern is considered. The gate signals S1 and S4 were drawn for two consecutive switching periods Ts [15]. The effect of dead-time (tΔ) is illustrated by the dashed rectangles in Fig. 2(a) and (b). It is also possible to evaluate how tΔ, the turn-on (ton) and turn-off (toff) time–delays affect the output voltage vao .1 The ton time is composed by the turn-on delay time (td(on)), the current rise time (tri) and the voltage fall time (tfv), while the toff is given by the turn-off delay time (td(off)) plus the voltage rise-time (trv) plus the current fall time (tfi) [16]. It is clear from Fig. 2(c) that when ia > 0, the voltage drops Vce and Vd reduce the “average instantaneous value”2 of vao when S1 and S4 are high, respectively. The voltage vao also has its averaged instantaneous value reduced during the (tΔ + ton) period and increased during the toff period. On the other hand, when ia is negative, vao has its averaged instantaneous value increased by the voltage drops Vce and Vd when S1 and S4 are low, as well as its average value is increased and decreased during the (tΔ + ton) and toff periods as shown in Fig. 2(d). Based on Fig. 2, the reduction of the VSC output voltage due to the aforementioned time-delays can be estimated as follows,
V=
t + ton 2Ts
toff
(Vdc
Vce + Vd ).
(5)
where ΔV is the output voltage reduction averaged value for two consecutive switching periods. Although the modelling of the dead-time was performed for the phase “a”, the methodology presented here can be easily extend to the other legs of the converter. Thus, assuming that the VSC synthesize sinusoidal currents at its terminals, the three-phase distortion voltages due the time delays, with respect to the dc-centre tap of Fig. 1, are given by:
2. Mathematical modelling Fig. 1 shows a schematic diagram of the three-phase VSC connected to the ac electric network through a three-phase first-order low-pass harmonic filter. Where Rf and Lf are the resistance and inductance per phase, respectively. The input terminals of the converter is connected to a generic dc-source. The resistance Rp models the losses and self-discharge of the converter's dc-capacitor. The power on the dc-side can be provided by any conventional or alternative energy source (e.g. wind, photovoltaic, micro-turbine, etc.) which requires an inverter as the interface between the primary energy source and the grid. The dc capacitor is shown split into two parts to make the theoretical analysis easier to understand. This fictitious point is not accessible in most of commercial and experimental prototypes. Ideally, the semiconductor switches of the same leg of the VSC are commutated in a complementary way. It means that, when the upper semiconductor is switched on, the lower one is switched off and viceversa. However, in real applications, there is a short period of time, called dead-time, in which both switches are kept open. The dead-time prevents the short-circuit of the converter dc-side capacitor. During this period, the current flows through the lower or upper diode of the VSC leg in accordance with the current polarity. If it is positive, the current flows through the lower diode, otherwise it flows through the upper one. Thus, the phase “a” terminal voltage vao , with respect to the
v ko, =
V sign (ik ),
(6)
where sign (·) represents the signal function and k {a, b , c } . Fig. 3(a)–(c) show the three-phase distortion voltages according to the output current polarity. Notice that the voltages vao, , v bo, and vco, are π rad phase-lagged with respect to the phase currents, respectively. The output currents were plotted normalized in relation to the VSC rated value. The high frequency harmonics due to commutation were neglected. That is, it was considered that the output filter effectively attenuate those harmonics. The previous voltage waveforms are similar to those from a sixpulse inverter. Thus, assuming a balanced operation, the phase-toneutral voltages are given by [16], 1
The dead-time tΔ should be chosen greater than ton and toff. The terminology average instantaneous value is used here to denote the average value calculated during one switching period Ts. 2
2
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Fig. 1. Three-phase grid-connected VSC system under study.
Fig. 2. Switching waveforms for phase “a”: (a) S1 gate signal, (b) S4 gate signal, (c) output voltage vao for ia > 0 and, (d) output voltage vao for ia < 0.
v kn, =
2 v ko, 3
1 v 3
o,
1 vmo, 3
Ih, =
(7)
{a, b , c } and ℓ ≠ k, m {a , b , c} and where k {a, b , c } , m ≠ ℓ ≠ k. Fig. 4 shows the phase-to-neutral distortion voltage for the phase “a” of the converter. Similarly voltage waveforms can be drawn for phases “b” and “c” by lagging van, of 2π/3 rad and 4π/3 rad, respectively. The characteristic harmonics of van, are given by 6h ± 1, while their amplitude can be calculated by expanding the voltage waveform depicted in Fig. 4 on its Fourier series as shown below,
Vˆh, =
4 3 V 3h
cos h
6
cos h
5 6
,
Vh, Zf , h
(9)
where |Zf , h | = Rf2 + (h Lf ) 2 and Zf ,h = tan 1 (h Lf / Rf ) are the interface low-pass filter magnitude and phase, respectively; ω is the system fundamental frequency. The analysis of (9) shows that the magnitude of the harmonic current Ih,Δ decreases as the harmonic order increases. The reduction occurs not only due the harmonic voltage reduction, but also by the increase of the interface filter impedance. Despite of the amplitude reduction of high order harmonics, the fifth and seventh order harmonics may not be neglected, depending on the switching frequency. Therefore, to reduce the output current distortion a compensation strategy is needed.
(8)
3. Dead-time compensation strategy
where Vˆh, is the peak-value of phase-to-neutral distortion voltage and h = 1, 2, 3, …. Considering the grid-voltages , vb and vc in Fig. 1 are balanced and free of harmonics, the distortion voltages van, , v bn, and vcn, forces an harmonic current flow through the interface filter. The rms value of each harmonic current component, for h ≠ 1, is given by,
In order to overcome the undesired effects of the dead-time, turn-on and turn-off time-delays in a grid-connected power converter, a simple control strategy is proposed. The compensation scheme is based on the cancellation of the distortion voltages caused by the aforementioned 3
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Fig. 3. Three-phase VSC distortion voltages and output currents: (a) phase “a”, (b) phase “b”, (c) phase “c”.
non-linearities by using its estimation modelled by (5) and (6). Where the measured value of Vdc is used for on-line calculations of ΔV. This strategy reduces the influence of Vdc variations on the compensation [13]. Fig. 5 shows the block diagram used to estimate in real time the distortion voltages caused by tΔ, ton and toff. Three notch filters N(s) (Appendix A) are used to extract the fundamental component of ia, ib and ic. This structure prevents problems regarding the signal function when the output currents have large ripple or phase shifted due to harmonics. Since the centre tap of the dc bus is not connected to the neutral point of electric system, the triplen harmonics of the VSC terminal voltages will be cancelled. Thus the compensation algorithm may use the terminal distorted voltages vao, , v bo, and vco, instead of the phase-to-neutral voltages van, , v bn, and vcn, . This choice reduces the computation effort of the algorithm. Fig. 6 shows the complete control block diagram of the grid-connected power converter. Two PI controllers, designed in synchronous reference frame, regulate the currents synthesized by the VSC [17]. This strategy is widely used in the literature to control the active and reactive powers flow at the terminals of grid-connected converters through the direct id and quadrature iq current components, respectively. The PLL circuit supplies the angle θ used to transform the
voltages and currents to synchronous reference frame [13]. Since the time-delays reduce the output voltages of the converter, the distortion voltages vao, , v bo, and vco, , estimated by the control algorithm shown in Fig. 5, are inverted and transformed to αβ-coordinates before being added to the reference voltages of the current controllers, v * . Then, the
resulting voltages are divided by 3 ( 2dc ) to generate the modulation signals mαβ that are sent to the space vector modulation (SVM) block. The factor (2/ 3 ) was associated with the Vdc/2 voltage to normalize mαβ, avoiding the over-modulation of control signals used generate the pulse pattern of the converter switches. Although the SVM has been used herein to control the VSC, other modulation techniques can be employed without modifications and loss of effectiveness. The time-delays tΔ, ton = (td (on) + tri + t fv ) and toff = (td (off) + trv + t fi) used in Fig. 5, as well as the voltage drops Vce and Vd, are obtained from the manufacturer data sheets of the drive circuits and the semiconductor switches, respectively. The analysis of (5) shows that the weight of tΔ, ton and toff times increases under higher frequencies operation, that is, small switching times Ts. On the other hand, the influence of Vce and Vd may be neglected in (5) due to their lower values in comparison to Vdc. Nevertheless a boost in the DC bus voltage may be require to avoid over-modulation as a result of the additional ΔV voltage generated by the compensation 2
V
Fig. 4. Phase-to-neutral voltage for phase “a” of the VSC.
4
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Fig. 5. Block diagram of algorithm used to estimate the distortion voltages.
method. Then, considering that the SVM strategy is used to generate the converter switching pattern, the following relation yields:
2 Vdc Vˆ1,max = 3 2 where Vˆ1,max
fundamental component peak value. The voltage given in (10) corresponds to the length of a rotating vector with amplitude equal to the radius of the circumference inscribed in the hexagon, formed by the switching converter voltages in the αβ-plane [15]. Thus, replacing h by 1 in (5) and substituting the result in (10) yields:
(10)
is the converter's output phase-to-neutral voltage
Fig. 6. Grid-connected converter with current controller in synchronous reference frame and time-delays compensation. 5
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Fig. 7. Layout of experimental setup: (1) DSP; (2) conditioning board; (3) buffer board; (4) SKHI22A H4 drivers; (5) Voltage-sourced converter (SKS50FB6U +B6CI32V12); (6) Voltage sensors (LV 25P); (7) Current sensors (HAS 50-S.
Vdc =
4 3
V
Table 2 VSC semiconductor parameters.
(11)
where ΔVdc is the value that the DC voltage level should be increased to avoid over-modulation when the compensation algorithm is used. 4. Experimental validation Fig. 7 shows the picture of the experimental set-up of the gridconnected converter built in laboratory to validate the proposed compensation strategy. The VSC was constructed using three Semikron modules SKM100GB128D driven by SKHI22A dual-hybrid IGBT driver. The control system was implemented in a TMS320F28335 DSP from Texas Instruments. Tables 1 and 2 show the parameters of the system and VSC, respectively. Fig. 8 shows the distortion voltages waveforms in the αβ-reference frame. These signals were generated by the compensating algorithm implemented in the DSP. Notice that the distortion voltages have waveforms in accordance with the theoretical analysis previously present. The use of different dc-bus voltage values, converter switching frequency, among other parameters only changes the amplitude of v , v , , not its waveform. The phase “a” modulation index considering the operation of the VSC without the dead-time compensation strategy is depicted in Fig. 9. The reference signals for the converter current controllers are id* = 7.0 A and iq* = 0 A . This condition implies in approximately 1.33 kW and 0 kvar of active and reactive powers at the converter's terminals. The modulation index is a control signal that varies slowly, compared with switching-frequency triangular waveform. It is the output controller signal used to determine the switching pattern [18].
Symbol
Value
AC rms phase-to-neutral voltage Fundamental frequency Interface filter inductance Interface filter resistance DC-link voltage DC-link capacitance Sampling frequency
Van f1 Lf Rf Vdc Ceq fs
127 V 60 Hz 1.25 mH 0.33 Ω 420 V 4700 μF 20 kHz
Symbol
Value
Dead-time Turn-on time-delay Turn-off time-delay Switch voltage-drop Diode voltage-drop
tΔ ton toff Vce Vd
4.3 μs 1.0 μs 1.0 μs 1.85 V 2.2 V
Commonly, for grid-connected applications, the magnitude and phase of inverter output voltage must be changed in accordance with the desired active and reactive power at its terminals. This is performed by changing the modulation signal. The modulation index is used to modulate the switch duty ratio and has a frequency f1, which is the desired fundamental frequency of the inverter voltage output. Fig. 10 shows the phase “a” modulation index for the operation modes given in Table 3, with the proposed dead-time compensation algorithm. Notice that the modulation index waveforms change according to the phase of the converter's output current, which is directly related to the operation mode. The modulation index has its peak decreased in Fig. 10(a). This behaviour can be explained by the fact the reference voltages v * are in phase with the voltages v , when the VSC drains active power from the grid (i.e. rectifier operation mode). On the other hand, during the active power supplying mode, Fig. 10(b), the voltages v * and v , are phase-shifted by π rad. The comparison between Fig. 10(a) and (b) shows that the modulation index has its amplitude increased in the second case. This condition should carefully evaluated by the designer to avoid over-modulation according to the following analysis. Substituting the phase-to-neutral peak voltage value taken from Table 1 into (10), it returns the minimum DC bus voltage for the SVM linear operation, which is 311 V. On the other hand, substituting the parameters given in Table 2 into (5), and assuming a switching frequency of 20 kHz, it results in ΔV = 18.08 V. Replacing the previous value for the distortion voltage in (11) it gives ΔVdc = 39.87 V. Then, the minimum DC bus voltage level, when the proposed compensation method is used, must be (Vdc + ΔVdc) = 350.87 V. Finally, considering a safety factor of 20% to compensate for voltage drops in the interface filter, as well as to avoid over-modulation during transients, the converter DC bus voltage was chosen equal to 420 V.
Table 1 System parameters. Parameter
Parameter
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Fig. 8. Experimental waveforms generated by the dead-time compensation algorithm.
Fig. 9. Phase “a” modulation index for active power injection id* = 7.0 A and iq* = 0 A without dead-time compensation.
Fig. 10. Phase “a” modulation index considering different operation modes for the VSC with dead-time compensation: (a) rectifier operation mode id* = 7.0 A and iq* = 0 A ; (b) active power supply id* = + 7.0 A and iq* = 0 A ; (c) reactive power support id* = 0 A and iq* = 7.0 A ; (d) reactive power support id* = 0 A and iq* = + 7.0 A .
The last two waveforms of Fig. 10 are obtained for the converter supporting reactive power to the mains. Fig. 10(c) and (d) show the modulation indexes for the cases when the reference direct current id* is zero and the reference quadrature current iq* is −7.0 A and +7.0 A, respectively. In order to analyse the switching frequency effects on the output current, Fig. 11 shows the phase “a” current waveform considering three different switching frequencies (10, 20 and 25 kHz). In the left and right columns of Fig. 11 is depicted the current injected into the grid for the operation of the VSC without and with the dead-time compensation, respectively. The reference currents are id* = 7 A and iq* = 0 A. In this operation mode the converter injects approximately 1.33 kW into the electric network. Notice that the synthesized current waveform become more distorted as the switching frequency is
Table 3 Operation modes for time-delays compensation tests. Operation mode Active power drain
Reference currents
Time-delay compensation
7.0 A
Enabled
Active power supply
id* = + 7.0 A iq* = 0 A
Enabled
Reactive power support
id* = 0 A iq* = 7.0 A
Enabled
Reactive power support
id* = 0 A iq* = + 7.0 A
Enabled
id* =
iq* = 0 A
7
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Fig. 11. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 7 A and iq* = 0 A and considering different switching frequencies: (a) without dead–time compensation; (b) with proposed compensation.
Fig. 12. Detail of the dynamic response of dead-time compensation scheme.
8
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Fig. 13. Frequency spectrum for the operation under 25 kHz switching frequency: (a) before compensation; (b) after compensation.
Fig. 12 shows the transient behaviour of the output current when the proposed algorithm is enabled. This waveform was obtained under a fs = 25 kHz switching frequency operation. The waveform presents a small overcurrent and the dead-time effect is fully compensated in approximately one period after the proposed is enabled. Fig. 13(a) and (b) show the harmonic spectra for the phase “a” current before and after the start of the dead time compensation. Note that the fifth and seventh harmonics have their magnitudes decreased, as expected by the theoretical analysis. The THD is reduced from 14% to 2.67% complying the requirements of IEEE-1547 [19]. Table 4 presents a comparison between the experimental values obtained from Fig. 13(a) and harmonic currents calculated using (9). The small difference between theoretical and experimental results corroborates to the validation of the mathematical model. Experimental results are obtained using a closed-loop current controller. Therefore, its influence should be taken into account during the analysis. Fig. 14 shows the Bode Diagram of the closed-loop current controller, highlighting the attenuation in fifth and seventh harmonic components. These attenuation need to be considered in the harmonic component calculation of the output current. The current controller closed-loop transfer function is designed to behave as a first order dynamic system, as follows
Table 4 Harmonic current based on theoretical analysis and experimental results. Order of harmonic
5th 7th
Magnitude of current Theoreticala (Eq. (9))
Experimental (Fig. 13)
0.94 A 0.36 A
0.91 A 0.33 A
a Values multiplied by attenuation of current closed-loop transfer function given in Fig. 14.
increased. This behaviour is due to the fact that the relative weight of the time-delays increases with the reduction of switching period Ts. From (5), and considering the parameters given in Tables 1 and 2, the distortion voltage ΔV increases from 18.08 V to 22.59 V when the switching frequency goes from 10 kHz to 25 kHz, respectively. The comparison between the left and right plots of Fig. 11 shows that the proposed compensation method improves the waveforms of the current synthesized by the converter, reducing its total harmonic distortion (THD). Nevertheless, although the switching frequency reduction decreases the magnitude of the distortion voltage ΔV, it increases the output current commutation ripple.
Fig. 14. Closed-loop current controller frequency response. 9
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Fig. 15. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 0 A and iq* = 7 A and considering different switching frequencies for the converter: (a) without dead-time compensation; (b) with proposed compensation.
Gi,CL (s ) =
* idq i dq
=
1 , 1 + is
and ωo = 2π60 rad/s. To perform stability analysis the signal function shown in Fig. 17 can be replaced by its describing function Yf(A) = 4/(πA) [21], where A is the amplitude of the input signal. Then, the block diagram can be redraw as shown in Fig. 17b). According to the Nyquist stability analysis there will be limit cycles if the equation
(12)
where τi is the chosen closed-loop time constant. A trade-off between fast response and attenuation characteristics is important when choosing an adequate time constant. Yazdani and Iravani [17] suggest a value between 0.5 ms and 5 ms. In this paper τi was chosen equal to 1.25 ms. Finally, to analyse the proposed compensation effectiveness under different operation modes, the system is tested under active power consumption and reactive power compensation. Figs. 15 and 16 show the phase “a” grid-voltage and the converter output current when the VSC compensates reactive power and drains active, respectively. Again, the results are shown for three different switching frequencies. The comparison between the left and right columns demonstrates that the proposed compensation strategy effectively reduces the output current harmonic distortion caused the time-delays. The stability analysis of the proposed compensation method can be performed redrawing the block diagram of Fig. 6 as shown in Fig. 17(a). The proportional integral controller, originally designed in dq-reference frame, was replaced by an equivalent proportional resonant controller Ci (s ) = kp + ki /(s 2 + o2) in abc–reference frame, as described in [20]. The gains kp = R/τi and ki = L/τi were chosen to guarantee a first-order dynamic behaviour, as shown in (12), for the VSC current closed-loop,
G (j ) =
1 , Yf (A)
(13)
is satisfied. Where
G (j ) = V
H (j ) [1 1 + Ci (j ) H (j )
N (j )].
(14)
The easiest way to solve (13) is to plot both sides of the equation in a complex plane and find the intersection points of the two curves as depicted in Fig. 18. As the curves does not intersect, no limit cycle is expected. Furthermore, as −1/Yf(A) lies completely outside the Nyquist curve the oscillations will vanish [21]. It should be pointed out that the oscillations will disappear regardless of the variations in ΔV. This is due the fact that the relative degree of the transfer function G(s) is two. Limit cycles only appear if the relative degree of the linear system is higher than three. 10
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Fig. 16. Phase “a” grid-voltage (Channel 1) and VSC-current (Channel 3) waveforms for id* = for the converter: (a) without dead-time compensation; (b) with proposed compensation.
12 A and iq* = 0 A and considering different switching frequencies
Fig. 17. (a) Simplified equivalent control block diagram for phase “a”. (b) Simplified equivalent block using describing function.
5. Conclusions
results were present to validate the proposed scheme. A method to refine the compensation voltage can be used. Although, by only using datasheet informations, it is possible to effectively reduce the harmonics currents caused by dead-time effect and voltage drops. An important point is to use the fundamental frequency of current to determine the polarity. Harmonic currents affect the process of estimating the distorting voltages. The use of proposed compensation strategy has the advantage of being independent of the switching frequency. This feature allows operating the converter with higher switching frequencies, limited only by the physical capacity of the semiconductor devices, without compromising the output current quality. As a consequence, smaller output
This work presented a simple and effective dead-time delay compensation for grid-connected converters. Based on lag times and voltage drop effects, it was possible to model the distortion voltage at VSC's terminals. The main idea of compensation strategy proposed here consists of adding the estimated distorting voltage due to the dead-time to the current controller output signal, reducing the undesired effects of the commutation time-delays. The compensation method was tested under different switching frequencies and operation modes: absorbing or supplying active power and supporting positive or negative reactive power. Experimental 11
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Fig. 18. Describing function analysis.
filters can be used, reducing the cost, volume and weight of the system. Further advantages are: independence of the operation mode; independence of control law used to regulate the output currents (plug-in characteristic); short transient and the fact the system's stability is not jeopardized when the compensation loop is added.
Acknowledgements The authors would like to thank the National Council for Scientific and Technological Development (CNPq), the Coordination for the Improvement of Higher Education Personnel (CAPES), the State Funding Agency of Minas Gerais (FAPEMIG), UFMG and UFJF for financial support for the development of this research.
Appendix A. Notch filter transfer function The transfer function of the notch-filter used by the dead-time compensating algorithm to estimate the fundamental frequency of the VSC currents is:
N (s ) =
s2
s 2 + c2 + s Qb +
2 c
(A.1)
where ωc is the cut-off frequency, Q is the quality-factor and ( b / Q ) defines the rejection band width of the filter. Fig. A.19 shows the notch filter frequency response for ωb = 2πfb, fb = 10 Hz, Q = 0.707, ωc = 2πf1 and f1 = 60 Hz.
Fig. A.19. Notch-filter frequency response. 12
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