- Email: [email protected]
A simple digital delay for nuclear physics experiments
Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
A simple digital delay for nuclear physics experiments J.G. Marques a,n, C. Cruz b a b
C2TN, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS, Portugal LATR, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS, Portugal
art ic l e i nf o
a b s t r a c t
Article history: Received 15 July 2013 Received in revised form 19 January 2014 Accepted 28 January 2014 Available online 4 February 2014
A simple high precision digital delay for nuclear physics experiments was developed using fast ECL electronics. The circuit uses an oscillator synchronized with the signal to be delayed and a presettable counter. It is capable of delaying a negative NIM signal by 2 ms with a precision better than 50 ps. The circuit was developed for use in slow-fast coincidence units for Perturbed Angular Correlation spectrometers but it is not limited to this application. & 2014 Elsevier B.V. All rights reserved.
Keywords: Perturbed Angular Correlations Experimental nuclear physics Digital delay Emitter-Coupled Logic
1. Introduction The use of high precision delays is common in nuclear physics apparatus, laser timing systems, and automated testing, amongst other applications. Perturbed Angular Correlation (PAC) of gamma radiation is a well-known nuclear physics technique for investigation in solid state physics through the measurement of hyperfine interactions [1]. PAC uses an unstable probe nucleus that decays through a γ–γ cascade, with an intermediate state with suitable spin, half-life, and nuclear moments. In a PAC spectrometer the time interval between the detection of the two γ transitions of the cascade is recorded; its histogram will show the half-life of the intermediate state of the cascade, perturbed by the interaction of the nuclear probe with the surrounding atoms in the material under study. The perturbation is extracted using standard procedures [2]. Although only two detectors are strictly necessary to detect the two radiations of the γ–γ cascade, virtually all PAC studies are currently performed using four- or six-detector spectrometers [2–11]. Digital signal processors started being used in the last decade [6–8,10,11] but the data rates are still challenging for this technical approach. Most conventional spectrometers use a “slow-fast” arrangement, schematically shown in Fig. 1 using only two detectors. Two signals are extracted from the photomultiplier associated with each detector: a fast signal from the anode, for timing, and a slow signal from one of the last dynodes, for energy discrimination. In the “slow-fast” arrangement the fast timing pulses after discrimination,
n
Corresponding author. E-mail address: [email protected] (J.G. Marques).
http://dx.doi.org/10.1016/j.nima.2014.01.060 0168-9002 & 2014 Elsevier B.V. All rights reserved.
typically using a constant fraction discriminator (CFD) [12], are gated by the corresponding slow energy channel. This arrangement has the advantage of reducing the number of events at the time-toamplitude converter (TAC), but the delay introduced by the processing electronics in the slow channel must be compensated by a fixed delay inserted in the fast channel before the coincidence circuitry. An energy selection of the timing signals can also be achieved when detecting conversion electrons from one of the transitions of the γ–γ cascade of some PAC isotopes using a magnetic spectrometer or when using fast discriminators with energy selection [13–15] but these variants are less common. A delay of about 1.5 ms is sufficient to ensure a good energy discrimination using a conventional amplifier with a short integration constant and a timing single channel analyzer (TSCA) for energy discrimination. This delay is usually done using 300 m of good quality coaxial cable which presents the following disadvantages:
For a six-detector spectrometer this amounts to a total of
1800 m of cable occupying a larger volume than the rest of the electronics. To compensate for the degradation in amplitude and rise-time of the timing signal it is common to use an additional fast discriminator after the cable delay, thus increasing the number of electronic modules per detector channel; as an alternative the cable can be split in two sections, 200 m after the anode and 100 m after the CFD [4] which is not optimal for discrimination of the fast anode signals.
A simple delay circuit based on the well-known 74LS121 Transistor–Transistor Logic (TTL) monostable [16] with a selected
J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
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Fig. 1. Schematic representation of a “slow–fast” arrangement used in PAC spectrometers. Only two detectors are shown; when more detectors are used, the “start” input of the TAC is preceded by an OR logic function of all start signals from the detectors and the same is done for the “stop” signals; the memory of the multichannel analyzer (MCA) must then be subdivided in equal segments to include the necessary combinations of pairs of detectors.
capacitor has been used in a PAC spectrometer as an alternative to this procedure but the time resolution was limited to 1 ns for a delay of 1 ms [17], which was acceptable when measuring relatively slow hyperfine interaction frequencies using a spectrometer with NaI(Tl) scintillators. Since the typical time resolution using NaI(Tl) scintillators was of the order of a few ns, this active delay did not worsen the time resolution considerably. BaF2 scintillators have been used in PAC spectrometers since the 1980s and allow time resolutions of the order of a few tenths of ns [18], also dependent on the energies of the γ–γ cascade [19]. Similar time resolutions can be achieved with the newer LaBr3(Ce) scintillators [11] which have the added advantage of a better energy resolution than BaF2. Thus fast, low jitter electronics are required and the number of units per detector channel should be reduced to the extent possible. The achievable precision for a state-of-the-art capacitor-based timing circuit can be inferred, e.g., from commercially available TAC, whose time resolution is specified at approximately 0.01% of the range [20,21], or 150 ps for a hypothetical 1.5 ms range. The circuit discussed here is a simple alternative to the use of purely passive delay or to capacitor-based active delay. The delay introduced by a 300 m long cable is simulated using a significantly smaller cable and a control circuit which makes a signal go through the cable a certain number of times. This general approach has been implemented before using a 150 ns long cable and a programmable decade counter [22]. We have opted to insert the cable in an oscillator loop with simpler electronics and a significantly smaller cable. Surface mounted Emitter-Coupled Logic (ECL) circuits of the series 10H, 10E and 10EL (ON Semiconductor) [23,24] and an ultrafast ECL comparator (Maxim) [25] were used in a multilayered board, achieving a 2 ms delay with a precision better than 50 ps.
2. Circuit description and implementation The developed digital delay is based on an oscillator and a presettable counter. Since the signal to be delayed is random, if a free running oscillator was used it would be necessary to use
a frequency of the order of a few GHz to obtain a precision of 100 ps, due to the inherent one-clock pulse error [26]. However, it is possible to use a frequency two to three orders of magnitude lower if a synchronous circuit is used, i.e., if the oscillator is started by the incoming signal. This approach has already been used with a crystalcontrolled TTL oscillator [27], but its performance was still limited by the characteristics of TTL gates. Crystal-controlled oscillators using ECL gates are discussed in detail in Refs. [28,29]. These oscillators have very good stability to temperature and power supply variations which would make them the first choice for the application described here. However, we found it easier to make a reliable triggered oscillator using a simple cable delay in the feedback loop. Fig. 2 shows a simplified diagram of the main part of the developed circuit, where filtering capacitors were left out. The incoming negative NIM [30] signal is first converted to ECL levels using an ultra-fast comparator (U1, MAX9691) and then triggers a D-type flip-flop (U2C, 1/4 of MC10E131). Any further incoming signals will be ignored until the delay period is over. Upon valid triggering, the Qn output of the flip-flop goes to the low state and enables a NOR gate (U3D, 1/4 of 10H102) to act as an inverter. With a 70 cm long ( 3 ns) RG174 coaxial cable between the other input and the output, this gate will oscillate with a period of approximately 8 ns, i.e., twice the length of the cable plus the propagation delay of the gate. An oscillator synchronized with the incoming signal is thus obtained; its period can be adjusted using different lengths of cable. Practice has shown that a better performance of the oscillator is obtained using a gate with two independent outputs, so that one output is used only for the oscillator and the other only for the load; a second gate from the same chip is used as a buffer and the remaining gates are left unused, albeit properly terminated. The 50 Ω coaxial cable in the feedback loop is terminated using a standard 82.5–133 Ω resistor pair at the end of the cable to match its impedance [28]. An 8-bits presettable synchronous binary counter (U4, MC10E016) is used to count a prescribed number of times. In order to allow some flexibility, 4 bits can be programmed by the user via a dip switch and the remaining four are fixed. For the 3 ns long cable mentioned above the maximum delay is approximately 2 ms (256 times the oscillator period of 8 ns).
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J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
Fig. 2. Simplified diagram of the main part of the developed delay circuit.
Upon completion of the count, the Terminate Count (TCn) output goes low, generates the delayed signal and reloads the counter. A differential receiver (U5, MC10EL16) is used to buffer TCn and provide also its complement. These signals are used to generate, with another D-type flip-flop (U2D, 1/4 of MC10E131), an internal reset, namely for the D-type flip-flop at the input, a negative NIM signal for output/test and provide a timing signal for further internal processing. The level conversion of the input negative NIM signal can be done with other ECL fast comparators [31], or with standard levelshifters [32] without significant loss of performance. For other applications, several ECL counters can be cascaded, if necessary, using standard techniques [28,33]. Since it is desirable to reduce the number of electronic units per detector channel, it was decided to implement also the “slow-fast” coincidence circuitry in the same board for 2 TSCA from the same detector. Fig. 3 shows a simplified diagram of the coincidence circuit, where filtering capacitors were again left out. The two positive NIM signals from the TSCA are first converted to ECL levels using standard translators (U6A and U6B, 1/4 MC10H124 each), whose outputs go to the data inputs of two D-type flip-flops (U2A and U2B, 1/4 10E131 each) triggered by the buffered (inverted) TC signal. Negative NIM output signals are then generated using standard differential pairs with fast NPN transistors; positive NIM signals are also generated using simple monostable transistor-based circuits (not shown). As the slow channel has a higher jitter than the fast channel, the width of the signals from the TSCA must be, in practice, at least 100 ns. This is below the nominal width of positive NIM signals (500 ns) here used, so no changes are necessary, as the extra width causes no problems. If the negative NIM outputs of the TSCA had been used, it would have been necessary to enlarge their width
from the usual 10–20 ns to about 200 ns before performing the coincidence. The delay of the individual TSCA must always be adjusted to ensure that the selected output is always in advance of the corresponding delayed fast signal, so that the D-type flip-flops are properly triggered. The use of a D-type flip-flop for a coincidence operation is common in the internal structure of a CFD, where it avoids multiple triggering [12]. No such possibility exists in our circuit and the coincidence could also have been implemented using AND gates, without significant loss of performance. We have opted to use flip-flops to reduce the number of integrated circuits and minimize the length of timing-critical lines in the board. The overall circuit was implemented in a four-layer printed circuit board measuring 190 by 90 mm, housing the surfacemounted components and the coaxial cable in the oscillator. Besides the circuits described above, a TTL dual monostable circuit 74HCT123 was used to power two LEDs to give a visual indication of activity in each of the coincidence channels. Fig. 4 shows the general layout of the printed circuit board. The 5.2 V supply for the ECL circuits is obtained from the 6 V line of a NIM bin using a simple circuit with an JFET-input operational amplifier (TL081) and a power PNP transistor (PBSS9110). The consumption on the 6 V line is 590 mA. The delay and coincidence board was installed inside a single-width NIM module.
3. Performance Fig. 5 shows the startup of the oscillator as a response to the change of status of the flip-flop controlling the NOR gate.
J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
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Fig. 3. Simplified diagram of the coincidence circuit included in the same unit.
Fig. 4. General layout of the printed circuit board. The coaxial cable can be mounted in the upper right side of the board.
Fig. 5. Oscillator startup (lower trace, pin 18 of U3) as a response to the change of status of the flip-flop controlling the NOR gate (upper trace, pin 18 of U2). The horizontal scale is 40 ns/division. The image was taken using a Tektronix DPO2014 oscilloscope with 200 MHz bandwidth.
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Fig. 6 shows the test setup used to characterize the precision of the delay. An Ortec 462 Time Calibrator (TC) was used as a signal source. The TC produces pairs of “start” and “stop” signals separated by time intervals as specified in the period control, with a maximum value specified by the range control. The delay unit under test was inserted in the “start” signal path before the TAC, as shown in Fig. 6. With this setup the TAC measures a smaller effective range, as the “start” signals are being further delayed. While the TC range must be higher than the delay to be characterized, say 2.56 ms for a delay exceeding 1.28 ms (nearest value), it is possible to use a small TAC range (typically 50 ns) benefiting from a smaller time per channel value; the period control of the TC is adjusted from 2.56 ms down to the value where counts start to appear in the multichannel analyzer. In all tests we have used a TAC range of 50 ns and an MCA with 4096 channels, giving a time calibration of 11.970.1 ps/channel. Fig. 7 shows the result obtained using the setup with the 70 cm long cable and the counter set to 256, for 300 s and 12 h long acquisitions. The climatized laboratory has daily temperature variations of the order 70.5 1C. The short acquisition time profile has FWHM ¼46 ps, while for the longer acquisition time it has FWHM ¼80 ps, further showing a small tail. The observed degradation is most likely a result of delay drifts with power supply and temperature, which need to be quantified. The 6 V supply voltage was varied between 5.8 V and 6.2 V to measure the drift with supply voltage. The drift with temperature was measured after decreasing the forced air flow
Fig. 6. Test setup using a Time Calibrator (TC) Ortec 462 as a signal source. The delay under test is inserted in the “start” path between the TC and the time-toamplitude (TAC) converter.
through a full NIM bin including the unit under test. The temperatures of the TC, TAC and MCA were left unchanged. Switching off the fans placed on top of the NIM bin led to a typical temperature increase of 2.5 1C. When the 6 V supply voltage was changed to 5.8 V, the delay decreased by 120 ps; when it changed to 6.2 V, the delay increased by 24 ps. The asymmetry in these values reflects the action of the power supply in the unit under test – when the absolute value of the 6 V supply is increased there is hardly any effect, while its reduction leads to an inevitable decrease in its output, due to the reduced margin between the 6 V supply voltage and the intended output of 5.2 V. The measured delay drift with temperature was 0.9 70.2 ns/1C. The relatively high delay drifts are a consequence of the structure of the circuit. In fact, the oscillator “multiplies” by two the propagation delay drift of the oscillator gate (U3D) and then the counter “multiplies” this drift by the number of cycles, resulting in an overall “multiplication” factor of 512. The typical propagation delay drift with temperature of an ECL 10H gate is 0.5 ps/1C and its maximum value is 4 ps/1C [23]. The average measured drift is 1.7 ps/1C, well within the specifications. The loading of the counter was then reduced from 256 to 32, without changing the delay cable, in order to verify its effect. As a result, the temperature drift was reduced to 0.13 70.03 ns/1C, i.e., by a factor close to the reduction in the counter loading. The delay drift for a power supply change from 6.0 to 5.8 V was reduced to 12 ps and the drift for a power supply variation from 6.0 to 6.2 V was reduced to 6 ps. Taking into account this significant improvement, the delay cable was increased to 7 m (approximately 35 ns) in order to get back an overall delay of approximately 2 ms while keeping the counter with a loading of 32. The measured temperature drift was 0.14 70.03 ns/1C, i.e., without significant changes. Fig. 8 shows the result obtained using the setup with the 7 m long cable and the counter set to 32, for 300 s and 12 h long acquisitions. The short acquisition time profile has FWHM ¼ 30 ps,
Fig. 7. Characterization of the precision of the delay unit using the test setup for 300 s and 12 h long acquisitions. The counter was set to 256.
J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
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Fig. 8. Characterization of the precision of the optimized delay unit using the test setup for 300 s and 12 h long acquisitions. The counter was set to 32. Table 1 Specifications and measured performance of the digital delay. Parameter
Initial
Optimized
DGG7
Delay range Delay under test [ms] Short-time resolution FWHM [ps]a Overnight resolution FWHM [ps]b Temperature drift [ns/1C] Power supply drift ( 6.0 V to 5.8 V) [ns/V] Power supply drift ( 6.0 to 6.2 V) [ns/V] Consumption on 6 V supply [A]
256x internal cable 2 467 6 807 6 0.9 7 0.2 0.6 7 0.1 0.127 0.02 0.6
32x internal cable 2 307 6 48 7 6 0.147 0.03 0.067 0.01 0.03 7 0.01 0.6
1–10x internal cable of 150 ns 1.5 697 6 1757 6 0.177 0.03 4.3 7 0.4 n/ac 1.0
a b c
Acquisition time of 300 s. Acquisition time of 12 h. Not measured due to instability.
while for the longer acquisition time it has FWHM ¼48 ps. These values are significantly better than the ones observed before optimization and can be considered excellent for a PAC spectrometer. Table 1 summarizes the performance parameters for the initial delay unit, its optimized version and a DGG7 “Precise Delay Generator” [22] tested for comparison purposes. The optimized version of the delay unit described here is clearly better in every parameter. There are clear advantages in using a relatively small number of cycles in the delay and thus a larger coaxial cable in the oscillator. In case the amplitude of the ECL signal is too attenuated by the coaxial cable it will be necessary to reformat it, for example, using a fast comparator, such as used in the DGG7 delay. The contribution of the TC to the measured values can be determined using the test setup without any delays in the “start” and “stop” signal paths. The response is characterized by a Gaussian curve with FWHM ¼ 22 ps for a 1 h long acquisition. The stability of the period of the TC is better than 10 ppm/1C [34] of the selected period which was 40 ns in most of the measurements reported here.
The delay circuit as built has a dead time equivalent to the delay, i.e., a second signal which comes during the time interval where the previously accepted signal is being delayed will be ignored. This is not a problem in PAC spectrometers as the amplifier in the slow channel of each detector is doing an equivalent rejection and there is a one-to-one correspondence between the “fast” and “slow” signals, at least as long as proper noise discrimination is being done. Some CFDs include “blocking” features to avoid retriggering within an adjustable period, so this feature may already be present in the fast channel of each detector on the PAC spectrometer. In applications where a long dead-time is problematic, a suitable number of units can be used in series or in parallel, using a distributor as described in Ref. [35]. Fast digitizers allow the implementation of integer delays and fractional delays (of the sampling interval) and could be used to implement a versatile digital delay. The use of fractional delays has allowed, e.g., the recent optimization of a digital CFD with excellent timing characteristics [36]. On the other hand such digitizers allow implementing an all-digital PAC spectrometer with no need for external signal processing units [6–8,10,11]. As there are no clear advantages of a “hybrid” PAC spectrometer, the implementation of
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J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
a delay and coincidence unit using a fast digitizer has not been pursued here.
4. Conclusions The circuit presented here is a simple alternative to the use of passive cable delay or active capacitor-based delay. The delay introduced by a 300 m long cable is obtained using a significantly smaller cable and a control circuit which makes the signal go through the cable a certain number of times. The use of fast ECL integrated circuits allows delaying a negative NIM signal by 2 ms with a precision better than 50 ps. Although the circuit was developed for PAC spectrometers using negative NIM logic signals, its use is not limited to this application. The value of the delay can be changed through the programmable counter and the length of the cable used. Furthermore, the circuit can be easily changed to other input/output signal standards using suitable level converters to and from ECL. The authors can supply upon request the complete schematics and the printed circuit board layout ready for assembling.
Acknowledgments This work was partially supported by FCT, Portugal, through Project POCI/FIS/58498. The authors gratefully acknowledge Dr. Guilherme Correia (IST) for making available a DGG7 delay generator for comparison testing. Professor António Melo (Univ. Lisbon) is kindly acknowledged for being a source of inspiration on the simplification and optimization of PAC spectrometers. References [1] B. Hauer, R. Vianden, J.G. Marques, N.P. Barradas, J.G. Correia, A.A. Melo, J.C. Soares, F. Agulló-López, E. Diéguez, Physical Review B 51 (1995) 6208. [2] A.R. Arends, C. Hohenemser, F. Pleiter, H. de Waard, L. Chow, R.M. Sutter, Hyperfine Interactions 8 (1980) 191. [3] A. Baudry, P. Boyer, S. Choulet, C. Gamrat, P. Peretto, D. Perrin, R. Van Zurk, Nuclear Instruments and Methods A 260 (1987) 160. [4] T. Butz, S. Saibene, Th. Fraenzke, M. Weber, Nuclear Instruments and Methods A 284 (1989) 417. [5] J.G. Marques, J.G. Correia, A.A. Melo, M.F. da Silva, J.C. Soares, ISOLDE collaboration, Nuclear Instruments and Methods B 99 (1995) 645.
[6] C.H. Herden, M.A. Alves, K.D. Becker, J.A. Gardner, Hyperfine Interactions 159 (2005) 379. [7] C. Herden, J. Röder, J.A. Gardner, K.D. Becker, Nuclear Instruments and Methods A 594 (2008) 155. [8] J. Röder, C. Herden, J.A. Gardner, K.D. Becker, M. Uhrmacher, H. Hofsäss, Hyperfine Interactions 181 (2008) 131. [9] M. Rentería, A.G. Bibiloni, G.N. Darriba, L.A. Errico, E.L. Muñoz, D. Richard, J. Runco, Hyperfine Interactions 181 (2008) 145. [10] M. Nagl, U. Vetter, M. Uhrmacher, H. Hofsäss, Review of Scientific Instruments 81 (2010) 073501. [11] M. Jäger, K. Iwig, T. Butz, Review of Scientific Instruments 82 (2011) 065105. [12] J. Bialkowski, M. Moszynski, D. Wolski, Nuclear Instruments and Methods A 281 (1989) 657. [13] J.G. Correia, H. Haas, J.G. Marques, A.A. Melo, J.C. Soares, ISOLDE collaboration, Hyperfine Interactions 80 (1993) 1321. [14] J.G. Correia, J.G. Marques, E. Alves, D. Forkel-Wirth, S.G. Jahn, M. Restle, M. Dalmer, H. Hofsäss, K. Baruth-Ram, ISOLDE collaboration, Nuclear Instruments and Methods B 127/128 (1997) 723. [15] A. Bartos, K. Schemmerling, Th. Wenzel, M. Uhrmacher, Nuclear Instruments and Methods A 330 (1993) 132. [16] P. Horowitz, W. Hill, The Art of Electronics, Cambridge University Press, Cambridge, 1989. [17] A.R. Arends, Hyperfine interactions in cubic metals using perturbed angular correlation techniques (Ph.D. thesis), University of Groningen, The Netherlands, 1981 (unpublished). [18] J. Van Cauteren, G.N. Rao, M. Rots, Nuclear Instruments and Methods A 243 (1986) 445. [19] E. Gerdau, T.A. Thiel, G. Netz, Hyperfine Interactions 10 (1981) 1155. [20] EG&G Ortec, Model 566 Time-to-Amplitude Converter Operating and Service Manual, 1991. [21] Canberra Industries, Model 2145 Time to Amplitude Converter User's Manual, 2005. [22] Precise Delay Generator DGG7, Hahn Meitner Institute, Berlin. [23] ON Semiconductor, MECL Data, DL122/D, Rev. 7, 2000. [24] ON Semiconductor, High Performance ECL Data, DL150/D, Rev. 6, 2001. [25] Maxim Integrated Products, Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable, Rev. 2, 2012. [26] J. Kalisz, Metrologia 41 (2004) 17. [27] J. Pesor, W.D. Lawrance, Measurement Science and Technology 1 (1990) 24. [28] W.R. Blood , MECL system design handbook, HB205/D, Rev. 1A, ON Semiconductor, 4th ed. , 1988. [29] R.J. Matthys, Crystal Oscillator Circuits, Krieger Publishing Co., Malabar, 1992. [30] U.S. NIM Committee, Standard NIM Instrumentation System, DOE/ER-0457T, Department of Energy, Washington, 1990. [31] B.T. Turko, W.F. Kolbe, R.C. Smith, IEEE Transactions on Nuclear Science 37 (1990) 424. [32] A. Barna, E.L. Cisneros, Nuclear Instruments and Methods 73 (1969) 347. [33] H. Suzuki, H. Ego, M. Hara, T. Hori, Y. Kawashima, Y. Ohashi, T. Ohshima, N. Tani, H. Yonehara, Nuclear Instruments and Methods A 431 (1999) 294. [34] Advanced Measurement Technology, Model 462 Time Calibrator Operating and Service Manual, 2002. [35] A.K. Tickoo, C.L. Bhat, R. Koul, I.K. Kaul, S.K. Kaul, S.R. Kaul, Nuclear Instruments and Methods A 349 (1994) 600. [36] M. Jäger, T. Butz, Nuclear Instruments and Methods in Physics Research A 674 (2012) 24.
Contents lists available at ScienceDirect
Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima
A simple digital delay for nuclear physics experiments J.G. Marques a,n, C. Cruz b a b
C2TN, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS, Portugal LATR, Campus Tecnológico e Nuclear, Instituto Superior Técnico, Universidade de Lisboa, Estrada Nacional 10, km 139.7, 2695-066 Bobadela LRS, Portugal
art ic l e i nf o
a b s t r a c t
Article history: Received 15 July 2013 Received in revised form 19 January 2014 Accepted 28 January 2014 Available online 4 February 2014
A simple high precision digital delay for nuclear physics experiments was developed using fast ECL electronics. The circuit uses an oscillator synchronized with the signal to be delayed and a presettable counter. It is capable of delaying a negative NIM signal by 2 ms with a precision better than 50 ps. The circuit was developed for use in slow-fast coincidence units for Perturbed Angular Correlation spectrometers but it is not limited to this application. & 2014 Elsevier B.V. All rights reserved.
Keywords: Perturbed Angular Correlations Experimental nuclear physics Digital delay Emitter-Coupled Logic
1. Introduction The use of high precision delays is common in nuclear physics apparatus, laser timing systems, and automated testing, amongst other applications. Perturbed Angular Correlation (PAC) of gamma radiation is a well-known nuclear physics technique for investigation in solid state physics through the measurement of hyperfine interactions [1]. PAC uses an unstable probe nucleus that decays through a γ–γ cascade, with an intermediate state with suitable spin, half-life, and nuclear moments. In a PAC spectrometer the time interval between the detection of the two γ transitions of the cascade is recorded; its histogram will show the half-life of the intermediate state of the cascade, perturbed by the interaction of the nuclear probe with the surrounding atoms in the material under study. The perturbation is extracted using standard procedures [2]. Although only two detectors are strictly necessary to detect the two radiations of the γ–γ cascade, virtually all PAC studies are currently performed using four- or six-detector spectrometers [2–11]. Digital signal processors started being used in the last decade [6–8,10,11] but the data rates are still challenging for this technical approach. Most conventional spectrometers use a “slow-fast” arrangement, schematically shown in Fig. 1 using only two detectors. Two signals are extracted from the photomultiplier associated with each detector: a fast signal from the anode, for timing, and a slow signal from one of the last dynodes, for energy discrimination. In the “slow-fast” arrangement the fast timing pulses after discrimination,
n
Corresponding author. E-mail address: [email protected] (J.G. Marques).
http://dx.doi.org/10.1016/j.nima.2014.01.060 0168-9002 & 2014 Elsevier B.V. All rights reserved.
typically using a constant fraction discriminator (CFD) [12], are gated by the corresponding slow energy channel. This arrangement has the advantage of reducing the number of events at the time-toamplitude converter (TAC), but the delay introduced by the processing electronics in the slow channel must be compensated by a fixed delay inserted in the fast channel before the coincidence circuitry. An energy selection of the timing signals can also be achieved when detecting conversion electrons from one of the transitions of the γ–γ cascade of some PAC isotopes using a magnetic spectrometer or when using fast discriminators with energy selection [13–15] but these variants are less common. A delay of about 1.5 ms is sufficient to ensure a good energy discrimination using a conventional amplifier with a short integration constant and a timing single channel analyzer (TSCA) for energy discrimination. This delay is usually done using 300 m of good quality coaxial cable which presents the following disadvantages:
For a six-detector spectrometer this amounts to a total of
1800 m of cable occupying a larger volume than the rest of the electronics. To compensate for the degradation in amplitude and rise-time of the timing signal it is common to use an additional fast discriminator after the cable delay, thus increasing the number of electronic modules per detector channel; as an alternative the cable can be split in two sections, 200 m after the anode and 100 m after the CFD [4] which is not optimal for discrimination of the fast anode signals.
A simple delay circuit based on the well-known 74LS121 Transistor–Transistor Logic (TTL) monostable [16] with a selected
J.G. Marques, C. Cruz / Nuclear Instruments and Methods in Physics Research A 745 (2014) 50–56
51
Fig. 1. Schematic representation of a “slow–fast” arrangement used in PAC spectrometers. Only two detectors are shown; when more detectors are used, the “start” input of the TAC is preceded by an OR logic function of all start signals from the detectors and the same is done for the “stop” signals; the memory of the multichannel analyzer (MCA) must then be subdivided in equal segments to include the necessary combinations of pairs of detectors.
capacitor has been used in a PAC spectrometer as an alternative to this procedure but the time resolution was limited to 1 ns for a delay of 1 ms [17], which was acceptable when measuring relatively slow hyperfine interaction frequencies using a spectrometer with NaI(Tl) scintillators. Since the typical time resolution using NaI(Tl) scintillators was of the order of a few ns, this active delay did not worsen the time resolution considerably. BaF2 scintillators have been used in PAC spectrometers since the 1980s and allow time resolutions of the order of a few tenths of ns [18], also dependent on the energies of the γ–γ cascade [19]. Similar time resolutions can be achieved with the newer LaBr3(Ce) scintillators [11] which have the added advantage of a better energy resolution than BaF2. Thus fast, low jitter electronics are required and the number of units per detector channel should be reduced to the extent possible. The achievable precision for a state-of-the-art capacitor-based timing circuit can be inferred, e.g., from commercially available TAC, whose time resolution is specified at approximately 0.01% of the range [20,21], or 150 ps for a hypothetical 1.5 ms range. The circuit discussed here is a simple alternative to the use of purely passive delay or to capacitor-based active delay. The delay introduced by a 300 m long cable is simulated using a significantly smaller cable and a control circuit which makes a signal go through the cable a certain number of times. This general approach has been implemented before using a 150 ns long cable and a programmable decade counter [22]. We have opted to insert the cable in an oscillator loop with simpler electronics and a significantly smaller cable. Surface mounted Emitter-Coupled Logic (ECL) circuits of the series 10H, 10E and 10EL (ON Semiconductor) [23,24] and an ultrafast ECL comparator (Maxim) [25] were used in a multilayered board, achieving a 2 ms delay with a precision better than 50 ps.
2. Circuit description and implementation The developed digital delay is based on an oscillator and a presettable counter. Since the signal to be delayed is random, if a free running oscillator was used it would be necessary to use
a frequency of the order of a few GHz to obtain a precision of 100 ps, due to the inherent one-clock pulse error [26]. However, it is possible to use a frequency two to three orders of magnitude lower if a synchronous circuit is used, i.e., if the oscillator is started by the incoming signal. This approach has already been used with a crystalcontrolled TTL oscillator [27], but its performance was still limited by the characteristics of TTL gates. Crystal-controlled oscillators using ECL gates are discussed in detail in Refs. [28,29]. These oscillators have very good stability to temperature and power supply variations which would make them the first choice for the application described here. However, we found it easier to make a reliable triggered oscillator using a simple cable delay in the feedback loop. Fig. 2 shows a simplified diagram of the main part of the developed circuit, where filtering capacitors were left out. The incoming negative NIM [30] signal is first converted to ECL levels using an ultra-fast comparator (U1, MAX9691) and then triggers a D-type flip-flop (U2C, 1/4 of MC10E131). Any further incoming signals will be ignored until the delay period is over. Upon valid triggering, the Qn output of the flip-flop goes to the low state and enables a NOR gate (U3D, 1/4 of 10H102) to act as an inverter. With a 70 cm long ( 3 ns) RG174 coaxial cable between the other input and the output, this gate will oscillate with a period of approximately 8 ns, i.e., twice the length of the cable plus the propagation delay of the gate. An oscillator synchronized with the incoming signal is thus obtained; its period can be adjusted using different lengths of cable. Practice has shown that a better performance of the oscillator is obtained using a gate with two independent outputs, so that one output is used only for the oscillator and the other only for the load; a second gate from the same chip is used as a buffer and the remaining gates are left unused, albeit properly terminated. The 50 Ω coaxial cable in the feedback loop is terminated using a standard 82.5–133 Ω resistor pair at the end of the cable to match its impedance [28]. An 8-bits presettable synchronous binary counter (U4, MC10E016) is used to count a prescribed number of times. In order to allow some flexibility, 4 bits can be programmed by the user via a dip switch and the remaining four are fixed. For the 3 ns long cable mentioned above the maximum delay is approximately 2 ms (256 times the oscillator period of 8 ns).
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Fig. 2. Simplified diagram of the main part of the developed delay circuit.
Upon completion of the count, the Terminate Count (TCn) output goes low, generates the delayed signal and reloads the counter. A differential receiver (U5, MC10EL16) is used to buffer TCn and provide also its complement. These signals are used to generate, with another D-type flip-flop (U2D, 1/4 of MC10E131), an internal reset, namely for the D-type flip-flop at the input, a negative NIM signal for output/test and provide a timing signal for further internal processing. The level conversion of the input negative NIM signal can be done with other ECL fast comparators [31], or with standard levelshifters [32] without significant loss of performance. For other applications, several ECL counters can be cascaded, if necessary, using standard techniques [28,33]. Since it is desirable to reduce the number of electronic units per detector channel, it was decided to implement also the “slow-fast” coincidence circuitry in the same board for 2 TSCA from the same detector. Fig. 3 shows a simplified diagram of the coincidence circuit, where filtering capacitors were again left out. The two positive NIM signals from the TSCA are first converted to ECL levels using standard translators (U6A and U6B, 1/4 MC10H124 each), whose outputs go to the data inputs of two D-type flip-flops (U2A and U2B, 1/4 10E131 each) triggered by the buffered (inverted) TC signal. Negative NIM output signals are then generated using standard differential pairs with fast NPN transistors; positive NIM signals are also generated using simple monostable transistor-based circuits (not shown). As the slow channel has a higher jitter than the fast channel, the width of the signals from the TSCA must be, in practice, at least 100 ns. This is below the nominal width of positive NIM signals (500 ns) here used, so no changes are necessary, as the extra width causes no problems. If the negative NIM outputs of the TSCA had been used, it would have been necessary to enlarge their width
from the usual 10–20 ns to about 200 ns before performing the coincidence. The delay of the individual TSCA must always be adjusted to ensure that the selected output is always in advance of the corresponding delayed fast signal, so that the D-type flip-flops are properly triggered. The use of a D-type flip-flop for a coincidence operation is common in the internal structure of a CFD, where it avoids multiple triggering [12]. No such possibility exists in our circuit and the coincidence could also have been implemented using AND gates, without significant loss of performance. We have opted to use flip-flops to reduce the number of integrated circuits and minimize the length of timing-critical lines in the board. The overall circuit was implemented in a four-layer printed circuit board measuring 190 by 90 mm, housing the surfacemounted components and the coaxial cable in the oscillator. Besides the circuits described above, a TTL dual monostable circuit 74HCT123 was used to power two LEDs to give a visual indication of activity in each of the coincidence channels. Fig. 4 shows the general layout of the printed circuit board. The 5.2 V supply for the ECL circuits is obtained from the 6 V line of a NIM bin using a simple circuit with an JFET-input operational amplifier (TL081) and a power PNP transistor (PBSS9110). The consumption on the 6 V line is 590 mA. The delay and coincidence board was installed inside a single-width NIM module.
3. Performance Fig. 5 shows the startup of the oscillator as a response to the change of status of the flip-flop controlling the NOR gate.
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Fig. 3. Simplified diagram of the coincidence circuit included in the same unit.
Fig. 4. General layout of the printed circuit board. The coaxial cable can be mounted in the upper right side of the board.
Fig. 5. Oscillator startup (lower trace, pin 18 of U3) as a response to the change of status of the flip-flop controlling the NOR gate (upper trace, pin 18 of U2). The horizontal scale is 40 ns/division. The image was taken using a Tektronix DPO2014 oscilloscope with 200 MHz bandwidth.
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Fig. 6 shows the test setup used to characterize the precision of the delay. An Ortec 462 Time Calibrator (TC) was used as a signal source. The TC produces pairs of “start” and “stop” signals separated by time intervals as specified in the period control, with a maximum value specified by the range control. The delay unit under test was inserted in the “start” signal path before the TAC, as shown in Fig. 6. With this setup the TAC measures a smaller effective range, as the “start” signals are being further delayed. While the TC range must be higher than the delay to be characterized, say 2.56 ms for a delay exceeding 1.28 ms (nearest value), it is possible to use a small TAC range (typically 50 ns) benefiting from a smaller time per channel value; the period control of the TC is adjusted from 2.56 ms down to the value where counts start to appear in the multichannel analyzer. In all tests we have used a TAC range of 50 ns and an MCA with 4096 channels, giving a time calibration of 11.970.1 ps/channel. Fig. 7 shows the result obtained using the setup with the 70 cm long cable and the counter set to 256, for 300 s and 12 h long acquisitions. The climatized laboratory has daily temperature variations of the order 70.5 1C. The short acquisition time profile has FWHM ¼46 ps, while for the longer acquisition time it has FWHM ¼80 ps, further showing a small tail. The observed degradation is most likely a result of delay drifts with power supply and temperature, which need to be quantified. The 6 V supply voltage was varied between 5.8 V and 6.2 V to measure the drift with supply voltage. The drift with temperature was measured after decreasing the forced air flow
Fig. 6. Test setup using a Time Calibrator (TC) Ortec 462 as a signal source. The delay under test is inserted in the “start” path between the TC and the time-toamplitude (TAC) converter.
through a full NIM bin including the unit under test. The temperatures of the TC, TAC and MCA were left unchanged. Switching off the fans placed on top of the NIM bin led to a typical temperature increase of 2.5 1C. When the 6 V supply voltage was changed to 5.8 V, the delay decreased by 120 ps; when it changed to 6.2 V, the delay increased by 24 ps. The asymmetry in these values reflects the action of the power supply in the unit under test – when the absolute value of the 6 V supply is increased there is hardly any effect, while its reduction leads to an inevitable decrease in its output, due to the reduced margin between the 6 V supply voltage and the intended output of 5.2 V. The measured delay drift with temperature was 0.9 70.2 ns/1C. The relatively high delay drifts are a consequence of the structure of the circuit. In fact, the oscillator “multiplies” by two the propagation delay drift of the oscillator gate (U3D) and then the counter “multiplies” this drift by the number of cycles, resulting in an overall “multiplication” factor of 512. The typical propagation delay drift with temperature of an ECL 10H gate is 0.5 ps/1C and its maximum value is 4 ps/1C [23]. The average measured drift is 1.7 ps/1C, well within the specifications. The loading of the counter was then reduced from 256 to 32, without changing the delay cable, in order to verify its effect. As a result, the temperature drift was reduced to 0.13 70.03 ns/1C, i.e., by a factor close to the reduction in the counter loading. The delay drift for a power supply change from 6.0 to 5.8 V was reduced to 12 ps and the drift for a power supply variation from 6.0 to 6.2 V was reduced to 6 ps. Taking into account this significant improvement, the delay cable was increased to 7 m (approximately 35 ns) in order to get back an overall delay of approximately 2 ms while keeping the counter with a loading of 32. The measured temperature drift was 0.14 70.03 ns/1C, i.e., without significant changes. Fig. 8 shows the result obtained using the setup with the 7 m long cable and the counter set to 32, for 300 s and 12 h long acquisitions. The short acquisition time profile has FWHM ¼ 30 ps,
Fig. 7. Characterization of the precision of the delay unit using the test setup for 300 s and 12 h long acquisitions. The counter was set to 256.
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Fig. 8. Characterization of the precision of the optimized delay unit using the test setup for 300 s and 12 h long acquisitions. The counter was set to 32. Table 1 Specifications and measured performance of the digital delay. Parameter
Initial
Optimized
DGG7
Delay range Delay under test [ms] Short-time resolution FWHM [ps]a Overnight resolution FWHM [ps]b Temperature drift [ns/1C] Power supply drift ( 6.0 V to 5.8 V) [ns/V] Power supply drift ( 6.0 to 6.2 V) [ns/V] Consumption on 6 V supply [A]
256x internal cable 2 467 6 807 6 0.9 7 0.2 0.6 7 0.1 0.127 0.02 0.6
32x internal cable 2 307 6 48 7 6 0.147 0.03 0.067 0.01 0.03 7 0.01 0.6
1–10x internal cable of 150 ns 1.5 697 6 1757 6 0.177 0.03 4.3 7 0.4 n/ac 1.0
a b c
Acquisition time of 300 s. Acquisition time of 12 h. Not measured due to instability.
while for the longer acquisition time it has FWHM ¼48 ps. These values are significantly better than the ones observed before optimization and can be considered excellent for a PAC spectrometer. Table 1 summarizes the performance parameters for the initial delay unit, its optimized version and a DGG7 “Precise Delay Generator” [22] tested for comparison purposes. The optimized version of the delay unit described here is clearly better in every parameter. There are clear advantages in using a relatively small number of cycles in the delay and thus a larger coaxial cable in the oscillator. In case the amplitude of the ECL signal is too attenuated by the coaxial cable it will be necessary to reformat it, for example, using a fast comparator, such as used in the DGG7 delay. The contribution of the TC to the measured values can be determined using the test setup without any delays in the “start” and “stop” signal paths. The response is characterized by a Gaussian curve with FWHM ¼ 22 ps for a 1 h long acquisition. The stability of the period of the TC is better than 10 ppm/1C [34] of the selected period which was 40 ns in most of the measurements reported here.
The delay circuit as built has a dead time equivalent to the delay, i.e., a second signal which comes during the time interval where the previously accepted signal is being delayed will be ignored. This is not a problem in PAC spectrometers as the amplifier in the slow channel of each detector is doing an equivalent rejection and there is a one-to-one correspondence between the “fast” and “slow” signals, at least as long as proper noise discrimination is being done. Some CFDs include “blocking” features to avoid retriggering within an adjustable period, so this feature may already be present in the fast channel of each detector on the PAC spectrometer. In applications where a long dead-time is problematic, a suitable number of units can be used in series or in parallel, using a distributor as described in Ref. [35]. Fast digitizers allow the implementation of integer delays and fractional delays (of the sampling interval) and could be used to implement a versatile digital delay. The use of fractional delays has allowed, e.g., the recent optimization of a digital CFD with excellent timing characteristics [36]. On the other hand such digitizers allow implementing an all-digital PAC spectrometer with no need for external signal processing units [6–8,10,11]. As there are no clear advantages of a “hybrid” PAC spectrometer, the implementation of
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a delay and coincidence unit using a fast digitizer has not been pursued here.
4. Conclusions The circuit presented here is a simple alternative to the use of passive cable delay or active capacitor-based delay. The delay introduced by a 300 m long cable is obtained using a significantly smaller cable and a control circuit which makes the signal go through the cable a certain number of times. The use of fast ECL integrated circuits allows delaying a negative NIM signal by 2 ms with a precision better than 50 ps. Although the circuit was developed for PAC spectrometers using negative NIM logic signals, its use is not limited to this application. The value of the delay can be changed through the programmable counter and the length of the cable used. Furthermore, the circuit can be easily changed to other input/output signal standards using suitable level converters to and from ECL. The authors can supply upon request the complete schematics and the printed circuit board layout ready for assembling.
Acknowledgments This work was partially supported by FCT, Portugal, through Project POCI/FIS/58498. The authors gratefully acknowledge Dr. Guilherme Correia (IST) for making available a DGG7 delay generator for comparison testing. Professor António Melo (Univ. Lisbon) is kindly acknowledged for being a source of inspiration on the simplification and optimization of PAC spectrometers. References [1] B. Hauer, R. Vianden, J.G. Marques, N.P. Barradas, J.G. Correia, A.A. Melo, J.C. Soares, F. Agulló-López, E. Diéguez, Physical Review B 51 (1995) 6208. [2] A.R. Arends, C. Hohenemser, F. Pleiter, H. de Waard, L. Chow, R.M. Sutter, Hyperfine Interactions 8 (1980) 191. [3] A. Baudry, P. Boyer, S. Choulet, C. Gamrat, P. Peretto, D. Perrin, R. Van Zurk, Nuclear Instruments and Methods A 260 (1987) 160. [4] T. Butz, S. Saibene, Th. Fraenzke, M. Weber, Nuclear Instruments and Methods A 284 (1989) 417. [5] J.G. Marques, J.G. Correia, A.A. Melo, M.F. da Silva, J.C. Soares, ISOLDE collaboration, Nuclear Instruments and Methods B 99 (1995) 645.
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