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A simplified approach to hotspot alleviation in microprocessors
Accepted Manuscript A simplified approach to hotspot alleviation in microprocessors Chander Shekhar Sharma, Manish K. Tiwari, Dimos Poulikakos PII:
S1359-4311(15)00882-0
DOI:
10.1016/j.applthermaleng.2015.08.086
Reference:
ATE 6971
To appear in:
Applied Thermal Engineering
Received Date: 29 January 2015 Revised Date:
28 May 2015
Accepted Date: 28 August 2015
Please cite this article as: C.S. Sharma, M.K. Tiwari, D. Poulikakos, A simplified approach to hotspot alleviation in microprocessors, Applied Thermal Engineering (2015), doi: 10.1016/ j.applthermaleng.2015.08.086. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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A simplified approach to hotspot alleviation in microprocessors
Chander Shekhar SHARMA 1, Manish K. TIWARI 2, Dimos POULIKAKOS 1,* * Corresponding author: Tel.: +41 44 632 27 38; Fax: +41 44 632 11 76; Email: [email protected]
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1: Department of Mechanical and Process Engineering, ETH Zurich, 8092 Zurich, Switzerland
2: Department of Mechanical Engineering, University College London (UCL), Torrington Place, London WC1E 7JE, UK
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Abstract
Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits
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during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip which adversely affects the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a one-dimensional, semi-empirical approach for quick design of a
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microchannel heat sink for targeted, energy efficient liquid cooling of hotspots in microprocessors. Our approach enables targeted manipulation of the local cooling capacity in the microchannel heat sink, which in turn minimizes the chip temperature gradient. The method is formulated to design a heat sink for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of
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microchannel widths and flow rate distribution for various zones of the power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows
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uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting design estimate significantly reduces the effort involved in designing hotspot-targeted heat sinks. Keywords: Microchannels, Hotspot-targeted cooling, Electronics cooling, Hotspots 1. Introduction
Moore’s law has driven the performance increase in silicon microprocessors, at least until the middle of the last decade [1, 2]. However, the inability to follow the Dennard scaling for supply voltage while downscaling the transistor dimensions has progressively increased chip heat flux dissipation densities [3], inturn motivating a shift in the focus of heat transfer community from air cooling to single and two-phase -1-
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liquid cooling to maintain chip reliability [4, 5]. Starting with the seminal work of Tuckerman and Pease [6], liquid cooling of integrated circuits has been extensively researched including investigations on traditional microchannel (TMC) heat sinks and manifold microchannel (MMC) heat sinks. In TMC heat sinks, the
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coolant enters the heat transfer structure through a single inlet and leaves through a single outlet [7]. In MMC heat sinks, the coolant circulates through multiple and alternating inlet and outlet slot nozzles thus improving the heat transfer at comparatively lower pressure drops. [8-12].
Most of the research on liquid cooling of chips has focused on maximum junction temperature J , max
) reduction under uniform heat flux dissipation conditions. However, it is also necessary that the chip
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temperature is spatially as uniform as possible (i.e. approaching the isothermal chip condition) as large
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temperature gradients increase thermal stresses in the chip to substrate or heat sink interface, reduce electronic reliability in regions of high temperature and create circuit imbalances in CMOS (Complementary metal–oxide–semiconductor) devices [5]. A few studies have focused on reducing temperature non-
(
)
uniformity across the microprocessor ∆TJ ,max = TJ ,max − TJ ,min ; however, under a uniform chip heat flux
[13-15].
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map which have reduced relevance for current and future microprocessor architectures as described below
The large increase in chip heat flux dissipation in the last decade forced an industry-wide shift from serial to multicore microprocessors in order to continue the improvement in chip performance [16, 17]. In a
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typical multicore microprocessor, most of the processing power is concentrated in specific regions of the chip called as cores. As a result, these cores dissipate heat flux that is many times higher in magnitude than
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the heat flux dissipated by the rest of the chip. The cores are termed as hotspots while the rest of the chip is referred to as background. This non-uniform heating of the chip increases the criticality of chip temperature non-uniformity as compared to serial microprocessors. A few single phase liquid cooling approaches have been proposed in the past for preferential cooling of hotspots (termed as hotspot-targeted cooling) with varying degree of success [18-20]. Most of these strategies involve conventional cooling with heat sinks wherein the heat sinks are attached to the back of the chip using a suitable thermal interface material (TIM), commonly referred to as chip backside-attached
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cooling [4, 11]. However, the coolant can also be circulated through microchannels etched into the back of the chip. This approach, termed as embedded liquid cooling (ELC) is highly effective in targeting the hotspots due to a significant reduction in thermal resistance caused by the elimination of the TIM. [21-23].
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In our recently reported work, we proposed a novel liquid cooled microchannel heat sink design that targets the cooling over the hotspots and thus minimizes the chip temperature non-uniformity in a highly energy efficient manner. The design was obtained through an experimentally validated three-dimensional computational fluid dynamic (CFD) approach coupled with response surface (RSM) based optimization [24].
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In this paper, we propose a one-dimensional semi-empirical modeling approach for quick estimation of the hotspot-targeted microchannel heat sink design that can serve as an initial design for the CFD and RSM
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based optimization. The model provides a computationally efficient method to quickly obtain an estimate for microchannel and flow rate distributions required for the design. The model is formulated as a generalized design method and is applicable to conventional as well as ELC heat sinks on one hand and TMC as well as MMC heat sinks on the other. In section 2, we describe the generalized semi-empirical design approach. Section 3 presents an exemplar design of water-cooled TMC heat sink for a microprocessor power map
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having multiple hotspots. Section 4 presents the design of a water-cooled MMC heat sink for a modern day multicore microprocessor. Finally, section 5 briefly discusses the applicability of the proposed model. 2. Semi-empirical design method
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Consider an arbitrary microprocessor power map as shown in Fig.1. In the figure, each shaded area represents a region dissipating a different level of heat flux that is many times higher than that dissipated in
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the unshaded area (background). This power map can be discretized such that each cell of the discretized map encompasses an area of nearly constant heat flux. Figure 2(a) illustrates the coarsest level of discretization for the power map in Fig. 1 and Fig. 2(b) illustrates the (i,j)th cell and the nomenclature adopted in this work for the discretized power map where Q(′′i , j ) is the heat flux dissipation in the (i,j)th i
cell, m is the total coolant flow rate and φi is the fraction of the total flow directed to flow through the ith row. Figure 2(c) shows a schematic of the flow distribution in parallel zones as per the discretization in ycoordinate in Fig. 2(a). Each ith zone consists of parallel microchannels of varying widths wc ,( i , j ) in the jth
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cell along the flow in x-direction as per the heat flux distribution Q(′′i , j ) .
Figure 1: An arbitrary non-uniform power map with regions of high heat flux The discretization can be refined later, depending upon the desired resolution of the calculated temperature map. However, the highest degree of refinement is limited by the following constraint:
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∆yi ≥ wc ,max + ww,max
(1)
where wc ,max and ww ,max are the upper limits of the microchannel and wall widths respectively, for the heat
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sink design.
(a)
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(b)
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(c)
Figure 2: (a) Coarsest discretization of the power map into n x m cells (b) (i,j)th cell of the discretized power map (c) Schematic of the flow distribution in the parallel flow zones as per the discretization from (a). With the flow direction as shown in Fig. 2(b), the average coolant temperature in the (i,j)th cell
T f ,( i , j ) is given by Eq.(2).
j −1
T f ,(i , j ) = T f ,in + ∑ k =1
Q(′′i ,k ) ∆yi ∆xk i
φi m c p , f
+
Q(′′i , j ) ∆yi ∆x j i
(2)
2φi m c p , f
where T f ,in is the coolant inlet temperature. Next, we assume negligible heat spreading between the -5-
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junctions and the base of the heat sink. This is the most important assumption in this model as it allows the flow of heat from junctions to the coolant to be treated as one-dimensional. Hence the average junction
TJ ,( i , j ) = T f ,( i , j ) + Q(′′i , j ) Rλ′′ + Q(′′i , j ) Rα′′,( i , j )
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temperature in the (i,j)th cell TJ ,( i , j ) is obtained as below:
(3)
Here Rλ is the total conduction resistance between the junctions and the base of microchannels and is given by the summation of all the conduction resistances in series (such as those due to the silicon chip thickness,
Rλ′′ = ∑
∆zl λl
(4)
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l
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the TIM and the heat sink base):
Rα′′,( i , j ) is the convective resistance for heat transfer to the coolant in the (i,j)th cell. Accounting for the fin resistance and assuming adiabatic fin tops, Rα′′,( i , j ) is given by [10]:
wc ,(i , j ) + ww,(i , j )
α(i , j ) wc ,(i , j ) + 2α(i , j ) hc γ(i , j )
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Rα′′,(i , j ) =
(5)
where hc is the microchannel depth, α( i , j ) is the local convective heat transfer coefficient and γ(i , j ) is the local fin efficiency. γ(i , j ) is calculated as below:
tanh ( mhc )
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γ(i , j ) =
mhc
, m=
2α(i , j ) λw ww,(i , j )
(6)
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and α( i , j ) is given by:
α(i , j ) =
Nu D ,( i , j ) λ f Dc ,( i , j )
(7)
Here Nu D ,( i , j ) is the local Nusselt number defined in terms of Dc,(i , j ) , an equivalent length scale for the microchannel cross-section. The definition for Dc ,(i , j ) depends upon the form of correlation available for Nu D ,( i , j ) . The thermal resistances in Eq. (3) can be compared in terms of an order of magnitude analysis for a typical modern day silicon microprocessor cooled by a thin backside-attached copper heat sink or by
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ELC [10, 24]. The following relevant parameters are used for this comparison: α ≈ 1 − 5 × 104 W/m2K,
∆zCu = 1 mm, ∆zTIM = 10 μm, ∆zSi =525 μm, λCu =400 W/m.K, λTIM = 10 W/m.K, λSi =140 W/m.K,
wc = ww = hc ≈ 100 μm [4, 10, 24]. With these parameters, the various resistances compare as Rα′′ (13 –
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67 mm2K/W) > Rλ′′, Si (3.8 mm2K/W) > Rλ′′,Cu (2.5 mm2K/W) > Rλ′′,TIM (1 mm2K/W). In addition to these
′′ = W ( wc + ww ) mc ɺ p . For a 2 × 2 cm2 chip and resistances, the bulk resistance can be calculated as Rbulk ′′ is 0.06 mm2K/W, the least of all resistances. Finally, the total coolant (water) flow rate of 1 L/min, Rbulk
( R′′
total
′′ + Rα′′ + Rλ′′,total ) can be compared for chip backside-attached and ELC = Rbulk
(
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total thermal resistance
)
lies in the range
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′′ = Rbulk ′′ + Rα′′ + Rλ′′,Cu + Rλ′′,TIM + Rλ′′, Si approach. For chip backside-attached cooling, Rtotal
≈ 20 − 74 mm2K/W. On the other hand for ELC, Rλ′′,Cu and Rλ′′,TIM are eliminated and Rλ′′, Si reduces to 3
′′ reduces to ≈ 16 − 70 mm2K/W, a reduction of up to mm2K/W (as ∆zSi =525 µm - hc ). As a result Rtotal 20% as compared to backside-attached cooling at the lower end of the range of heat transfer coefficients. With these thermal characteristics of the heat sink in place, the design of the hotspot-targeted heat
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i
sink involves determination of geometrical parameters wc ,(i , j ) , ww,(i , j ) and operational parameters m and φi such that the maximum junction temperature TJ ,max , as well as chip wide temperature gradient ∆TJ ,max are
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minimized, while satisfying the following constraints
wc ,min ≤ wc ,( i , j ) ≤ wc ,max ww,min ≤ ww,( i , j ) ≤ ww,max
(8)
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∆P ≤ ∆Plimit
where wc ,min and ww ,min are the lower limits for microchannel and wall widths respectively and ∆Plimit is the upper limit for the overall pressure drop. The geometrical and operational design parameters are determined by separately considering the terms in Eq. (3) as discussed in the following subsections. 2.1 Determination of flow distribution ϕ i The first step in minimizing TJ ,max and ∆TJ ,max is minimization of bulk resistance that drives the increase in coolant temperature T f ,( i , j ) (the first term in Eq. (3) and given by Eq.(2)). This is achieved -7-
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by equalizing the rise in fluid temperature T f ,(i ,m) − Tf ,in for all n rows. This gives n equations in n unknown variables ϕ i : n
∑ϕ i =1
i
=1 (9)
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Q(′′i ,m ) ∆xm ∆y1 m −1 Q′′ ∆x ∆yi m −1 ′′ ′′ k ) ∆xk + (1, m ) m for i = 2 to n Q x Q(1, ∆ + = ∑ ∑ k (i ,k ) 2 2 ϕi k =1 ϕ1 k =1 With ϕ i determined as above, T f ,( i , j ) in Eq. (3) are fixed.
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The second term Q(′′i , j ) Rλ′′ is fixed for a given power map and cooling architecture. Hence, only the
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convective resistance term Q(′′i , j ) Rα′′,( i , j ) can be controlled which leads to determination of the channel widths wc ,(i , j ) as explained in the following subsection. 2.2 Determination of channel widths wc,(i , j )
In order to reach a unique solution for wc,(i , j ) , the microchannel wall widths ww,(i , j ) can be independently fixed such that the overall pressure drop is minimized. This gives:
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ww,(i , j ) = ww, min
(10)
With the wall widths fixed as above, the distribution of junction temperatures TJ ,(i , j ) is determined
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only by the distribution of channel widths wc ,(i , j ) through the convective resistance term in Eq. (3). This term is minimized under the following condition: (11)
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′′ Rα′′,min = Qmin ′′ Rα′′,max Q(′′i , j ) Rα′′,( i , j ) = Qmax
Eq. (11) distributes convective resistance according to the heat flux map. The minimum convective
′′ , resistance Rα′′,min corresponds to the finest microchannels wc ,min , assigned to the (i,j)th cell with Q(′′i , j ) = Qmax and is given by:
Rα′′, min =
wc ,min + ww,min αmax wc ,min + 2αmax hc γmin
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It should be noted that the choice of the finest microchannel dimension wc ,min will depend on the heat sink material (for example copper in case of conventional backside-attached heat sinks or silicon in case of ELC) and the fabrication process. For example, in case of ELC, for an aspect ratio limit of 10 for deep
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reactive ion etching and a microchannel depth of 300 microns, the finest microchannel dimension is limited to 30 microns [24].
Eqs. (11) and (12) along with Eqs. (5) and (10) result in following nm − 1 non-linear equations for
nm − 1 unknown microchannel widths wc ,(i , j ) :
α(i , j ) wc ,(i , j ) + 2α(i , j ) hc γ(i , j )
=
′′ Rα′′, min Qmax Q(′′i , j )
(13)
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with γ(i , j ) and α(i , j ) given by Eqs. (6) and (7).
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wc ,(i , j ) + ww,min
Since the channel widths change according to the change in heat flux along flow direction, it is important that the coolant flows uninterrupted in every row (i.e. does not run into a wall). This is ensured by simply modifying wc,(i , j ) values from Eq. (13) such that the microchannel pitch in any (i,j)th cell
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wc ,(i , j ) + ww,min is related to the pitches in adjacent upstream and downstream cells, wc ,(i , j −1) + ww,min and wc ,(i , j +1) + ww,min , through integral multiples.
i
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2.3 Determination of total coolant flow rate m
i
i
The only design parameter that remains to be determined is the total coolant flow rate m . The m
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can be fixed such that the maximum pressure drop among all the n rows does not violate the pressure drop constraint in Eq. (8) i.e.:
max ( ∆Pi ) ≤ ∆Plimit i
(14)
Pressure drops ∆Pi can be expressed in terms of Fanning friction factor, as below: i 2 µ f ( f Re D )(i , j ) ∆x j φi m p(i , j ) ∆Pi = ∑ 2 ρ f ∆yi Ac ,(i , j ) D j =1 c ,( i , j ) m
(15)
where p( i , j ) = wc ,( i , j ) + ww, min is the microchannel pitch and Ac ,( i , j ) = wc ,( i , j ) hc is the channel cross-9-
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i
sectional area. Equations (14) and (15) determine the highest allowable m . 2.4 Passive flow throttling to achieve coolant distribution ϕ i The pressure drops ∆Pi are bound to be different due to unequal flow distribution ϕ i and
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microchannel widths in all n rows. As a result, when coolant is supplied to such a microchannel heat transfer structure design, most of the coolant will escape through rows with wider microchannels due to smaller resistance to flow from these rows. Hence, the required flow distribution ϕ i , as calculated in subsection 2.1,
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will not be realized. This flow distribution can only be realized if the flow resistances of all parallel n rows are equalized when the coolant is distributed according to ϕ i [24]. This can be achieved by introducing
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additional resistances in all rows such that:
∆Pi + ∆Pi * = max ( ∆Pi ) = ∆Plimit i
(16)
where ∆Pi is the pressure drop due to the additional flow resistance introduced in the ith row. This is a key *
idea in our approach to hotspot targeted cooling.
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The additional resistances can be flow throttling zones either in the manifold that supplies the coolant or within the microchannel structure itself in the form of fine channels. In the latter case, however, it has to be ensured that the flow throttling channels do not interrupt the flow as discussed in section 2.2. Additionally, the throttling zones have to be positioned such that the enhanced cooling caused by the fine
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* microchannels does not adversely affect ∆TJ ,max achieved in section 2.2 [24]. Note that ∆Pi = 0 for the ith * row with ∆Pi = max ( ∆Pi ) . Similar to Eq.(15), ∆Pi can also be expressed as below:
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i
i * 2 µ ( f Re D )i L*i φi m ∆Pi = 2 * * * ρ A N ( Di ) f i i *
(17)
where the superscript ‘*’ indicates geometrical and operational parameters for the flow throttling zone. Then, by using Eq.(16), the geometrical parameters for the flow throttling zones can be calculated. With this, the design of a hotspot-targeted microchannel heat sink is completed. 2.5 Design for developed and developing flow
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The design method discussed above can be used for both TMC as well as MMC heat sinks. The critical difference between the two is in terms of the hydrodynamics due to which the semi-empirical design method is used differently for the two types of heat sinks.
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2.5.1 Developed flow In TMC heat sinks, the flow enters the microchannel heat transfer structure from one side, flows the entire length of the microchannels and exits from the other side. The flow develops quickly and hence can be assumed to be fully developed inside the microchannels. Since friction factors and Nusselt number for fully
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developed flow are independent of the Reynolds number and are only dependent on the geometry of the i
microchannels, wc ,( i , j ) values determined by Eq. (13) are independent of m and the heat sink design is
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completed in a single iteration by sequentially following the steps from section 2.1 to 2.4. 2.5.1 Developing flow
For MMC heat sinks, the flow inside the microchannels is developing for a large part of the microchannel length due to the relatively short channel length available between each pair of inlet and outlet slot nozzles [10, 11]. In this case, due to the dependence of Nusselt number and Fanning friction factor-
( f Re D )
on Reynolds number, the heat transfer coefficients α(i , j ) and hence
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Reynolds number product
i
the microchannel widths wc ,( i , j ) are no longer independent of m . This necessitates the following recursive i
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procedure once the required flow distribution is determined using Eq.(9): (a) Assume m (b) determine
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wc ,( i , j ) using Eq. (13) in section 2.2 and revise wc ,( i , j ) values to ensure uninterrupted flow (c) use Eqs. i
(14) and (15) in section 2.3 to check if the pressure drop constraint is satisfied - if yes, then increase m , i
repeat steps (a)-(c) and iterate to obtain the highest m satisfying the pressure drop constraint (d) calculate the configuration of flow throttling zones using Eqs. (16) and (17) in section 2.4. In the following two sections, we demonstrate the application of the semi-empirical design method for TMC and MMC heat sink cooling architecture. 3. Exemplar design for an arbitrary power map cooled by TMC heat sink In this section, we illustrate the use of the one-dimensional model to design a hotspot targeted - 11 -
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embedded TMC structure. We consider a highly non-uniform power map shown in Fig. 3 with W = 1.6 cm and L = 1.2 cm . The coolant is assumed to be water with the constant properties: ρ f = 998.2 kg/m3,
µ f = 0.001 Pa-s, and c p , f = 4180 J/kg-K. The thermal conductivity of silicon is also assumed to be
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constant ( λl =150 W/m-K). Following design constraints have been adopted for Eq. (8):
wc ,min = ww,min = 30 µm, ∆Plimit =0.5 bar. Considering a maximum feasible aspect ratio of 10 for microchannels [25], the microchannel height hc is assumed to be 300 µm and hence the unetched chip
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thickness ∆zl is 225 µm for a standard 525 µm thick silicon wafer. Flow is assumed to be fully
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developed and the correlations for Nu and f Re , for rectangular channels, are adopted from Shah and London [26]. These correlations are defined in terms of hydraulic diameter which can be expressed as:
Dc ,(i , j ) =
(w
2wc ,(i , j ) hc
+ ww, min
)
(18)
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c ,( i , j )
Figure 3: An exemplar non-uniform power map with heat flux dissipation in W/cm2. Using the coarsest level of discretization similar to Fig. 2, and following the sections 2.1 and 2.2, we obtain a set of non-linear system of equations for wc ,( i , j ) (Eq. (13)) that is solved using MATLAB - 12 -
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(R2013b). The wc ,( i , j ) values so obtained are modified to ensure uninterrupted coolant flow (refer to the section 2.2). The resulting hotspot-targeted wc distribution is shown in Fig. 4. i
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This is followed by the determination of maximum m (refer to the section 2.3). The i
∆Plimit constraint limits m to 1.17 g/s (0.07 l/min). Figure 5(a) shows the temperature map of the chip corresponding to the hotspot-targeted microchannel structure at 0.07 l/min. The performance of the optimal design is evaluated against a base case consisting of uniformly fine, embedded microchannels
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( wc = ww = 30 µm) and uniform flow distribution at the same level of pumping power as the hotspottargeted design. The base case represents the limit of TMC heat sink cooling. The temperature map for the
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base case is shown in Fig. 5(b). Figure 5 illustrates that, as compared to the base case, hotspot-targeted design reduces TJ ,max from 79.6 ℃ to 55.3 ℃ and ∆TJ ,max from 57.5 ℃ to 31.4 ℃ - an improvement of
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45 %.
Figure 4: wc distribution for the power map in Fig. 3
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(a)
(b) Figure 5: Temperature maps (a): hotspot-targeted design (b) base case. The same temperature scale for both the figures illustrates reduction in TJ ,max and ∆TJ ,max . Coolant flows from left to right.
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(a)
(b)
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(c)
Figure 6(a): Throttling zones towards coolant outlet (compare with Fig. 4) (b) Temperature map for the
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design shown in Fig.6(a) (compare with Fig. 5(a)) (c) Schematic of the throttling in ith row with two
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* microchannels of width wc ,(i ,m ) merging into a fine microchannel of width wc ,i
Following section 2.4, the pressure equalization is achieved by introducing flow throttling zones in the microchannel structure. The throttling zones are positioned towards the coolant outlet and are formed by merging every two channels in each row into a fine microchannel of 30 µm width, i.e. wc*,i =30
(
)
µm and ww,i = 2 wc,(i ,m) + ww, min − wc,i . With wc*,i and ww* ,i fixed, the throttling zone lengths Li are *
*
(
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obtained using Eqs. (16) and (17) with Di* = 2 wc*,i hc
) (w
* c ,i
)
+ ww* ,i and Ni* = ∆yi
*
(w
* w,i
)
+ wc*,i .
Figure 6(a) shows the microchannel structure along with flow throttling zones in black color. Figure 6(b) shows the temperature map for the complete design which clearly shows that the additional cooling from
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the throttling zones does not adversely affect the performance of the hotspot targeted design. Figure 6(c) shows a schematic of the flow throttling microchannels formed by merging two microchannels into a fine
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microchannel in the ith row.
4. Design for a multicore microprocessor power map cooled by MMC heat sink In this section, we demonstrate the application of the semi-empirical model for the design of an
MMC heat sink for hotspot-targeted cooling of a modern day multicore microprocessor. 4.1 One-dimensional model calibration The one-dimensional semi-empirical equations (Eqs. (2) and (3)) can model the thermal performance of an MMC heat sink for uniform power dissipation map [10]. Here, we calibrate and evaluate this model for highly non-uniform power maps against experimental results from Sharma et al. [24], who - 16 -
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used a non-uniform power map as depicted in Fig. 7(a). The areas marked hotspots are regularly distributed and dissipate 150 W/cm2 while the background dissipates 20 W/cm2. This power map is representative of a typical level of heat flux contrast in modern day multicore microprocessors. This power map is cooled by an
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MMC heat sink having uniform embedded microchannel structure (ELC, refer section 1) with wc = 35 µm,
ww = 25 µm, hc = 250 µm and ∆zl = 275 µm. The flow is distributed uniformly across the microchannels structure i.e. fraction of flow in each microchannel is φ = ( wc + ww )
( yn − y0 ) . The slot nozzles of the heat
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sink are arranged such that inlet slot nozzles are positioned over the hotspots to concentrate the jetimpingement cooling in these areas and outlet slot nozzles are positioned over the background area in-
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between the cores [24]. Figure 7(a) shows the placement of one pair of inlet and outlet slot nozzles and the direction of flow in the microchannels from inlet to outlet [24].
To model the convective flow resistance Rα'' ,( i , j ) in Eq. (3) for simultaneously developing microchannel flow between inlet and outlet slot nozzles, we adopt the Nusselt number correlation from
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Muzychka and Yovanovich, 2004 [27] for Nu D ,( i , j ) in Eq. (7). Since this correlation is based on square
(a)
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(b)
Figure 7(a) Non-uniform power map and placement of one inlet-outlet slot nozzle pair. Arrow indicates direction of flow. (b) Calibration of one-dimensional against experimental measurements for ∆TJ ,max and
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TJ ,max
root of flow area as the characteristic length, we have Dc ,( i , j ) =
wc ,( i , j ) hc . However, these correlations
require calibration as explained below to adequately capture the heat sink thermal performance.
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As mentioned in section 2, Eq. (3) does not account for heat spreading which becomes significant as the heat flux contrast increases in non-uniform power maps of the kind shown in Fig. 7(a).
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Moreover, the NuD correlation does not account for the jet impingement effect near the inlet slot nozzle and thus cannot accurately model the streamwise profile of the local heat transfer coefficient. These two effects combine to cause inaccuracy in the modeling of total thermal resistance and thus the junction temperature map. In order to improve the one-dimensional model accuracy, we calibrate the
NuD correlation by introducing a modified channel height hc* = chc [10]. The empirical constant c is then calibrated to achieve a close match for TJ ,max as well as ∆TJ ,max against experimentally measured values as shown in Fig. 7(b). The model predictions in the figure pertain to a fixed value of c for all the
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flow rates. Figure 7(b) compares the modelled and measured values as a function of the overall volumetric i
i
flow rate V = m ρ f . For the range of investigated flow rates, the calibrated model is able to capture
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TJ ,max and ∆TJ ,max within 3.5 ℃. The deviation of model predictions from experimental measurements is higher at lower flow rates. This is because of the strong effect of heat spreading at lower flow rates due to higher convective resistance Rα'' to heat transfer in the microchannel structure.
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A further improvement in accuracy of model predictions would require switching to threedimensional conjugate heat transfer CFD approach which alleviates the above described limitations of the
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one-dimensional model (refer [24] for further details of three-dimensional modeling). However, the purpose of the one-dimensional model is to arrive at a quick initial estimate of the MMC heat sink microchannel distribution using the design approach explained in sections 2.1-2.4. We demonstrate in the next section, that in spite of the assumptions involved in one-dimensional equations, the one-dimensional semi-empirical design approach achieves a sound initial estimate of the hotspot-targeted MMC heat sink
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design.
4.2 Hotspot-targeted MMC heat sink design
This section describes the application of the one-dimensional semi-empirical model for the design of a hotspot-targeted MMC heat sink for a non-uniform power map. We consider the power map shown in Fig.
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7(a) with hotspots now dissipating 300 W/cm2 while the background dissipates 20 W/cm2 of heat flux as
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before. The design constraints are chosen to be: wc ,min = ww,min = 30 µm, ∆Plimit =0.35 bar [28]. Rest of the configuration of MMC heat sink is same as described in section 4.1. Along with the calibrated Nu correlation from previous section for modeling the thermal performance, we adopt the
f Re correlation, for
simultaneously developing flow from Muzychka and Yovanovich, 2004 [27], to model the hydrodynamic performance of the heat sink.
Since the hotspots are regularly distributed, the analysis considers a unit cell of the power map between the inlet-outlet slot nozzle pair marked in Fig. 7(a). The simultaneously developing flow necessitates the use of the recursive procedure described in section 2.5.2 for design of the heat sink. We
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describe the results of this procedure in the following.
(a)
(b)
Figure 8: (a) Hotspot-targeted wc distribution for the power map in Fig. 7(a). Throttling zones are shown
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in black color. (b) Comparison of TJ distribution for the hotspot-targeted and base MMC heat sink designs
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Equation (9) yields the coolant flow distribution whereby 86 % of the flow needs to be diverted to i
the two hotspots in the unit cell (43 % to each hotspot). Then, progressively increasing values of m are tested and for each value, wc ,( i , j ) distribution is calculated and the pressure drop constraint ∆Plimit is verified. Imposition of ∆Plimit yields a maximum feasible water flow rate of 0.026 kg/s (1.58 l/min). Figure 8(a) shows the resulting hotspot-targeted microchannel width distribution in the unit cell of the hotspottargeted MMC heat sink design. The throttling zones are shown in black color and have the configuration:
(
)
wc*,i = 30 µm, ww* ,i = 2 wc ,(i ,m ) + ww,min − wc*,i and L*i = 1.45 mm.
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Figure 8(b) compares the junction temperature map for the hotspot-targeted design TJ ,( i , j ) at i
maximum feasible m against the corresponding map for a base MMC heat sink design at the same level of pumping power. The base design is chosen to have a uniformly fine, embedded microchannel structure
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with wc = ww = 30 µm and uniform flow distribution to represent the limit of conventional ELC [24]. The hotspot-targeted MMC heat sink design reduces ∆TJ ,max from 21.3 ℃ to 14.9 ℃, an improvement of 30 %, and leads to a significantly more uniform temperature map. Note that although the coarsest level of
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discretization is used to generate the wc map in Fig. 8(a) to isolate areas of spatially constant heat flux (refer
resolution in the TJ map in Fig. 8(b).
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to section 2 and Fig. 2(a)), a finer level of discretization in x-direction has been used to obtain higher
A comparison of the TJ maps in Fig. 8(b) with the corresponding maps in [24] indicates that the calibrated one-dimensional model is limited in terms of the accuracy of the predicted TJ map as compared to detailed three-dimensional CFD modeling approach. However, the wc map shown in Fig.
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8(a) is similar to the distribution arrived at in [24] with the detailed CFD and RSM optimization. This shows that the current one-dimensional design approach is sufficient to achieve a good initial condition for detailed optimization thus reducing the iterations involved in CFD based optimization. Since the wc
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distribution, the throttling zone lengths, overall maximum feasible coolant flow rate and the chip temperature map are obtained by using approximate correlations for simultaneously developing flow in
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the semi-empirical one-dimensional model, these values can be refined by subsequent detailed CFD based optimization to arrive at the final hotspot-targeted heat sink design and its performance. In terms of practical implementation of the hotspot-targeted microchannel cooling concept, we also mention here that the non-uniform wc map is also feasible from fabrication considerations, especially for ELC as shown through an experimental study by Sharma at al. [29] for the power map in Fig. 7(a). 5. A note on the significance of thermal spreading As discussed in previous section, the absence of heat spreading effect in the one-dimensional model is the main contributor to inaccuracy in model predictions. Although closed-form estimates for - 21 -
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thermal spreading are available in the literature, these are mostly limited to the assumption of spatially uniform cooling from the microchannel heat transfer structure side and hence are not applicable to the present problem involving non-uniform distribution of the cooling capacity adapted to the chip power map
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[30-32]. Such systems also require three-dimensional conjugate heat transfer computations to estimate the extent of thermal spreading. However, a simple thermal resistance network analysis can be used to identify the conditions under which thermal spreading may be neglected for non-uniform power maps cooled by spatially adapted heat transfer structures.
( ∆x1 + ∆x2 ) × ∆y as
shown in
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Consider a microprocessor power map with overall dimensions
Fig. 9(a). It dissipates heat fluxes Q1'' , Q2'' , with Q1'' > Q2'' , on strips of areas A1 = ∆x1∆y and
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A2 = ∆x2 ∆ y . The total vertical thickness of the unetched chip is ∆z and this power map is cooled by a non-uniform microchannel structure and flow distribution that achieves effective convective resistances
Rα'' ,1 and Rα'' ,2 over areas A1 and A2 , respectively
( where R
'' α
)
= Rα A = 1 αeff . We assume that the
coolant flow is distributed among the two strips such that the bulk resistance is minimized. Hence,
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following section 2.1, the fluid temperatures in both the strips are equalized at all y coordinates. Figure
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9(b) shows the resistance network at any coordinate y for a thin strip of width dy (shown in Fig. 9(a)).
(a) (b) Figure 9: (a) A theoretical non-uniform chip power map subjected to non-uniform cooling. Coolant flows along y-coordinate (b) the thermal resistance network at any y-coordinate.
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′′ is the local lateral heat flux that leads to thermal spreading, Rλ′′ = ∆z λ is the conduction Here Qsp
′′ is the local resistance to lateral flow of heat which can be resistance of the unetched chip and Rsp approximated as
Lx λ with Lx ≈ 0.5 ( ∆x1 + ∆x2 ) . The infinitesimal areas are dA1 = ∆x1dy ,
(19).
Q1′′ Rα′′,1 − Q2′′ Rα′′,2 ∆x L ∆x Rα′′,1 + Rα′′,2 1 + x 1 ∆x2 λ∆z
(19)
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∆x Qsp′′ = 1 ∆z
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dA2 = ∆x2 dy and dAsp = ∆zdy . This network can be solved to obtain the lateral heat flux Qsp′′ in Eq.
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Equation (19) provides the following qualitative conditions under which the thermal spreading is insignificant. Thus: (a)
Qsp′′ is minimized if the convective resistances are scaled according to Eq. (11) as it reduces the numerator in the above equation. In fact, if the hotspots extend the entire flow length ∆y as in Fig. 9
′′ would be reduced to a negligible value as the convective and the flow is fully developed, Qsp
(b)
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resistance scaling will hold for all y .
Qsp′′ reduces with the size of the hotspots (reducing ∆x1 ) as the power map will approach a spatially uniform heat flux dissipation condition.
′′ dAsp reduces with the decrease in unetched chip thickness ∆z . The net lateral heat transfer Qsp
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6. Conclusions
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(c)
A 1-dimensional model for quick design of a liquid cooled, hotspot-targeted microchannel heat
sink was presented. The model is a generalized design method for developed and developing flow situations encountered in TMC and MMC heat sinks respectively and it is applicable to arbitrary chip power maps encountered in serial and multicore microprocessors. The approach is equally applicable to both conventional and embedded cooling heat sinks. The potential of the model was demonstrated first by an exemplar design for a TMC heat sink with developed flow in microchannels. For developing flow, the model was calibrated against existing experimental results and the calibrated model was used to design a
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MMC heat sink with embedded microchannels. Lastly, a simple analysis of thermal spreading in nonuniform microprocessor power maps was presented to highlight the conditions under which heat spreading
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becomes insignificant thus increasing the accuracy of the one-dimensional modeling approach.
Nomenclature
cross-sectional area of each parallel flow path in the throttling zone (m2)
cp
specific heat capacity (J/KgK)
D
equivalent cross-sectional length scale (m)
i
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Ai*
total coolant flow (kg/s)
hc
microchannel height (m)
i, j,k
indices
L*i
length of throttling zone in ith row (m)
n, m
number of rows and columns in the discretized power map
Ni*
number of parallel flow paths in throttling zone
NuD
Nusselt number defined for D
Qi'', j
heat flux in the (i,j)th cell (W/m2)
Qsp''
thermal spreading heat flux (W/m2)
∆P
pressure drop (Pa)
Rα′′ ′′ Rbulk
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Rλ′′
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m
conduction resistance (m2K/W) convection resistance (m2K/W) bulk resistance (m2K/W)
f Re D
Fanning friction factor-Reynolds number product
TJ
junction temperature (K)
Tf
coolant temperature (K) - 24 -
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wc
microchannel width (m)
ww
microchannel wall width (m)
W ×L
microprocessor chip dimensions (m2)
x j , yi
coordinates (m)
∆zl
thickness of lth layer (m)
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Greek symbols
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∆x j , ∆yi cell diemnsions of discretized power map (m)
heat transfer coefficient (W/m2K)
c
microchannel
D
equivalent cross-sectional length scale
ϕi
fraction of m directed into the ith row
γ
fin efficiency
λ f , λw
fluid and solid thermal conductivities in heat sink (W/mK)
λl
thermal conductivity of lth layer in heat transfer path from junctions to microchannel base
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α
(W/mK)
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i
dynamic fluid viscosity (Pa.s)
ρf
fluid density (kg/m3)
f max min
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Subcripts
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µf
fluid
maximum minimum
Acronyms CMOS complementary meatl-oxide-semiconductor ELC
embedded liquid cooling
MMC manifold microchannel - 25 -
RSM
response surface methodology
TIM
thermal interface material
TMC
traditional microchannel
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References
[1] G.E. Moore, Cramming More Components Onto Integrated Circuits, Electronics, 38 (1965) 114-117. [2] S.H. Fuller, L.I. Millett, Computing Performance: Game Over or Next Level?, Computer, 44 (2011) 3138. Directions, Solid-State Electron., 51 (2007) 518-525.
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[3] R.H. Dennard, J. Cai, A. Kumar, A Perspective on Today’s Scaling Challenges and Possible Future [4] C.S. Sharma, S. Zimmermann, M.K. Tiwari, B. Michel, D. Poulikakos, Optimal Thermal Operation of
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Liquid-cooled Electronic Chips, Int. J. Heat Mass Transfer, 55 (2012) 1957-1969.
[5] JEDEC, Failure Mechanisms and Models for Semiconductor Devices, in: JEDEC (ed.), 2010, pp. 1-9,6872.
[6] D.B. Tuckerman, R.F.W. Pease, High-Performance Heat Sinking for VLSI, IEEE Electron Device Lett., 2 (1981) 126-129.
[7] P.-S. Lee, S.V. Garimella, D. Liu, Investigation of Heat Transfer in Rectangular Microchannels, Int. J. Heat Mass Transf., 48 (2005) 1688-1704.
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[8] D. Copeland, M. Behnia, W. Nakayama, Manifold Microchannel Heat Sinks: Isothermal Analysis, IEEE Trans Compon Pack Technol., Part A, 20 (1997) 96-102. [9] J.H. Ryu, D.H. Choi, S.J. Kim, Three-dimensional Numerical Optimization of a Manifold Microchannel Heat Sink, Int. J. Heat Mass Transf., 46 (2003) 1553-1562.
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[10] W. Escher, B. Michel, D. Poulikakos, A Novel High Performance, Ultra Thin Heat Sink for Electronics, Int. J. Heat Fluid Flow, 31 (2010) 586-598. [11] C.S. Sharma, M.K. Tiwari, B. Michel, D. Poulikakos, Thermofluidics and Energetics of a Manifold
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Microchannel Heat Sink for Electronics With Recovered Hot Water as Working Fluid, Int. J. Heat Mass Transfer, 58 (2013) 135-151.
[12] E. Kermani, S. Dessiatoun, A. Shooshtari, M.M. Ohadi, Experimental Investigation of Heat Transfer Performance of a Manifold Microchannel Heat Sink for Cooling of Concentrated Solar Cells, in:
Electronic
Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 453-459. [13] G. Hetsroni, A. Mosyak, Z. Segal, G. Ziskind, A Uniform Temperature Heat Sink for Cooling of Electronic Devices, Int. J. Heat Mass Transfer, 45 (2002) 3275-3286. [14] C.A. Rubio-Jimenez, S.G. Kandlikar, A. Hernandez-Guerrero, Numerical Analysis of Novel Micro Pin Fin Heat Sink With Variable Fin Density, IEEE Trans. Compon. Pack. Technol., 2 (2012) 825-833. [15] J. Barrau, D. Chemisana, J. Rosell, L. Tadrist, M. Ibañez, An experimental study of a new hybrid jet impingement/micro-channel cooling scheme, Applied Thermal Engineering, 30 (2010) 2058-2066. - 26 -
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[16] H. Esmaeilzadeh, E. Blem, Ren, #233, e.S. Amant, K. Sankaralingam, D. Burger, Power Limitations and Dark Silicon Challenge the Future of Multicore, ACM Trans. Comput. Syst., 30 (2012) 1-27. [17] IBM Unveils New POWER7 Systems To Manage Increasingly Data-Intensive Services, in, Vol. 2013, http://www-03.ibm.com/press/us/en/pressrelease/29315.wss. [18] Y.J. Lee, P.S. Lee, S.K. Chou, Hotspot Mitigating With Obliquely Finned Microchannel Heat Sink---An
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Experimental Study, IEEE Trans Compon Pack Technol., 3 (2013) 1332 - 1341.
[19] T. Brunschwiler, H. Rothuizen, S. Paredes, B. Michel, E. Colgan, P. Bezama, Hotspot-adapted Cold Plates to Maximize System Efficiency, in: 15th International Workshop on Thermal Investigations of ICs and Systems, 2009. THERMINIC 2009. , 2009, pp. 150-156.
[20] P.-S. Lee, S.V. Garimella, Hot-Spot Thermal Management With Flow Modulation in a Microchannel ASME International Mechanical Engineering Congress and Exposition Vol. 2005, ASME,
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Heat Sink, in:
Orlando, Florida, USA, 2005, pp. 643-647.
[21] B. Dang, M.S. Bakir, J.D. Meindl, Integrated Thermal-fluidic I/O Interconnects for an On-chip
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Microchannel Heat Sink, IEEE Electron Device Lett., 27 (2006) 117-119.
[22] K. Etessam-Yazdani, M. Asheghi, H.F. Hamann, Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis, IEEE Trans Compon Pack Technol., 31 (2008) 211215.
[23] Z. Mingyuan, Z.R. Huang, Design of On-Chip Microchannel Fluidic Cooling Structures, in: Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th, 2007, pp. 20172023.
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[24] C.S. Sharma, M.K. Tiwari, S. Zimmermann, T. Brunschwiler, G. Schlottig, B. Michel, D. Poulikakos, Energy Efficient Hotspot-targeted Embedded Liquid Cooling of Electronics, Applied Energy, 138 (2015) 414-422.
[25] M.J. Madou, Fundamentals of Microfabrication : The Science of Miniaturization, 2nd ed., Boca Raton,
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FL : CRC Press 2002.
[26] R.K. Shah, A.L. London, Laminar flow forced convection in ducts, Academic Press, New York, 1978. [27] Y.S. Muzychka, M.M. Yovanovich, Laminar Forced Convection Heat Transfer in the Combined Entry
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Region of Non-Circular Ducts, Journal of heat transfer, Transaction of ASME, 126 (2004) 54-61. [28] E.G. Colgan, B. Furman, M. Gaynes, W.S. Graham, N.C. LaBianca, A Practical Implementation of Silicon Microchannel Coolers for High Power Chips, IEEE Trans. Compon. Pack. Technol., 30 (2007) 218225.
[29] C.S. Sharma, G. Schlottig, T. Brunschwiler, M.K. Tiwari, B. Michel, D. Poulikakos, A novel method of energy efficient hotspot-targeted embedded liquid cooling for electronics: An experimental study, International Journal of Heat and Mass Transfer, 88 (2015) 684-694. [30] Y.S. Muzychka, J.R. Culham, M.M. Yovanovich, Thermal Spreading Resistance of Eccentric Heat Sources on Rectangular Flux Channels, Journal of Electronic Packaging, 125 (2003) 178-185. [31] Y.S. Muzychka, M.M. Yovanovich, J.R. Culham, Thermal Spreading Resistance in Compound and Orthotropic Systems, Journal of Thermophysics and Heat Transfer, 18 (2004) 45-51. - 27 -
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[32] S. Lee, S. Song, V. Au, K.P. Moran, Constriction/ spreading resistance model for electronics packaging,
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in: ASME/JSME Thermal Engineering Conference, Vol. 4, 1995.
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S1359-4311(15)00882-0
DOI:
10.1016/j.applthermaleng.2015.08.086
Reference:
ATE 6971
To appear in:
Applied Thermal Engineering
Received Date: 29 January 2015 Revised Date:
28 May 2015
Accepted Date: 28 August 2015
Please cite this article as: C.S. Sharma, M.K. Tiwari, D. Poulikakos, A simplified approach to hotspot alleviation in microprocessors, Applied Thermal Engineering (2015), doi: 10.1016/ j.applthermaleng.2015.08.086. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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A simplified approach to hotspot alleviation in microprocessors
Chander Shekhar SHARMA 1, Manish K. TIWARI 2, Dimos POULIKAKOS 1,* * Corresponding author: Tel.: +41 44 632 27 38; Fax: +41 44 632 11 76; Email: [email protected]
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1: Department of Mechanical and Process Engineering, ETH Zurich, 8092 Zurich, Switzerland
2: Department of Mechanical Engineering, University College London (UCL), Torrington Place, London WC1E 7JE, UK
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Abstract
Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits
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during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip which adversely affects the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a one-dimensional, semi-empirical approach for quick design of a
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microchannel heat sink for targeted, energy efficient liquid cooling of hotspots in microprocessors. Our approach enables targeted manipulation of the local cooling capacity in the microchannel heat sink, which in turn minimizes the chip temperature gradient. The method is formulated to design a heat sink for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of
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microchannel widths and flow rate distribution for various zones of the power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows
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uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting design estimate significantly reduces the effort involved in designing hotspot-targeted heat sinks. Keywords: Microchannels, Hotspot-targeted cooling, Electronics cooling, Hotspots 1. Introduction
Moore’s law has driven the performance increase in silicon microprocessors, at least until the middle of the last decade [1, 2]. However, the inability to follow the Dennard scaling for supply voltage while downscaling the transistor dimensions has progressively increased chip heat flux dissipation densities [3], inturn motivating a shift in the focus of heat transfer community from air cooling to single and two-phase -1-
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liquid cooling to maintain chip reliability [4, 5]. Starting with the seminal work of Tuckerman and Pease [6], liquid cooling of integrated circuits has been extensively researched including investigations on traditional microchannel (TMC) heat sinks and manifold microchannel (MMC) heat sinks. In TMC heat sinks, the
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coolant enters the heat transfer structure through a single inlet and leaves through a single outlet [7]. In MMC heat sinks, the coolant circulates through multiple and alternating inlet and outlet slot nozzles thus improving the heat transfer at comparatively lower pressure drops. [8-12].
Most of the research on liquid cooling of chips has focused on maximum junction temperature J , max
) reduction under uniform heat flux dissipation conditions. However, it is also necessary that the chip
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(T
temperature is spatially as uniform as possible (i.e. approaching the isothermal chip condition) as large
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temperature gradients increase thermal stresses in the chip to substrate or heat sink interface, reduce electronic reliability in regions of high temperature and create circuit imbalances in CMOS (Complementary metal–oxide–semiconductor) devices [5]. A few studies have focused on reducing temperature non-
(
)
uniformity across the microprocessor ∆TJ ,max = TJ ,max − TJ ,min ; however, under a uniform chip heat flux
[13-15].
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map which have reduced relevance for current and future microprocessor architectures as described below
The large increase in chip heat flux dissipation in the last decade forced an industry-wide shift from serial to multicore microprocessors in order to continue the improvement in chip performance [16, 17]. In a
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typical multicore microprocessor, most of the processing power is concentrated in specific regions of the chip called as cores. As a result, these cores dissipate heat flux that is many times higher in magnitude than
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the heat flux dissipated by the rest of the chip. The cores are termed as hotspots while the rest of the chip is referred to as background. This non-uniform heating of the chip increases the criticality of chip temperature non-uniformity as compared to serial microprocessors. A few single phase liquid cooling approaches have been proposed in the past for preferential cooling of hotspots (termed as hotspot-targeted cooling) with varying degree of success [18-20]. Most of these strategies involve conventional cooling with heat sinks wherein the heat sinks are attached to the back of the chip using a suitable thermal interface material (TIM), commonly referred to as chip backside-attached
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cooling [4, 11]. However, the coolant can also be circulated through microchannels etched into the back of the chip. This approach, termed as embedded liquid cooling (ELC) is highly effective in targeting the hotspots due to a significant reduction in thermal resistance caused by the elimination of the TIM. [21-23].
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In our recently reported work, we proposed a novel liquid cooled microchannel heat sink design that targets the cooling over the hotspots and thus minimizes the chip temperature non-uniformity in a highly energy efficient manner. The design was obtained through an experimentally validated three-dimensional computational fluid dynamic (CFD) approach coupled with response surface (RSM) based optimization [24].
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In this paper, we propose a one-dimensional semi-empirical modeling approach for quick estimation of the hotspot-targeted microchannel heat sink design that can serve as an initial design for the CFD and RSM
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based optimization. The model provides a computationally efficient method to quickly obtain an estimate for microchannel and flow rate distributions required for the design. The model is formulated as a generalized design method and is applicable to conventional as well as ELC heat sinks on one hand and TMC as well as MMC heat sinks on the other. In section 2, we describe the generalized semi-empirical design approach. Section 3 presents an exemplar design of water-cooled TMC heat sink for a microprocessor power map
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having multiple hotspots. Section 4 presents the design of a water-cooled MMC heat sink for a modern day multicore microprocessor. Finally, section 5 briefly discusses the applicability of the proposed model. 2. Semi-empirical design method
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Consider an arbitrary microprocessor power map as shown in Fig.1. In the figure, each shaded area represents a region dissipating a different level of heat flux that is many times higher than that dissipated in
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the unshaded area (background). This power map can be discretized such that each cell of the discretized map encompasses an area of nearly constant heat flux. Figure 2(a) illustrates the coarsest level of discretization for the power map in Fig. 1 and Fig. 2(b) illustrates the (i,j)th cell and the nomenclature adopted in this work for the discretized power map where Q(′′i , j ) is the heat flux dissipation in the (i,j)th i
cell, m is the total coolant flow rate and φi is the fraction of the total flow directed to flow through the ith row. Figure 2(c) shows a schematic of the flow distribution in parallel zones as per the discretization in ycoordinate in Fig. 2(a). Each ith zone consists of parallel microchannels of varying widths wc ,( i , j ) in the jth
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cell along the flow in x-direction as per the heat flux distribution Q(′′i , j ) .
Figure 1: An arbitrary non-uniform power map with regions of high heat flux The discretization can be refined later, depending upon the desired resolution of the calculated temperature map. However, the highest degree of refinement is limited by the following constraint:
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∆yi ≥ wc ,max + ww,max
(1)
where wc ,max and ww ,max are the upper limits of the microchannel and wall widths respectively, for the heat
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sink design.
(a)
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(b)
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(c)
Figure 2: (a) Coarsest discretization of the power map into n x m cells (b) (i,j)th cell of the discretized power map (c) Schematic of the flow distribution in the parallel flow zones as per the discretization from (a). With the flow direction as shown in Fig. 2(b), the average coolant temperature in the (i,j)th cell
T f ,( i , j ) is given by Eq.(2).
j −1
T f ,(i , j ) = T f ,in + ∑ k =1
Q(′′i ,k ) ∆yi ∆xk i
φi m c p , f
+
Q(′′i , j ) ∆yi ∆x j i
(2)
2φi m c p , f
where T f ,in is the coolant inlet temperature. Next, we assume negligible heat spreading between the -5-
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junctions and the base of the heat sink. This is the most important assumption in this model as it allows the flow of heat from junctions to the coolant to be treated as one-dimensional. Hence the average junction
TJ ,( i , j ) = T f ,( i , j ) + Q(′′i , j ) Rλ′′ + Q(′′i , j ) Rα′′,( i , j )
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temperature in the (i,j)th cell TJ ,( i , j ) is obtained as below:
(3)
Here Rλ is the total conduction resistance between the junctions and the base of microchannels and is given by the summation of all the conduction resistances in series (such as those due to the silicon chip thickness,
Rλ′′ = ∑
∆zl λl
(4)
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l
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the TIM and the heat sink base):
Rα′′,( i , j ) is the convective resistance for heat transfer to the coolant in the (i,j)th cell. Accounting for the fin resistance and assuming adiabatic fin tops, Rα′′,( i , j ) is given by [10]:
wc ,(i , j ) + ww,(i , j )
α(i , j ) wc ,(i , j ) + 2α(i , j ) hc γ(i , j )
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Rα′′,(i , j ) =
(5)
where hc is the microchannel depth, α( i , j ) is the local convective heat transfer coefficient and γ(i , j ) is the local fin efficiency. γ(i , j ) is calculated as below:
tanh ( mhc )
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γ(i , j ) =
mhc
, m=
2α(i , j ) λw ww,(i , j )
(6)
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and α( i , j ) is given by:
α(i , j ) =
Nu D ,( i , j ) λ f Dc ,( i , j )
(7)
Here Nu D ,( i , j ) is the local Nusselt number defined in terms of Dc,(i , j ) , an equivalent length scale for the microchannel cross-section. The definition for Dc ,(i , j ) depends upon the form of correlation available for Nu D ,( i , j ) . The thermal resistances in Eq. (3) can be compared in terms of an order of magnitude analysis for a typical modern day silicon microprocessor cooled by a thin backside-attached copper heat sink or by
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ELC [10, 24]. The following relevant parameters are used for this comparison: α ≈ 1 − 5 × 104 W/m2K,
∆zCu = 1 mm, ∆zTIM = 10 μm, ∆zSi =525 μm, λCu =400 W/m.K, λTIM = 10 W/m.K, λSi =140 W/m.K,
wc = ww = hc ≈ 100 μm [4, 10, 24]. With these parameters, the various resistances compare as Rα′′ (13 –
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67 mm2K/W) > Rλ′′, Si (3.8 mm2K/W) > Rλ′′,Cu (2.5 mm2K/W) > Rλ′′,TIM (1 mm2K/W). In addition to these
′′ = W ( wc + ww ) mc ɺ p . For a 2 × 2 cm2 chip and resistances, the bulk resistance can be calculated as Rbulk ′′ is 0.06 mm2K/W, the least of all resistances. Finally, the total coolant (water) flow rate of 1 L/min, Rbulk
( R′′
total
′′ + Rα′′ + Rλ′′,total ) can be compared for chip backside-attached and ELC = Rbulk
(
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total thermal resistance
)
lies in the range
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′′ = Rbulk ′′ + Rα′′ + Rλ′′,Cu + Rλ′′,TIM + Rλ′′, Si approach. For chip backside-attached cooling, Rtotal
≈ 20 − 74 mm2K/W. On the other hand for ELC, Rλ′′,Cu and Rλ′′,TIM are eliminated and Rλ′′, Si reduces to 3
′′ reduces to ≈ 16 − 70 mm2K/W, a reduction of up to mm2K/W (as ∆zSi =525 µm - hc ). As a result Rtotal 20% as compared to backside-attached cooling at the lower end of the range of heat transfer coefficients. With these thermal characteristics of the heat sink in place, the design of the hotspot-targeted heat
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i
sink involves determination of geometrical parameters wc ,(i , j ) , ww,(i , j ) and operational parameters m and φi such that the maximum junction temperature TJ ,max , as well as chip wide temperature gradient ∆TJ ,max are
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minimized, while satisfying the following constraints
wc ,min ≤ wc ,( i , j ) ≤ wc ,max ww,min ≤ ww,( i , j ) ≤ ww,max
(8)
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∆P ≤ ∆Plimit
where wc ,min and ww ,min are the lower limits for microchannel and wall widths respectively and ∆Plimit is the upper limit for the overall pressure drop. The geometrical and operational design parameters are determined by separately considering the terms in Eq. (3) as discussed in the following subsections. 2.1 Determination of flow distribution ϕ i The first step in minimizing TJ ,max and ∆TJ ,max is minimization of bulk resistance that drives the increase in coolant temperature T f ,( i , j ) (the first term in Eq. (3) and given by Eq.(2)). This is achieved -7-
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by equalizing the rise in fluid temperature T f ,(i ,m) − Tf ,in for all n rows. This gives n equations in n unknown variables ϕ i : n
∑ϕ i =1
i
=1 (9)
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Q(′′i ,m ) ∆xm ∆y1 m −1 Q′′ ∆x ∆yi m −1 ′′ ′′ k ) ∆xk + (1, m ) m for i = 2 to n Q x Q(1, ∆ + = ∑ ∑ k (i ,k ) 2 2 ϕi k =1 ϕ1 k =1 With ϕ i determined as above, T f ,( i , j ) in Eq. (3) are fixed.
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The second term Q(′′i , j ) Rλ′′ is fixed for a given power map and cooling architecture. Hence, only the
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convective resistance term Q(′′i , j ) Rα′′,( i , j ) can be controlled which leads to determination of the channel widths wc ,(i , j ) as explained in the following subsection. 2.2 Determination of channel widths wc,(i , j )
In order to reach a unique solution for wc,(i , j ) , the microchannel wall widths ww,(i , j ) can be independently fixed such that the overall pressure drop is minimized. This gives:
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ww,(i , j ) = ww, min
(10)
With the wall widths fixed as above, the distribution of junction temperatures TJ ,(i , j ) is determined
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only by the distribution of channel widths wc ,(i , j ) through the convective resistance term in Eq. (3). This term is minimized under the following condition: (11)
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′′ Rα′′,min = Qmin ′′ Rα′′,max Q(′′i , j ) Rα′′,( i , j ) = Qmax
Eq. (11) distributes convective resistance according to the heat flux map. The minimum convective
′′ , resistance Rα′′,min corresponds to the finest microchannels wc ,min , assigned to the (i,j)th cell with Q(′′i , j ) = Qmax and is given by:
Rα′′, min =
wc ,min + ww,min αmax wc ,min + 2αmax hc γmin
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It should be noted that the choice of the finest microchannel dimension wc ,min will depend on the heat sink material (for example copper in case of conventional backside-attached heat sinks or silicon in case of ELC) and the fabrication process. For example, in case of ELC, for an aspect ratio limit of 10 for deep
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reactive ion etching and a microchannel depth of 300 microns, the finest microchannel dimension is limited to 30 microns [24].
Eqs. (11) and (12) along with Eqs. (5) and (10) result in following nm − 1 non-linear equations for
nm − 1 unknown microchannel widths wc ,(i , j ) :
α(i , j ) wc ,(i , j ) + 2α(i , j ) hc γ(i , j )
=
′′ Rα′′, min Qmax Q(′′i , j )
(13)
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with γ(i , j ) and α(i , j ) given by Eqs. (6) and (7).
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wc ,(i , j ) + ww,min
Since the channel widths change according to the change in heat flux along flow direction, it is important that the coolant flows uninterrupted in every row (i.e. does not run into a wall). This is ensured by simply modifying wc,(i , j ) values from Eq. (13) such that the microchannel pitch in any (i,j)th cell
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wc ,(i , j ) + ww,min is related to the pitches in adjacent upstream and downstream cells, wc ,(i , j −1) + ww,min and wc ,(i , j +1) + ww,min , through integral multiples.
i
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2.3 Determination of total coolant flow rate m
i
i
The only design parameter that remains to be determined is the total coolant flow rate m . The m
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can be fixed such that the maximum pressure drop among all the n rows does not violate the pressure drop constraint in Eq. (8) i.e.:
max ( ∆Pi ) ≤ ∆Plimit i
(14)
Pressure drops ∆Pi can be expressed in terms of Fanning friction factor, as below: i 2 µ f ( f Re D )(i , j ) ∆x j φi m p(i , j ) ∆Pi = ∑ 2 ρ f ∆yi Ac ,(i , j ) D j =1 c ,( i , j ) m
(15)
where p( i , j ) = wc ,( i , j ) + ww, min is the microchannel pitch and Ac ,( i , j ) = wc ,( i , j ) hc is the channel cross-9-
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i
sectional area. Equations (14) and (15) determine the highest allowable m . 2.4 Passive flow throttling to achieve coolant distribution ϕ i The pressure drops ∆Pi are bound to be different due to unequal flow distribution ϕ i and
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microchannel widths in all n rows. As a result, when coolant is supplied to such a microchannel heat transfer structure design, most of the coolant will escape through rows with wider microchannels due to smaller resistance to flow from these rows. Hence, the required flow distribution ϕ i , as calculated in subsection 2.1,
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will not be realized. This flow distribution can only be realized if the flow resistances of all parallel n rows are equalized when the coolant is distributed according to ϕ i [24]. This can be achieved by introducing
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additional resistances in all rows such that:
∆Pi + ∆Pi * = max ( ∆Pi ) = ∆Plimit i
(16)
where ∆Pi is the pressure drop due to the additional flow resistance introduced in the ith row. This is a key *
idea in our approach to hotspot targeted cooling.
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The additional resistances can be flow throttling zones either in the manifold that supplies the coolant or within the microchannel structure itself in the form of fine channels. In the latter case, however, it has to be ensured that the flow throttling channels do not interrupt the flow as discussed in section 2.2. Additionally, the throttling zones have to be positioned such that the enhanced cooling caused by the fine
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* microchannels does not adversely affect ∆TJ ,max achieved in section 2.2 [24]. Note that ∆Pi = 0 for the ith * row with ∆Pi = max ( ∆Pi ) . Similar to Eq.(15), ∆Pi can also be expressed as below:
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i
i * 2 µ ( f Re D )i L*i φi m ∆Pi = 2 * * * ρ A N ( Di ) f i i *
(17)
where the superscript ‘*’ indicates geometrical and operational parameters for the flow throttling zone. Then, by using Eq.(16), the geometrical parameters for the flow throttling zones can be calculated. With this, the design of a hotspot-targeted microchannel heat sink is completed. 2.5 Design for developed and developing flow
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The design method discussed above can be used for both TMC as well as MMC heat sinks. The critical difference between the two is in terms of the hydrodynamics due to which the semi-empirical design method is used differently for the two types of heat sinks.
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2.5.1 Developed flow In TMC heat sinks, the flow enters the microchannel heat transfer structure from one side, flows the entire length of the microchannels and exits from the other side. The flow develops quickly and hence can be assumed to be fully developed inside the microchannels. Since friction factors and Nusselt number for fully
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developed flow are independent of the Reynolds number and are only dependent on the geometry of the i
microchannels, wc ,( i , j ) values determined by Eq. (13) are independent of m and the heat sink design is
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completed in a single iteration by sequentially following the steps from section 2.1 to 2.4. 2.5.1 Developing flow
For MMC heat sinks, the flow inside the microchannels is developing for a large part of the microchannel length due to the relatively short channel length available between each pair of inlet and outlet slot nozzles [10, 11]. In this case, due to the dependence of Nusselt number and Fanning friction factor-
( f Re D )
on Reynolds number, the heat transfer coefficients α(i , j ) and hence
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Reynolds number product
i
the microchannel widths wc ,( i , j ) are no longer independent of m . This necessitates the following recursive i
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procedure once the required flow distribution is determined using Eq.(9): (a) Assume m (b) determine
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wc ,( i , j ) using Eq. (13) in section 2.2 and revise wc ,( i , j ) values to ensure uninterrupted flow (c) use Eqs. i
(14) and (15) in section 2.3 to check if the pressure drop constraint is satisfied - if yes, then increase m , i
repeat steps (a)-(c) and iterate to obtain the highest m satisfying the pressure drop constraint (d) calculate the configuration of flow throttling zones using Eqs. (16) and (17) in section 2.4. In the following two sections, we demonstrate the application of the semi-empirical design method for TMC and MMC heat sink cooling architecture. 3. Exemplar design for an arbitrary power map cooled by TMC heat sink In this section, we illustrate the use of the one-dimensional model to design a hotspot targeted - 11 -
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embedded TMC structure. We consider a highly non-uniform power map shown in Fig. 3 with W = 1.6 cm and L = 1.2 cm . The coolant is assumed to be water with the constant properties: ρ f = 998.2 kg/m3,
µ f = 0.001 Pa-s, and c p , f = 4180 J/kg-K. The thermal conductivity of silicon is also assumed to be
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constant ( λl =150 W/m-K). Following design constraints have been adopted for Eq. (8):
wc ,min = ww,min = 30 µm, ∆Plimit =0.5 bar. Considering a maximum feasible aspect ratio of 10 for microchannels [25], the microchannel height hc is assumed to be 300 µm and hence the unetched chip
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thickness ∆zl is 225 µm for a standard 525 µm thick silicon wafer. Flow is assumed to be fully
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developed and the correlations for Nu and f Re , for rectangular channels, are adopted from Shah and London [26]. These correlations are defined in terms of hydraulic diameter which can be expressed as:
Dc ,(i , j ) =
(w
2wc ,(i , j ) hc
+ ww, min
)
(18)
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c ,( i , j )
Figure 3: An exemplar non-uniform power map with heat flux dissipation in W/cm2. Using the coarsest level of discretization similar to Fig. 2, and following the sections 2.1 and 2.2, we obtain a set of non-linear system of equations for wc ,( i , j ) (Eq. (13)) that is solved using MATLAB - 12 -
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(R2013b). The wc ,( i , j ) values so obtained are modified to ensure uninterrupted coolant flow (refer to the section 2.2). The resulting hotspot-targeted wc distribution is shown in Fig. 4. i
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This is followed by the determination of maximum m (refer to the section 2.3). The i
∆Plimit constraint limits m to 1.17 g/s (0.07 l/min). Figure 5(a) shows the temperature map of the chip corresponding to the hotspot-targeted microchannel structure at 0.07 l/min. The performance of the optimal design is evaluated against a base case consisting of uniformly fine, embedded microchannels
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( wc = ww = 30 µm) and uniform flow distribution at the same level of pumping power as the hotspottargeted design. The base case represents the limit of TMC heat sink cooling. The temperature map for the
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base case is shown in Fig. 5(b). Figure 5 illustrates that, as compared to the base case, hotspot-targeted design reduces TJ ,max from 79.6 ℃ to 55.3 ℃ and ∆TJ ,max from 57.5 ℃ to 31.4 ℃ - an improvement of
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45 %.
Figure 4: wc distribution for the power map in Fig. 3
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(a)
(b) Figure 5: Temperature maps (a): hotspot-targeted design (b) base case. The same temperature scale for both the figures illustrates reduction in TJ ,max and ∆TJ ,max . Coolant flows from left to right.
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(a)
(b)
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(c)
Figure 6(a): Throttling zones towards coolant outlet (compare with Fig. 4) (b) Temperature map for the
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design shown in Fig.6(a) (compare with Fig. 5(a)) (c) Schematic of the throttling in ith row with two
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* microchannels of width wc ,(i ,m ) merging into a fine microchannel of width wc ,i
Following section 2.4, the pressure equalization is achieved by introducing flow throttling zones in the microchannel structure. The throttling zones are positioned towards the coolant outlet and are formed by merging every two channels in each row into a fine microchannel of 30 µm width, i.e. wc*,i =30
(
)
µm and ww,i = 2 wc,(i ,m) + ww, min − wc,i . With wc*,i and ww* ,i fixed, the throttling zone lengths Li are *
*
(
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obtained using Eqs. (16) and (17) with Di* = 2 wc*,i hc
) (w
* c ,i
)
+ ww* ,i and Ni* = ∆yi
*
(w
* w,i
)
+ wc*,i .
Figure 6(a) shows the microchannel structure along with flow throttling zones in black color. Figure 6(b) shows the temperature map for the complete design which clearly shows that the additional cooling from
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the throttling zones does not adversely affect the performance of the hotspot targeted design. Figure 6(c) shows a schematic of the flow throttling microchannels formed by merging two microchannels into a fine
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microchannel in the ith row.
4. Design for a multicore microprocessor power map cooled by MMC heat sink In this section, we demonstrate the application of the semi-empirical model for the design of an
MMC heat sink for hotspot-targeted cooling of a modern day multicore microprocessor. 4.1 One-dimensional model calibration The one-dimensional semi-empirical equations (Eqs. (2) and (3)) can model the thermal performance of an MMC heat sink for uniform power dissipation map [10]. Here, we calibrate and evaluate this model for highly non-uniform power maps against experimental results from Sharma et al. [24], who - 16 -
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used a non-uniform power map as depicted in Fig. 7(a). The areas marked hotspots are regularly distributed and dissipate 150 W/cm2 while the background dissipates 20 W/cm2. This power map is representative of a typical level of heat flux contrast in modern day multicore microprocessors. This power map is cooled by an
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MMC heat sink having uniform embedded microchannel structure (ELC, refer section 1) with wc = 35 µm,
ww = 25 µm, hc = 250 µm and ∆zl = 275 µm. The flow is distributed uniformly across the microchannels structure i.e. fraction of flow in each microchannel is φ = ( wc + ww )
( yn − y0 ) . The slot nozzles of the heat
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sink are arranged such that inlet slot nozzles are positioned over the hotspots to concentrate the jetimpingement cooling in these areas and outlet slot nozzles are positioned over the background area in-
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between the cores [24]. Figure 7(a) shows the placement of one pair of inlet and outlet slot nozzles and the direction of flow in the microchannels from inlet to outlet [24].
To model the convective flow resistance Rα'' ,( i , j ) in Eq. (3) for simultaneously developing microchannel flow between inlet and outlet slot nozzles, we adopt the Nusselt number correlation from
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Muzychka and Yovanovich, 2004 [27] for Nu D ,( i , j ) in Eq. (7). Since this correlation is based on square
(a)
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(b)
Figure 7(a) Non-uniform power map and placement of one inlet-outlet slot nozzle pair. Arrow indicates direction of flow. (b) Calibration of one-dimensional against experimental measurements for ∆TJ ,max and
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TJ ,max
root of flow area as the characteristic length, we have Dc ,( i , j ) =
wc ,( i , j ) hc . However, these correlations
require calibration as explained below to adequately capture the heat sink thermal performance.
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As mentioned in section 2, Eq. (3) does not account for heat spreading which becomes significant as the heat flux contrast increases in non-uniform power maps of the kind shown in Fig. 7(a).
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Moreover, the NuD correlation does not account for the jet impingement effect near the inlet slot nozzle and thus cannot accurately model the streamwise profile of the local heat transfer coefficient. These two effects combine to cause inaccuracy in the modeling of total thermal resistance and thus the junction temperature map. In order to improve the one-dimensional model accuracy, we calibrate the
NuD correlation by introducing a modified channel height hc* = chc [10]. The empirical constant c is then calibrated to achieve a close match for TJ ,max as well as ∆TJ ,max against experimentally measured values as shown in Fig. 7(b). The model predictions in the figure pertain to a fixed value of c for all the
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flow rates. Figure 7(b) compares the modelled and measured values as a function of the overall volumetric i
i
flow rate V = m ρ f . For the range of investigated flow rates, the calibrated model is able to capture
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TJ ,max and ∆TJ ,max within 3.5 ℃. The deviation of model predictions from experimental measurements is higher at lower flow rates. This is because of the strong effect of heat spreading at lower flow rates due to higher convective resistance Rα'' to heat transfer in the microchannel structure.
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A further improvement in accuracy of model predictions would require switching to threedimensional conjugate heat transfer CFD approach which alleviates the above described limitations of the
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one-dimensional model (refer [24] for further details of three-dimensional modeling). However, the purpose of the one-dimensional model is to arrive at a quick initial estimate of the MMC heat sink microchannel distribution using the design approach explained in sections 2.1-2.4. We demonstrate in the next section, that in spite of the assumptions involved in one-dimensional equations, the one-dimensional semi-empirical design approach achieves a sound initial estimate of the hotspot-targeted MMC heat sink
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design.
4.2 Hotspot-targeted MMC heat sink design
This section describes the application of the one-dimensional semi-empirical model for the design of a hotspot-targeted MMC heat sink for a non-uniform power map. We consider the power map shown in Fig.
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7(a) with hotspots now dissipating 300 W/cm2 while the background dissipates 20 W/cm2 of heat flux as
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before. The design constraints are chosen to be: wc ,min = ww,min = 30 µm, ∆Plimit =0.35 bar [28]. Rest of the configuration of MMC heat sink is same as described in section 4.1. Along with the calibrated Nu correlation from previous section for modeling the thermal performance, we adopt the
f Re correlation, for
simultaneously developing flow from Muzychka and Yovanovich, 2004 [27], to model the hydrodynamic performance of the heat sink.
Since the hotspots are regularly distributed, the analysis considers a unit cell of the power map between the inlet-outlet slot nozzle pair marked in Fig. 7(a). The simultaneously developing flow necessitates the use of the recursive procedure described in section 2.5.2 for design of the heat sink. We
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describe the results of this procedure in the following.
(a)
(b)
Figure 8: (a) Hotspot-targeted wc distribution for the power map in Fig. 7(a). Throttling zones are shown
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in black color. (b) Comparison of TJ distribution for the hotspot-targeted and base MMC heat sink designs
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Equation (9) yields the coolant flow distribution whereby 86 % of the flow needs to be diverted to i
the two hotspots in the unit cell (43 % to each hotspot). Then, progressively increasing values of m are tested and for each value, wc ,( i , j ) distribution is calculated and the pressure drop constraint ∆Plimit is verified. Imposition of ∆Plimit yields a maximum feasible water flow rate of 0.026 kg/s (1.58 l/min). Figure 8(a) shows the resulting hotspot-targeted microchannel width distribution in the unit cell of the hotspottargeted MMC heat sink design. The throttling zones are shown in black color and have the configuration:
(
)
wc*,i = 30 µm, ww* ,i = 2 wc ,(i ,m ) + ww,min − wc*,i and L*i = 1.45 mm.
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Figure 8(b) compares the junction temperature map for the hotspot-targeted design TJ ,( i , j ) at i
maximum feasible m against the corresponding map for a base MMC heat sink design at the same level of pumping power. The base design is chosen to have a uniformly fine, embedded microchannel structure
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with wc = ww = 30 µm and uniform flow distribution to represent the limit of conventional ELC [24]. The hotspot-targeted MMC heat sink design reduces ∆TJ ,max from 21.3 ℃ to 14.9 ℃, an improvement of 30 %, and leads to a significantly more uniform temperature map. Note that although the coarsest level of
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discretization is used to generate the wc map in Fig. 8(a) to isolate areas of spatially constant heat flux (refer
resolution in the TJ map in Fig. 8(b).
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to section 2 and Fig. 2(a)), a finer level of discretization in x-direction has been used to obtain higher
A comparison of the TJ maps in Fig. 8(b) with the corresponding maps in [24] indicates that the calibrated one-dimensional model is limited in terms of the accuracy of the predicted TJ map as compared to detailed three-dimensional CFD modeling approach. However, the wc map shown in Fig.
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8(a) is similar to the distribution arrived at in [24] with the detailed CFD and RSM optimization. This shows that the current one-dimensional design approach is sufficient to achieve a good initial condition for detailed optimization thus reducing the iterations involved in CFD based optimization. Since the wc
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distribution, the throttling zone lengths, overall maximum feasible coolant flow rate and the chip temperature map are obtained by using approximate correlations for simultaneously developing flow in
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the semi-empirical one-dimensional model, these values can be refined by subsequent detailed CFD based optimization to arrive at the final hotspot-targeted heat sink design and its performance. In terms of practical implementation of the hotspot-targeted microchannel cooling concept, we also mention here that the non-uniform wc map is also feasible from fabrication considerations, especially for ELC as shown through an experimental study by Sharma at al. [29] for the power map in Fig. 7(a). 5. A note on the significance of thermal spreading As discussed in previous section, the absence of heat spreading effect in the one-dimensional model is the main contributor to inaccuracy in model predictions. Although closed-form estimates for - 21 -
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thermal spreading are available in the literature, these are mostly limited to the assumption of spatially uniform cooling from the microchannel heat transfer structure side and hence are not applicable to the present problem involving non-uniform distribution of the cooling capacity adapted to the chip power map
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[30-32]. Such systems also require three-dimensional conjugate heat transfer computations to estimate the extent of thermal spreading. However, a simple thermal resistance network analysis can be used to identify the conditions under which thermal spreading may be neglected for non-uniform power maps cooled by spatially adapted heat transfer structures.
( ∆x1 + ∆x2 ) × ∆y as
shown in
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Consider a microprocessor power map with overall dimensions
Fig. 9(a). It dissipates heat fluxes Q1'' , Q2'' , with Q1'' > Q2'' , on strips of areas A1 = ∆x1∆y and
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A2 = ∆x2 ∆ y . The total vertical thickness of the unetched chip is ∆z and this power map is cooled by a non-uniform microchannel structure and flow distribution that achieves effective convective resistances
Rα'' ,1 and Rα'' ,2 over areas A1 and A2 , respectively
( where R
'' α
)
= Rα A = 1 αeff . We assume that the
coolant flow is distributed among the two strips such that the bulk resistance is minimized. Hence,
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following section 2.1, the fluid temperatures in both the strips are equalized at all y coordinates. Figure
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9(b) shows the resistance network at any coordinate y for a thin strip of width dy (shown in Fig. 9(a)).
(a) (b) Figure 9: (a) A theoretical non-uniform chip power map subjected to non-uniform cooling. Coolant flows along y-coordinate (b) the thermal resistance network at any y-coordinate.
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′′ is the local lateral heat flux that leads to thermal spreading, Rλ′′ = ∆z λ is the conduction Here Qsp
′′ is the local resistance to lateral flow of heat which can be resistance of the unetched chip and Rsp approximated as
Lx λ with Lx ≈ 0.5 ( ∆x1 + ∆x2 ) . The infinitesimal areas are dA1 = ∆x1dy ,
(19).
Q1′′ Rα′′,1 − Q2′′ Rα′′,2 ∆x L ∆x Rα′′,1 + Rα′′,2 1 + x 1 ∆x2 λ∆z
(19)
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∆x Qsp′′ = 1 ∆z
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dA2 = ∆x2 dy and dAsp = ∆zdy . This network can be solved to obtain the lateral heat flux Qsp′′ in Eq.
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Equation (19) provides the following qualitative conditions under which the thermal spreading is insignificant. Thus: (a)
Qsp′′ is minimized if the convective resistances are scaled according to Eq. (11) as it reduces the numerator in the above equation. In fact, if the hotspots extend the entire flow length ∆y as in Fig. 9
′′ would be reduced to a negligible value as the convective and the flow is fully developed, Qsp
(b)
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resistance scaling will hold for all y .
Qsp′′ reduces with the size of the hotspots (reducing ∆x1 ) as the power map will approach a spatially uniform heat flux dissipation condition.
′′ dAsp reduces with the decrease in unetched chip thickness ∆z . The net lateral heat transfer Qsp
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6. Conclusions
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A 1-dimensional model for quick design of a liquid cooled, hotspot-targeted microchannel heat
sink was presented. The model is a generalized design method for developed and developing flow situations encountered in TMC and MMC heat sinks respectively and it is applicable to arbitrary chip power maps encountered in serial and multicore microprocessors. The approach is equally applicable to both conventional and embedded cooling heat sinks. The potential of the model was demonstrated first by an exemplar design for a TMC heat sink with developed flow in microchannels. For developing flow, the model was calibrated against existing experimental results and the calibrated model was used to design a
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MMC heat sink with embedded microchannels. Lastly, a simple analysis of thermal spreading in nonuniform microprocessor power maps was presented to highlight the conditions under which heat spreading
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becomes insignificant thus increasing the accuracy of the one-dimensional modeling approach.
Nomenclature
cross-sectional area of each parallel flow path in the throttling zone (m2)
cp
specific heat capacity (J/KgK)
D
equivalent cross-sectional length scale (m)
i
SC
Ai*
total coolant flow (kg/s)
hc
microchannel height (m)
i, j,k
indices
L*i
length of throttling zone in ith row (m)
n, m
number of rows and columns in the discretized power map
Ni*
number of parallel flow paths in throttling zone
NuD
Nusselt number defined for D
Qi'', j
heat flux in the (i,j)th cell (W/m2)
Qsp''
thermal spreading heat flux (W/m2)
∆P
pressure drop (Pa)
Rα′′ ′′ Rbulk
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Rλ′′
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m
conduction resistance (m2K/W) convection resistance (m2K/W) bulk resistance (m2K/W)
f Re D
Fanning friction factor-Reynolds number product
TJ
junction temperature (K)
Tf
coolant temperature (K) - 24 -
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wc
microchannel width (m)
ww
microchannel wall width (m)
W ×L
microprocessor chip dimensions (m2)
x j , yi
coordinates (m)
∆zl
thickness of lth layer (m)
SC
Greek symbols
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∆x j , ∆yi cell diemnsions of discretized power map (m)
heat transfer coefficient (W/m2K)
c
microchannel
D
equivalent cross-sectional length scale
ϕi
fraction of m directed into the ith row
γ
fin efficiency
λ f , λw
fluid and solid thermal conductivities in heat sink (W/mK)
λl
thermal conductivity of lth layer in heat transfer path from junctions to microchannel base
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α
(W/mK)
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i
dynamic fluid viscosity (Pa.s)
ρf
fluid density (kg/m3)
f max min
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Subcripts
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µf
fluid
maximum minimum
Acronyms CMOS complementary meatl-oxide-semiconductor ELC
embedded liquid cooling
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RSM
response surface methodology
TIM
thermal interface material
TMC
traditional microchannel
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References
[1] G.E. Moore, Cramming More Components Onto Integrated Circuits, Electronics, 38 (1965) 114-117. [2] S.H. Fuller, L.I. Millett, Computing Performance: Game Over or Next Level?, Computer, 44 (2011) 3138. Directions, Solid-State Electron., 51 (2007) 518-525.
SC
[3] R.H. Dennard, J. Cai, A. Kumar, A Perspective on Today’s Scaling Challenges and Possible Future [4] C.S. Sharma, S. Zimmermann, M.K. Tiwari, B. Michel, D. Poulikakos, Optimal Thermal Operation of
M AN U
Liquid-cooled Electronic Chips, Int. J. Heat Mass Transfer, 55 (2012) 1957-1969.
[5] JEDEC, Failure Mechanisms and Models for Semiconductor Devices, in: JEDEC (ed.), 2010, pp. 1-9,6872.
[6] D.B. Tuckerman, R.F.W. Pease, High-Performance Heat Sinking for VLSI, IEEE Electron Device Lett., 2 (1981) 126-129.
[7] P.-S. Lee, S.V. Garimella, D. Liu, Investigation of Heat Transfer in Rectangular Microchannels, Int. J. Heat Mass Transf., 48 (2005) 1688-1704.
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[8] D. Copeland, M. Behnia, W. Nakayama, Manifold Microchannel Heat Sinks: Isothermal Analysis, IEEE Trans Compon Pack Technol., Part A, 20 (1997) 96-102. [9] J.H. Ryu, D.H. Choi, S.J. Kim, Three-dimensional Numerical Optimization of a Manifold Microchannel Heat Sink, Int. J. Heat Mass Transf., 46 (2003) 1553-1562.
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[10] W. Escher, B. Michel, D. Poulikakos, A Novel High Performance, Ultra Thin Heat Sink for Electronics, Int. J. Heat Fluid Flow, 31 (2010) 586-598. [11] C.S. Sharma, M.K. Tiwari, B. Michel, D. Poulikakos, Thermofluidics and Energetics of a Manifold
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Microchannel Heat Sink for Electronics With Recovered Hot Water as Working Fluid, Int. J. Heat Mass Transfer, 58 (2013) 135-151.
[12] E. Kermani, S. Dessiatoun, A. Shooshtari, M.M. Ohadi, Experimental Investigation of Heat Transfer Performance of a Manifold Microchannel Heat Sink for Cooling of Concentrated Solar Cells, in:
Electronic
Components and Technology Conference, 2009. ECTC 2009. 59th, 2009, pp. 453-459. [13] G. Hetsroni, A. Mosyak, Z. Segal, G. Ziskind, A Uniform Temperature Heat Sink for Cooling of Electronic Devices, Int. J. Heat Mass Transfer, 45 (2002) 3275-3286. [14] C.A. Rubio-Jimenez, S.G. Kandlikar, A. Hernandez-Guerrero, Numerical Analysis of Novel Micro Pin Fin Heat Sink With Variable Fin Density, IEEE Trans. Compon. Pack. Technol., 2 (2012) 825-833. [15] J. Barrau, D. Chemisana, J. Rosell, L. Tadrist, M. Ibañez, An experimental study of a new hybrid jet impingement/micro-channel cooling scheme, Applied Thermal Engineering, 30 (2010) 2058-2066. - 26 -
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[16] H. Esmaeilzadeh, E. Blem, Ren, #233, e.S. Amant, K. Sankaralingam, D. Burger, Power Limitations and Dark Silicon Challenge the Future of Multicore, ACM Trans. Comput. Syst., 30 (2012) 1-27. [17] IBM Unveils New POWER7 Systems To Manage Increasingly Data-Intensive Services, in, Vol. 2013, http://www-03.ibm.com/press/us/en/pressrelease/29315.wss. [18] Y.J. Lee, P.S. Lee, S.K. Chou, Hotspot Mitigating With Obliquely Finned Microchannel Heat Sink---An
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Experimental Study, IEEE Trans Compon Pack Technol., 3 (2013) 1332 - 1341.
[19] T. Brunschwiler, H. Rothuizen, S. Paredes, B. Michel, E. Colgan, P. Bezama, Hotspot-adapted Cold Plates to Maximize System Efficiency, in: 15th International Workshop on Thermal Investigations of ICs and Systems, 2009. THERMINIC 2009. , 2009, pp. 150-156.
[20] P.-S. Lee, S.V. Garimella, Hot-Spot Thermal Management With Flow Modulation in a Microchannel ASME International Mechanical Engineering Congress and Exposition Vol. 2005, ASME,
SC
Heat Sink, in:
Orlando, Florida, USA, 2005, pp. 643-647.
[21] B. Dang, M.S. Bakir, J.D. Meindl, Integrated Thermal-fluidic I/O Interconnects for an On-chip
M AN U
Microchannel Heat Sink, IEEE Electron Device Lett., 27 (2006) 117-119.
[22] K. Etessam-Yazdani, M. Asheghi, H.F. Hamann, Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis, IEEE Trans Compon Pack Technol., 31 (2008) 211215.
[23] Z. Mingyuan, Z.R. Huang, Design of On-Chip Microchannel Fluidic Cooling Structures, in: Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th, 2007, pp. 20172023.
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[24] C.S. Sharma, M.K. Tiwari, S. Zimmermann, T. Brunschwiler, G. Schlottig, B. Michel, D. Poulikakos, Energy Efficient Hotspot-targeted Embedded Liquid Cooling of Electronics, Applied Energy, 138 (2015) 414-422.
[25] M.J. Madou, Fundamentals of Microfabrication : The Science of Miniaturization, 2nd ed., Boca Raton,
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FL : CRC Press 2002.
[26] R.K. Shah, A.L. London, Laminar flow forced convection in ducts, Academic Press, New York, 1978. [27] Y.S. Muzychka, M.M. Yovanovich, Laminar Forced Convection Heat Transfer in the Combined Entry
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Region of Non-Circular Ducts, Journal of heat transfer, Transaction of ASME, 126 (2004) 54-61. [28] E.G. Colgan, B. Furman, M. Gaynes, W.S. Graham, N.C. LaBianca, A Practical Implementation of Silicon Microchannel Coolers for High Power Chips, IEEE Trans. Compon. Pack. Technol., 30 (2007) 218225.
[29] C.S. Sharma, G. Schlottig, T. Brunschwiler, M.K. Tiwari, B. Michel, D. Poulikakos, A novel method of energy efficient hotspot-targeted embedded liquid cooling for electronics: An experimental study, International Journal of Heat and Mass Transfer, 88 (2015) 684-694. [30] Y.S. Muzychka, J.R. Culham, M.M. Yovanovich, Thermal Spreading Resistance of Eccentric Heat Sources on Rectangular Flux Channels, Journal of Electronic Packaging, 125 (2003) 178-185. [31] Y.S. Muzychka, M.M. Yovanovich, J.R. Culham, Thermal Spreading Resistance in Compound and Orthotropic Systems, Journal of Thermophysics and Heat Transfer, 18 (2004) 45-51. - 27 -
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[32] S. Lee, S. Song, V. Au, K.P. Moran, Constriction/ spreading resistance model for electronics packaging,
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M AN U
SC
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in: ASME/JSME Thermal Engineering Conference, Vol. 4, 1995.
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