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A single flux quantum standard logic cell library
Physica C 378–381 (2002) 1471–1474 www.elsevier.com/locate/physc
A single flux quantum standard logic cell library S. Yorozu a
a,*
, Y. Kameda a, H. Terai b, A. Fujimaki c, T. Yamada c, S. Tahara
a
Fundamental Research Laboratories, NEC Corporation, 34 Miyukigaoka, Tsukuba 305-8501, Ibaraki, Japan b Kansai Advanced Research Center, Communication Research Laboratory, Kobe 651-2492, Japan c Department of Quantum Engineering, Nagoya University, Furo-cho, Chikusaku, Nagoya 464-8603, Japan Received 27 September 2001; accepted 25 December 2001
Abstract To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable. Ó 2002 Elsevier Science B.V. All rights reserved. PACS: 85.25.Cp; 85.25.Hv Keywords: Superconducting devices; Single flux quantum logic; Cell-based design; RSFQ logic cell library
1. Introduction Single flux quantum (SFQ) large-scale digital circuits can operate at several tens GHz speed with very low power consumption; no other digital circuits have such characteristics. However, very few large-scale random-logic-circuits are reported because no design methodologies have been established as yet [1]. A top-down design methodology and tools should be established. The cell-based method is one candidate for the SFQ circuit design [2]. In cell-based design, a digital circuit is made by *
Corresponding author. Tel.: +81-298-50-2634; fax: +81298-56-6139. E-mail address: [email protected] (S. Yorozu).
placing many standard cells in a cell library that have elemental logic functions such as and, or, d-flip flop, Josephson transmission line (JTL), etc. We developed a new SFQ logic cell library for cell-based circuit design. We call it CONNECT (co-operation of Nagoya University––NEC-CRL teams) cell library. The CONNECT cells were designed with as small interactions between cells as possible. In layout level, we defined a minimum standard size and made cell height and width a multiple of the standard size for convenience of placing. A digital level simulator can be used for estimating the performance of the circuits made by using CONNECT library. Thus we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. In addition,
0921-4534/02/$ - see front matter Ó 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 1 - 4 5 3 4 ( 0 2 ) 0 1 7 5 9 - 8
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S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
this library can be used with higher-level design tools such as automatic placement and layout. In this paper, we report on the CONNECT cell library.
2. Cell library The CONNECT cell library was established based on NEC standard fabrication technology (2.5 kA/cm2 and 2 lm 2 lm Josephson junction technology) and Cadence design systems Corporation CAD software [3,4]. We added our specially developed software to the CAD system for adapting the SFQ circuit to the CAD system because a SFQ circuit is different from conventional semiconductor circuit technologies. A state of the art CONNECT cell library consists of about 100 cells. The CONNECT cell is separated into three levels; digital level, analog level, and layout level. Fig. 1 shows the design flow chart of the CONNECT cell. The digital level is described by using Verilog hardware description language, which includes information on pins, operation (behavior), operation delay time, and timing between clock and data signals (setup time, hold time, etc.). The analog level is a circuit diagram described by Josephson junctions, inductances, and resistances. The circuit is designed according to digital level behavior description. In circuit design, we referred to conventional circuits and concepts as prototypes [5,6]. At the analog level design, it is important to minimize interactions between cells for expanding circuit scale. To minimize interactions, we have designed and optimized circuits by
Fig. 1. Design flow chart.
Fig. 2. Analog level design scheme.
using the scheme shown in Fig. 2. We defined the rules as follows. (1) The critical current of a Josephson junction of JTL is 0.2 mA. (2) As shown in Fig. 2, the target circuit is added a half JTL on both input and output ports for checking leak currents, and then optimized. In optimization, circuit parameters of half JTLs are unchanged. (3) All input and output ports of the target circuit have an 0.15 mA bias current injection port. (4) All currents that flow between the target circuit and the half-JTL (Iin and Iout in Fig. 2) are less than 0.0015 mA.
Fig. 3. Standard cell example (JTL: Josephson transmission line).
S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
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Table 1 Characteristics of principal cells Logic
Number of JJ
Delay time (ps)
JTL Pulse splitter Confluence buffer TFF AND XOR NOT DFF NDRO
2 3 7 7 13 11 10 6 11
7.6 8.3 13.2 13.2 17 12.2 12.2 10.2 18.7
We optimized circuit parameters by using optimization software that was developed at Nagoya University [7]. All circuit parameter values have been optimized for obtaining the widest margins even if all critical currents are shifted 10%. After optimizing, we re-simulated the circuit, obtained timing parameters, and changed to digital level timing parameter values. The layout level is the physical layout data of the cell circuit consistent with the analog level design result. All layout data were based on the NEC fabrication technology. We defined a minimum standard cell size as 40 lm and made cell height and width a multiple of the size. Input and output ports were also placed at 40 lm steps with 20 lm shifted from the edge of the cell. Fig. 3 shows an example of a JTL cell analog and layout levels. Its layout size is 40 lm 40 lm, which is standard minimum size of the CONNECT cells. Table 1 shows characteristics of the principal cells. All cells were optimized, but we continue to reoptimize them for the best performance.
3. Cell-based design using the library Fig. 4 shows a example of a cell-based circuit design. The first step is to design a target circuit without considering a wiring delay as shown in Fig. 4(a). This circuit was designed by using a deep pipeline scheme. Next, we replace all wirings with wiring-cells (JTL cell) as shown in Fig. 4(b). In SFQ circuit design, it is difficult to adjust the time sequence between data and clock timing signals. In order to have design flexibility, there are many kinds of wiring cells having various delay times
Setup time (ps)
)7 2 19.4 )2.3 )2.0
Hold time (ps)
Bias margin
7.7 )1 10.0 2.4 2.0
þ40% þ24% þ31% þ32% þ38% þ16% þ40% þ16%
to to to to to to to to
)24% )20% )31% )16% )21% )28% )44% )16%
and sizes. As a result, the schematic, Fig. 4(b), also has some kinds of wiring cells. The circuit was simulated using Verilog-XL (Cadence Design systems software) without analog time domain dynamic simulations until all timing constraints were satisfied. After completing the circuit design (Fig. 4(b)), the circuit’s digital schematic was converted automatically to a physical layout level. This circuit has 135 cells (419 Josephson junctions). Without using the CONNECT cell library, it is difficult to design such random logic circuits. Using this circuit layout, a test chip was fabricated using 2-lm NEC standard fabrication technology (Fig. 4(c)), and we experimentally demonstrated successful operation which has 9% dc bias margin. There are differences between typical margin of cells of Table 1 and the circuit margin. This difference is resulted that each cell has different operating point because the critical current of the tested chip is shifted about 10% from designed value. From bias margin measurements of each cell, overlapped margin is around 9%, which is similar to the whole circuit margin. As a result, the testing result means that our cell library is reliable within the present state of cells. For making robust cells and library, each cells needs further optimization.
4. Conclusion We have developed a new cell library for largescale SFQ digital circuits, which is called CONNECT. All CONNECT cells are optimized for obtaining the widest margins and minimizing interactions between cells. At present, there are
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S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
Fig. 4. Example of cell-based design.
totally over 100 cells in the library so that it is useful to make wiring. For estimating the reliability of the library, we designed, fabricated, and tested a sample circuit. We demonstrated its correct operations, and thereby confirmed the cell library is reliable. We continue to re-optimize cells for the best performance. In addition, automatic placement––routing methodologies and tools based on this cell library should be developed in the future.
Acknowledgements The authors would like to thank Prof. Hayakawa, Dr. Wang, and Dr. Hidaka. The part of this work was performed through Special Coordination
Funds for promoting Science and Technology of the Ministry of Education, Culture, Sports, Science and Technology of the Japanese Government.
References [1] M. Dorojevets et al., IEEE Trans. Appl. Supercond. 11 (2001) 326. [2] N. Yoshikawa et al., Physica C 357–360 (2001) 1529. [3] S. Nagasawa et al., IEEE Trans. Appl. Supercond. 5 (1995) 2447. [4] http://www.cadence.com. [5] K. Likharev, V. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 3. [6] http://gamayun.physics.sunysb.edu/RSFQ. [7] N. Mori et al., Physica C 357–360 (2001) 1557.
A single flux quantum standard logic cell library S. Yorozu a
a,*
, Y. Kameda a, H. Terai b, A. Fujimaki c, T. Yamada c, S. Tahara
a
Fundamental Research Laboratories, NEC Corporation, 34 Miyukigaoka, Tsukuba 305-8501, Ibaraki, Japan b Kansai Advanced Research Center, Communication Research Laboratory, Kobe 651-2492, Japan c Department of Quantum Engineering, Nagoya University, Furo-cho, Chikusaku, Nagoya 464-8603, Japan Received 27 September 2001; accepted 25 December 2001
Abstract To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable. Ó 2002 Elsevier Science B.V. All rights reserved. PACS: 85.25.Cp; 85.25.Hv Keywords: Superconducting devices; Single flux quantum logic; Cell-based design; RSFQ logic cell library
1. Introduction Single flux quantum (SFQ) large-scale digital circuits can operate at several tens GHz speed with very low power consumption; no other digital circuits have such characteristics. However, very few large-scale random-logic-circuits are reported because no design methodologies have been established as yet [1]. A top-down design methodology and tools should be established. The cell-based method is one candidate for the SFQ circuit design [2]. In cell-based design, a digital circuit is made by *
Corresponding author. Tel.: +81-298-50-2634; fax: +81298-56-6139. E-mail address: [email protected] (S. Yorozu).
placing many standard cells in a cell library that have elemental logic functions such as and, or, d-flip flop, Josephson transmission line (JTL), etc. We developed a new SFQ logic cell library for cell-based circuit design. We call it CONNECT (co-operation of Nagoya University––NEC-CRL teams) cell library. The CONNECT cells were designed with as small interactions between cells as possible. In layout level, we defined a minimum standard size and made cell height and width a multiple of the standard size for convenience of placing. A digital level simulator can be used for estimating the performance of the circuits made by using CONNECT library. Thus we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. In addition,
0921-4534/02/$ - see front matter Ó 2002 Elsevier Science B.V. All rights reserved. PII: S 0 9 2 1 - 4 5 3 4 ( 0 2 ) 0 1 7 5 9 - 8
1472
S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
this library can be used with higher-level design tools such as automatic placement and layout. In this paper, we report on the CONNECT cell library.
2. Cell library The CONNECT cell library was established based on NEC standard fabrication technology (2.5 kA/cm2 and 2 lm 2 lm Josephson junction technology) and Cadence design systems Corporation CAD software [3,4]. We added our specially developed software to the CAD system for adapting the SFQ circuit to the CAD system because a SFQ circuit is different from conventional semiconductor circuit technologies. A state of the art CONNECT cell library consists of about 100 cells. The CONNECT cell is separated into three levels; digital level, analog level, and layout level. Fig. 1 shows the design flow chart of the CONNECT cell. The digital level is described by using Verilog hardware description language, which includes information on pins, operation (behavior), operation delay time, and timing between clock and data signals (setup time, hold time, etc.). The analog level is a circuit diagram described by Josephson junctions, inductances, and resistances. The circuit is designed according to digital level behavior description. In circuit design, we referred to conventional circuits and concepts as prototypes [5,6]. At the analog level design, it is important to minimize interactions between cells for expanding circuit scale. To minimize interactions, we have designed and optimized circuits by
Fig. 1. Design flow chart.
Fig. 2. Analog level design scheme.
using the scheme shown in Fig. 2. We defined the rules as follows. (1) The critical current of a Josephson junction of JTL is 0.2 mA. (2) As shown in Fig. 2, the target circuit is added a half JTL on both input and output ports for checking leak currents, and then optimized. In optimization, circuit parameters of half JTLs are unchanged. (3) All input and output ports of the target circuit have an 0.15 mA bias current injection port. (4) All currents that flow between the target circuit and the half-JTL (Iin and Iout in Fig. 2) are less than 0.0015 mA.
Fig. 3. Standard cell example (JTL: Josephson transmission line).
S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
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Table 1 Characteristics of principal cells Logic
Number of JJ
Delay time (ps)
JTL Pulse splitter Confluence buffer TFF AND XOR NOT DFF NDRO
2 3 7 7 13 11 10 6 11
7.6 8.3 13.2 13.2 17 12.2 12.2 10.2 18.7
We optimized circuit parameters by using optimization software that was developed at Nagoya University [7]. All circuit parameter values have been optimized for obtaining the widest margins even if all critical currents are shifted 10%. After optimizing, we re-simulated the circuit, obtained timing parameters, and changed to digital level timing parameter values. The layout level is the physical layout data of the cell circuit consistent with the analog level design result. All layout data were based on the NEC fabrication technology. We defined a minimum standard cell size as 40 lm and made cell height and width a multiple of the size. Input and output ports were also placed at 40 lm steps with 20 lm shifted from the edge of the cell. Fig. 3 shows an example of a JTL cell analog and layout levels. Its layout size is 40 lm 40 lm, which is standard minimum size of the CONNECT cells. Table 1 shows characteristics of the principal cells. All cells were optimized, but we continue to reoptimize them for the best performance.
3. Cell-based design using the library Fig. 4 shows a example of a cell-based circuit design. The first step is to design a target circuit without considering a wiring delay as shown in Fig. 4(a). This circuit was designed by using a deep pipeline scheme. Next, we replace all wirings with wiring-cells (JTL cell) as shown in Fig. 4(b). In SFQ circuit design, it is difficult to adjust the time sequence between data and clock timing signals. In order to have design flexibility, there are many kinds of wiring cells having various delay times
Setup time (ps)
)7 2 19.4 )2.3 )2.0
Hold time (ps)
Bias margin
7.7 )1 10.0 2.4 2.0
þ40% þ24% þ31% þ32% þ38% þ16% þ40% þ16%
to to to to to to to to
)24% )20% )31% )16% )21% )28% )44% )16%
and sizes. As a result, the schematic, Fig. 4(b), also has some kinds of wiring cells. The circuit was simulated using Verilog-XL (Cadence Design systems software) without analog time domain dynamic simulations until all timing constraints were satisfied. After completing the circuit design (Fig. 4(b)), the circuit’s digital schematic was converted automatically to a physical layout level. This circuit has 135 cells (419 Josephson junctions). Without using the CONNECT cell library, it is difficult to design such random logic circuits. Using this circuit layout, a test chip was fabricated using 2-lm NEC standard fabrication technology (Fig. 4(c)), and we experimentally demonstrated successful operation which has 9% dc bias margin. There are differences between typical margin of cells of Table 1 and the circuit margin. This difference is resulted that each cell has different operating point because the critical current of the tested chip is shifted about 10% from designed value. From bias margin measurements of each cell, overlapped margin is around 9%, which is similar to the whole circuit margin. As a result, the testing result means that our cell library is reliable within the present state of cells. For making robust cells and library, each cells needs further optimization.
4. Conclusion We have developed a new cell library for largescale SFQ digital circuits, which is called CONNECT. All CONNECT cells are optimized for obtaining the widest margins and minimizing interactions between cells. At present, there are
1474
S. Yorozu et al. / Physica C 378–381 (2002) 1471–1474
Fig. 4. Example of cell-based design.
totally over 100 cells in the library so that it is useful to make wiring. For estimating the reliability of the library, we designed, fabricated, and tested a sample circuit. We demonstrated its correct operations, and thereby confirmed the cell library is reliable. We continue to re-optimize cells for the best performance. In addition, automatic placement––routing methodologies and tools based on this cell library should be developed in the future.
Acknowledgements The authors would like to thank Prof. Hayakawa, Dr. Wang, and Dr. Hidaka. The part of this work was performed through Special Coordination
Funds for promoting Science and Technology of the Ministry of Education, Culture, Sports, Science and Technology of the Japanese Government.
References [1] M. Dorojevets et al., IEEE Trans. Appl. Supercond. 11 (2001) 326. [2] N. Yoshikawa et al., Physica C 357–360 (2001) 1529. [3] S. Nagasawa et al., IEEE Trans. Appl. Supercond. 5 (1995) 2447. [4] http://www.cadence.com. [5] K. Likharev, V. Semenov, IEEE Trans. Appl. Supercond. 1 (1991) 3. [6] http://gamayun.physics.sunysb.edu/RSFQ. [7] N. Mori et al., Physica C 357–360 (2001) 1557.