- Email: [email protected]
A Software Product Line Design Based Approach for Real-time Scheduling of Reconfigurable Embedded Systems
Accepted Manuscript A Software Product Line design based approach for real-time scheduling of reconfigurable embedded systems Hamza Gharsellaoui, Jihen Maazoun, Nadia Bouassida, Samir Ben Ahmed, Hanene Ben-Abdallah PII:
S0747-5632(17)30268-6
DOI:
10.1016/j.chb.2017.04.026
Reference:
CHB 4925
To appear in:
Computers in Human Behavior
Received Date: 2 October 2015 Revised Date:
24 March 2017
Accepted Date: 9 April 2017
Please cite this article as: Gharsellaoui H., Maazoun J., Bouassida N., Ahmed S.B. & Ben-Abdallah H., A Software Product Line design based approach for real-time scheduling of reconfigurable embedded systems, Computers in Human Behavior (2017), doi: 10.1016/j.chb.2017.04.026. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
A Software Product Line Design Based Approach for Real-Time Scheduling of Reconfigurable Embedded Systems
SC
RI PT
Hamza Gharsellaoui1, Jihen Maazoun2, Nadia Bouassida3, Samir Ben Ahmed4 and Hanene Ben-Abdallah5 1 National Engineering School of Carthage (ENIC), Carthage University, Tunisia 2 Mir@cl Laboratory, Faculty of Economics and Management of Sfax, Sfax University, Tunisia 3 Higher Institute of Computer Science and Multimedia of Sfax, Sfax University, Tunisia 4 Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Tunisia 5 FCIT, King Abdulaziz University, Jeddah, Kingdom of Saudi Arabia [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
M AN U
Keywords: Real-Time Scheduling, Reconfigurable Embedded Systems, SPL Design, UML Marte.
Abstract
1. Introduction
EP
TE D
In this paper, we deal with the development of dynamically reconfigurable embedded systems in terms of the production of execution schedules of system tasks (feasible configuration) under hard real-time constraints. Indeed, several real-time embedded systems must be dynamically reconfigured to account for hardware/software faults and/or maintain acceptable performances. Depending on the run-time environment, some reconfigurations might be unfeasible, i.e., they violate some real-time constraints of the system. More specifically, we propose an approach that starts from a set of reconfigurations to construct a Software Product Line (SPL) that can be reused in a predictive and organized way to derive real-time embedded systems. To make sure that the SPL offers various feasible reconfigurations, we define an intelligent agent (IA) that automatically checks the system’s feasibility after a reconfiguration scenario is applied on a multiprocessor embedded system. This agent dynamically determines precious technical solutions to define a new product whenever a reconfiguration is unfeasible. The set of products thus defined by the agent can then be unified into an SPL. The originality of our approach is its capacity to extract, from the unfeasible configurations of an embedded system, an SPL design enriched with real-time constraints and modeled with a UML Marte profile. The SPL design can assist in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time requirements and to obtain a feasible system under normal and overload conditions.
AC C
Nowadays, due to the growing class of portable systems, such as personal computing and communication devices, embedded and real-time systems contain new complex software which is increasing by the time. This complexity is growing because many available software development models don’t take into account the specific needs of embedded and systems development. The software engineering principles for embedded system should address specific constraints such as hard timing constraints, limited memory and power use, predefined hardware platform technology, and hardware costs. On the other hand, the new generations of embedded control systems are addressing new criteria such as flexibility and agility [1]. For these reasons, there is a need to develop tools, methodologies in embedded software engineering and dynamic reconfigurable embedded control systems as an independent discipline. 1.1. Definitions
ACCEPTED MANUSCRIPT Each embedded system is a subset of tasks. Each task is characterized by its worst case execution times p,ψh
p,ψ h
, an offset (release time) ai
reconfiguration scenario processor p, (p
ψ h (h ∈
, a period
Ti
p,ψ h
and a deadline
p ,ψ h
Di
for each
1...M, we assume that we have M reconfiguration scenarios) and on each
∈ 1..K, we assume that we have K identical processors numbered from 1 to K), and n real-time
tasks numbered from 1 to n that composed a feasible subset of tasks entitled The general goal is to be reassured that any reconfiguration scenario ψ
h
ξold
and need to be scheduled [1].
changing the implementation of the
RI PT
(WCETs) Ci
embedded system does not violate real-time constraints: i.e. the system is feasible and meets real-time constraints even if we change its implementation after any reconfiguration scenario. In [2] and in order to obtain this optimization, the authors propose an intelligent agent-based architecture in which a software agent is reconfiguration scenario ψ
SC
deployed to dynamically adapt the system to its environment by applying reconfiguration scenarios. A means the addition, removal or update of tasks in order to save the whole system on
h
the occurrence of hardware/software faults, or also to improve its performance when random disturbances
M AN U
happen at run-time. In this paper, a reconfiguration scenario means a definition of a new Software Product Lines (SPL) which ensures predictive and organized software reuse. This process starts from the current tasks parameters to identify a product line in a bottom-up approach. In our work, a sporadic task is described by minimum inter-arrival time
Pi
p,ψ h p,ψh
case execution time (WCETs) Ci
p,ψ which is assumed to be equal to its relative deadline D h and a worst i for each reconfiguration scenario
ψ h and on each processor p.
TE D
A random disturbance is defined in the current paper as any random internal or external event allowing the addition of tasks that we assume sporadic or removal of sporadic/periodic tasks to adapt the system’s behavior. Indeed, a hard real-time system typically has a mixture of off-line and on-line workloads and assumed to be feasible before any reconfiguration scenarioψ
h
. The off-line requests support the normal functions of the
EP
system while the on-line requests are sporadic tasks to handle external events such as operator commands and recovery actions which are usually unpredictable.
AC C
1.2. Preliminaries For this reason and in this original work, we propose a new optimal scheduling algorithm based on the dynamic priorities scheduling Earliest Deadline First (EDF) algorithm principles on each processor p and for each dynamic reconfiguration scenario ψ
h
in order to obtain the feasibility of the system at run-time, meeting real-
time constraints of this system. According to [3], a hyperperiod is defined as HP = ζ ,2* LCM where LCM is the well-known Least Common Multiple of the tasks periods and
ζ
+ ζ ,
is the largest task offset. This
algorithm, in our original paper assumes that sporadic tasks span no more than one hyperperiod of the periodic tasks
HP ( p ,ψ h ) = ζ
( p ,ψ h )
,2* LCM + ζ
Common Multiple of tasks periods and
ζ
( p ,ψ h )
( p ,ψ h )
, where
LCM ( p ,ψ h )
is the well-known Least
is the largest task offset of all tasks
( p ,ψ )
τk
h
for each
ACCEPTED MANUSCRIPT reconfiguration scenario ψ
h
on each processor p. The problem is how to construct a software product lines
(SPL) based on the shared task set variable parameters of the failed (unfeasible) embedded system that forms a feature. A feature is seen in [4], as an end user, visible characteristic of the system. To represent the variability in an SPL, a feature model (diagram) is used to specify the SPL variants and variation points; it indicates the features and the constraints (and, or, require, etc) relating the features to one another [5]. A feature model can be derived through SPL development process either in top down [6] or a bottom-up [7], [8], [9] approach.
RI PT
According to [10], a top-down development process starts with a domain analysis to construct the feature model of an SPL and it’s often used for not well explored application domains and requires a high expertise in the applications domain. In contrast, a bottom-up process identifies the mandatory and variable features from the source code of a set of product variants belonging to the same domain. For this reason, we propose in our current and original work a bottom-up approach that extracts from the current task parameters the SPL design enriched
SC
with real-time constraints presented by the critical multiprocessor embedded system. Indeed, our approach proposes a bottom-up SPL design method that adapts it for extracting both the feature models from the task set parameters and the UML Marte profile that we call SPL-UML-Marte. According to the work reported in [11],
M AN U
this method is:
Firstly extracts the SPL design (class and sequence diagrams) of the different task set parameters of the multiprocessor embedded system by applying reverse engineering techniques.
Secondly, it uses the Formal Concept Analysis (FCA) technique proposed by [12], [13] to unify the design of the different parameters of the unfeasible multiprocessor embedded system to extract the design of the SPL. To do so, we use at the same time the Latent Semantic Indexing (LSI) technique defined by the authors in [14] to extract the feature model from the new parameters of the multiprocessor unfeasible embedded system.
TE D
Finally, the enriched SPL is modeled with a UML Marte profile that assists in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time constraints and requirements and to obtain a feasible system under normal and overload conditions and this is an efficient point of the originality of
EP
our work. To obtain these results, the intelligent agent calculates the residual time
( p ,ψ ) before and after h
Ri
each addition scenario and calculates the minimum of those proposed solutions in order to obtain
( p,ψ )opt Re spk h . Where
AC C
( p,ψ ) Re spk h optimal noted
( p,ψ )opt Re spk h
is the minimum of
the response time of the current system under study given by the following equation = ( p ,ψ h )
M in (R e sp k ,1
,
( p ,ψ h )
R e spk ,2
,
( p ,ψ h )
R e sp k ,3
,
( p ,ψ h )
R e sp k ,4
,
( p ,ψ h )
R e sp k ,5
,
( p ,ψ h )
R e sp k ,6
,
( p ,ψ h )
R e sp k ,7
To calculate these previous values ( p ,ψ h )
R e sp k ,1
,
( p ,ψ h )
R e spk ,2
,
( p ,ψ h )
R e sp k ,3
,
( p ,ψ h )
R e sp k ,4
,
( p ,ψ h )
R e sp k ,5
, we proposed new theoretical concepts R ( p ,ψ h ) , S ( p ,ψ h ) , s ( p ,ψ h ) , i i i
,
( p ,ψ h )
R e sp k ,6
,
( p ,ψ h )
R e sp k ,7
f i( p ,ψ h ) and Li( p ,ψ h ) for the case
)
ACCEPTED MANUSCRIPT of real-time sporadic operating system (OS) tasks. Where
( p ,ψ
Si
( p ,ψ ) is the residual time of task ( p ,ψ h ) , h σ
Ri
i
) ( p ,ψ h ) , ( p ,ψ h ) is the last release time of task h denotes the first release time of taskσ si i
f i( p ,ψ h ) denotes the estimated finishing time of task σ i( p ,ψ h ) and Li( p ,ψ h ) σ i( p ,ψ h ) for each reconfiguration scenario ψ h
σ i( p ,ψ h ) ,
denotes the laxity of task
and on each processor p.
RI PT
A tool RT-SPL-Reconfig is developed in this work to support all the services offered by the agent. This proposed tool entitled RT-SPL-Reconfig is developed based on the visual studio environment used as a software platform and coded with C# language. The feasibility of the system is evaluated after each reconfiguration scenario ψ and on each processor p to be offered by the agent.
h
SC
The organization of the paper is as follows. Section 2 introduces the state of the art of the proposed approach and gives the basic guarantee algorithm. In Section 3, we present the related work of the new approach for optimal scheduling theory. Section 4 presents the SPL-UML Marte as a profile for software product lines. Section 5
M AN U
presents the contribution of the proposed work and shows how this work is a significant extension to the state of the art of EDF scheduling and discusses all the steps of the proposed approach research. In section 6 we use a mobile phone as a use case study. Section 7 summarizes the main results and presents the conclusion of the proposed approach and describes the intended future works.
2. System Model and Assumptions
In this section we will present the state of the art of the proposed approach and the basic guarantee algorithm.
TE D
2.1. State of the Art Nowadays, several interesting studies have been published to develop reconfigurable embedded control systems. In [15] Marian et al. propose a static reconfiguration technique for the reuse of tasks that implement a broad range of systems. The work in [16] proposes a methodology based on the human intervention to dynamically reconfigure tasks of considered systems. In [17], an ontology-based agent is proposed by Vyatkin et al. to
EP
perform systems reconfigurations according to user requirements and also the environment evolution. Window-constrained scheduling is proposed in [18], which is based on an algorithm named dynamic windowconstrained scheduling (DWCS). The research work in [19] provides a window-constrained-based method to
AC C
determine how much a task can increase its computation time, without missing its deadline under EDF scheduling. In [19], a window-constrained execution time can be assumed for reconfigurable tasks in n among m windows of jobs. In the current paper, a window constrained schedule is used to separate old and new tasks that assumed sporadic on each processor p and after each reconfiguration scenarioψ
h
. Old and new tasks are
located in different windows to schedule the system with a minimum response time. In [20], a window constrained schedule is used to schedule the system with low power consumption. In the following, we only consider periodic and sporadic tasks. Few results have been proposed to deal with deadline assignment problem. Baruah, Buttazzo and Gorinsky in [1] propose to modify the deadlines of a task set to minimize the output, seen as secondary criteria of this work. So, we note that the optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration scenario ψ
h
is that we propose in the current
ACCEPTED MANUSCRIPT original work in which we give solutions computed and presented by the intelligent agent for users to respond to their requirements.
Running Example 1: To illustrate the key point of the proposed dynamic reconfiguration approach, we consider as a set of 5 characterized tasks, shown in Table 1, as a motivational example. 2
C
D
and
τ .τ E
A
and
τ
B
are periodic tasks and all the rest
1
1
2
A
B
(τ C ,τ D andτ E ) are sporadic tasks.
RI PT
S y s = τ ,τ
ξ = Sys U Sys S y s = τ ,τ and
Each task can be executed immediately after its arrival and must be finished by its deadline. First, at time t, Sys1
U = ∑ CT 2
is feasible because the processor utilization factor
i =1
i
= 0.30 ≤ 1. We suppose after, that a
i
utilization becomes
U =∑ 5
i =1
SC
reconfiguration scenario is applied at time t1 to add 3 new sporadic tasks (τ C ,τ D andτ E ) . The new processor Ci = 1 .2 1 f 1 . Therefore the system is unfeasible. In the following tables Ti
M AN U
(table 1 and table 2), the first column represents the task identifier, the second column represents the release time, the third column represents the deadline of each task which is less than or equal to its period in these examples of real time tasks, the fourth column represents the period and the five column represents the worst case execution time (WCET) of each task.
* Pi is the inter-arrival time. ai
0 0 5 5 11
Di
Ti = Pi*
Ci
10 20 15 8 12
10 20 -
2 2 5 4 1
TE D
Task A B C D E
EP
Table 1: The characteristics of the 5 tasks
To illustrate the key point of the proposed dynamically approach, we assume that there are K identical processors numbered from 1 to K, and n real-time tasks numbered from 1 to n that composed a feasible subset of
ξ
AC C
tasks entitled
old
and need to be scheduled. At time t and before the application of the reconfiguration scenario
ψ h , each one of the tasks of
ξ
o ld
is feasible, e.g. the execution of each instance in each processor is finished
before the corresponding deadline and the tasks are not assumed to be arranged in any specific order. Every processor p assigns a set of periodic tasks
TS
= {τ 1p , τ 2p , ..., τ np } . This allocation is made with an
P
allowance algorithm at the time of the design, for example by using one of the well-known techniques: first-fit (FF), next-fit (NF), best-fit (BF), worst-fit (WF). These tasks are independent and can be interrupted at any time. Every task
τ ip has an execution time (Worst Case Execution Time) Cip , one period Ti p and a deadline Dip which p
is assumed to be less than or equal to its period, e.g. Di
≤ Ti p . Every task instance k has to respect its absolute
ACCEPTED MANUSCRIPT deadline, namely the kth authority of the task
τ ip named τ ip,k must
be completed before time
Dip,k = (k − 1)Ti p + Dip .We express all the measures of time (e.g. periods, the deadlines, the calculations) as being multiple of the tick of the processor clock. Every processor p will execute its tasks in local by using EDF, it means that the priorities
Pi p of periodic tasks are dynamic and the scheduler guarantees that every instance of
every task will run before its deadline. These tasks are handled by a global scheduler (GS), which assigns them,
RI PT
to processors by using the state informations of the local schedulers. Moreover, under EDF scheduling, a task will fit on a processor as long as the total utilization of all tasks assigned to that processor does not exceed unity (the total utilization factor = 1). Finally, for reasons of simplicity, we assume that all the overheads of context exchange, scheduling of tasks and the preemption of the tasks and the migration cost of the tasks are equal to zero because we assume that all the processors of our embedded systems are identical and as a consequence
We assume now the arrival at run-time of a second subset
reconfiguration scenario ψ
h
C urrent
( t1 ) composed
ξ = C u rren t ψh
of n+m tasks. In this case a
Sysψ h means the modification of its ψh
Sys
( t1 ) = ξ
o ld
Uξ
is a subset of old tasks which are not affected by the reconfiguration scenario ψ
ξ
TE D
ξ o ld
Sys
is applied. The reconfiguration of the system
implementation that will be as follows at time t1:
Where
ξnew which is composed of m real-time tasks at time
M AN U
t1 (t1 = t + ∆t). We have a system
SC
there is no more switching time.
implement the system before the time t1) and
ψh
EP
ξ
= ξ o ld U ξ
h
n ew (e.g. they
new is a subset of new tasks in the system. We assume
that an updated task is considered as a new one at time t1. When the reconfiguration scenarioψ time t1, two cases exist:
ψh
h
is applied at
•
If tasks of
•
agent, Otherwise, the agent should provide different solutions for users in order to re-obtain the system’s
h
ψ
h
new
are feasible, then no reaction should be done by the
AC C
ψ
feasibility.
Running Example 2: In this section, we demonstrate the performance of our proposed approach for both periodic synchronous and
asynchronous, and sporadic tasks. The simulation runs on our tool RT-SPL-Reconfig and proven by the real-time simulator Cheddar [21] with a task set composed of old tasks for each reconfiguration scenario ψ
h
p,ψ (ξold ) and new tasks (ξnew ) on the processor p h
.We illustrate with a simplified example to ease the understanding of our
approach. The task set considered for this example is given in table 2 and is composed of 10 tasks. The sum of utilization of all tasks is equal to 426.1%. We have 3 identical processors in our system to schedule these tasks.
ACCEPTED MANUSCRIPT In this case, we assume that each task’s deadline is less than or equal to its period. The worst case execution times, deadlines and the time periods of all tasks are generated randomly. According to [3], a hyperperiod is defined as HP = ζ ,2* LCM
ζ
periods and
+ ζ , where LCM is the well-known Least Common Multiple of the tasks
is the largest task offset This algorithm, in our original paper assumes that sporadic tasks span no
more than one hyperperiod of the periodic tasks H P ( p ,ψ h ) = ζ
( p ,ψ h )
LCM ( p ,ψ h ) of all tasks
,2* LCM + ζ
is the well-known Least Common Multiple of tasks periods and
( p ,ψ )
τk
ζ
( p ,ψ h )
( p ,ψ h )
, where
RI PT
is the largest task offset
h for each reconfiguration scenario ψ on each processor p. In our work, the system h
runs for time units equal to hyper-period of periodic tasks because if it is feasible in this mentioned hyper-period,
SC
then we obtain the feasibility during all the running- time according to [3].
Also, in this experiment, our task set example is initially implemented by 5 characterized old tasks old
= {τ 1 ;τ 2 ;τ 3 ;τ 4 ;τ 5 } ) . These tasks are feasible because the processor utilization factor U = 1.19 ≤ 3.
These
tasks
should
meet
all
required
deadlines
defined
in
user
M AN U
(ξ
requirements
and
we
have
F easib ility ( C u rren t ξ ( t ) ) ≡ T ru e . o ld
Firstly, tasks are partitioned; task processor 2 while tasks
τ1
is affected to the first processor. Also,
1,0
)
= 0.285 ≤ 1 while the utilization factors of the processor 2 and the processor 3 are calculated as
follows:
2,0 ( 2) C 2 U = ∑ i2 = 0.372 ≤ 1 ; i =1 Ti 3 3,0 ( 2) C 3 U = ∑ i3 = 0.533 ≤ 1 . i =1 Ti
AC C
•
EP
2
•
τ 1 utilization factor is the same as the first processor 1 utilization
TE D
(U
We suppose that a first reconfiguration scenario ψ
ξ ψ new = {τ 6 ;τ 7 ;τ 8 ;τ 9 ;τ 10 } . 1
are affected to the
τ 4 and τ 5 are affected to the processor 3. We have three sets of local tasks. As there is
only one task on the first processor, then task factor
τ 2 and τ 3
1
(h = 1) is applied at time t1 to add 5 new tasks ψ1
The new processor utilization factor becomes
Therefore the system is unfeasible. Feasibility (
C u r r e n tξ
ψ
1
t
U = 4.261f 3
time units.
) = False. Indeed, if the number
of tasks increases, then the overload of the system increases too. Our optimal earliest deadline first (OEDF) algorithm is based on the following Guarantee Algorithm which is presented by Buttazzo and Stankovic in [22]. Indeed, OEDF algorithm is an extended and improved version of Guarantee Algorithm that usually guarantees the system’s feasibility.
ACCEPTED MANUSCRIPT 2.2. Guarantee Algorithm The dynamic, on-line, guarantee test in terms of residual time, which is a convenient parameter to deal with both normal and overload conditions, is presented here.
Algorithm GUARANTEE ( ξ ; σ a ) Begin
RI PT
t = get current time (); R0 = 0; d0 = t;
σa
in the ordered task linked list;
SC
Insert
ξ ' = ξ Uσ a ;
For each task
σa
σ a'
in the task set ξ ; '
such that i ≥ k do {
Ri = Ri−1 + (di - di−1) - ci;
If (Ri < 0) then return (”Not Guaranteed”);
Else return (” Guaranteed”) End.
3. Related Work
TE D
}
M AN U
k = position of
EP
This research work is based on the work reported in [11] where we have proposed a simple approach for the intelligence adaptation of a set of reconfigurations to construct a Software Product Line (SPL) that can be reused
AC C
in a predictive and organized way to derive real-time embedded systems. We propose to extend this previous proposed approach to real-time scheduling of embedded control systems, memory overload and low-power consumption constraints. Before describing in details our original proposed work, we will present some related works dealing with reconfigurations and real-time scheduling of embedded systems.
3.1. Real-Time Embedded Systems Scheduling Theory Today, real-time embedded systems are found in many diverse application areas including; automotive electronics, avionics, telecommunications, space systems, medical imaging, and consumer electronics. In all of these areas, there is rapid technological progress. Companies building embedded real-time systems are driven by a profit motive. To succeed, they aim to meet the needs and desires of their customers by providing systems that are more capable, more flexible, and more effective than their competition, and by bringing these systems to market earlier. This desire for technological progress has resulted in a rapid increase in both software complexity
ACCEPTED MANUSCRIPT and the processing demands placed on the underlying hardware [3]. In recent works, many real-time systems rely on the EDF scheduling algorithm in the case of uniprocessor scheduling theory. This algorithm has been shown to be optimal under many different conditions. For example, for independent, preemptable tasks, on a uniprocessor, EDF is optimal in the sense that if any algorithm can find a schedule where all tasks meet their deadlines, then EDF can meet the deadlines [23]. To address demands for increasing processor performance, silicon vendors no longer concentrate wholly on the miniaturization needed to increase
RI PT
processor clock speeds, as this approach has led to problems with both high power consumption and excessive heat dissipation. Instead, there is now an increasing trend towards using multiprocessor platforms for high-end real-time applications [3].
For these reasons, we will use in our work the case of real-time scheduling on homogeneous multiprocessor platforms. Before presenting our original contribution, we will present some definitions below. According to [1],
SC
each periodic task is described by an initial offset ai (activation time), a worst-case execution time (WCET) Ci, a relative deadline Di and a period Ti.
According to [22], each sporadic task is described by minimum inter-arrival time Pi which is assumed to be equal to its relative deadline Di, and a worst-case execution time (WCET) Ci. Hence, a sporadic task set will be
= {σ i ( Ci , Di ) ; i = 1..m} . Reconfiguration policies in the current paper are
M AN U
denoted as follows: Sys2
classically distinguished into two strategies: static and dynamic reconfigurations. Static reconfigurations are applied off-line to modify the assumed system before any system could start, whereas dynamic reconfigurations are dynamically applied at run-time, which can be further divided into two cases: manual reconfigurations applied by users and automatic reconfigurations applied by intelligent agents [1], [20]. This paper focuses on the dynamic reconfigurations of assumed mixture of off-line and on-line workloads that should meet deadlines
this assumption does not hold.
TE D
defined according to user requirements. The extension of the proposed algorithm should be straightforward when
3.2. Existing UML Profiles for SPL
EP
Several studies (e.g., [24], [6], [25]) have been interested in modeling product lines with UML 2.0, the standard for object-oriented analysis and design. In particular, they focused on defining profiles to manage the concept of variability in the SPL. The proposed UML profiles contain stereotypes, tagged values and constraints that can be
AC C
used to extend the UML meta-model. Claub [24] proposes a UML profile that extends the meta-model of the UML class diagram with the stereotypes <> and <>. The optionality of a model element can be expressed with the stereotype <>. Moreover the profile provides values for specifying the time in which the variability and optionality will be included in the design of the product line. Meta-classes extended by these stereotypes are: Class, Component, Package, collaboration and association. This work is a purely static approach and does not include proposals for behavioral modeling. The Triskell team in [6] proposed a similar approach and added an extension of the meta-model of the sequence diagram. For the static aspect, the authors proposed a set of stereotypes for the class diagram (Optionality, Variation, and Variant). For the dynamic aspect, the authors proposed a set of stereotypes for the sequence diagram (optional-lifeline, optional Interaction, variation, variant). Overall, existing UML profiles propose extensions that illustrate the variability of SPL. However, they focused essentially on the design without
ACCEPTED MANUSCRIPT considering the feature model and did not add features information to their diagrams. This information is very useful in case of feature evolution.
4. SPL-UML Marte: A Profile for Software Product Lines In this section, we present our UML Marte profile named SPL-UML Marte.
RI PT
4.1. Extensions for Class Diagrams In the context of SPL, the IA proposes to introduce different types of variability that are modeled using the following stereotypes:
• <> is used to specify optionality in UML Marte class diagrams. The optionality can concern classes, packages, attributes or oper ations.
stereotype applies for classes only.
SC
• <> is used to specify recommendation in UML Marte class diagrams. The recommendation
• <> is used to specify obligatory elements in UML Marte class diagrams. The obligatory stereotype can concern classes, packages, attributes or operations.
diagrams. It is represented by bold line.
M AN U
• <> is used to specify obligatory relation between classes in UML Marte class
• <> is used to specify optionality relation between classes in UML Marte class diagrams. It is represented by dashed line.
• <> is used to specify an alternative relation between classes in UML Marte class diagrams. • <> is used to specify in which feature it is. The stereotype can concern classes, packages, attributes or operations.
TE D
4.2. Extensions for Sequence Diagrams
Based on the [11] work, in our profile, the UML Marte sequence diagram is extended with the following stereotypes:
• <> is used to specify optionality in UML Marte sequence diagrams. The optionality can concern objects, actors or operations.
EP
• <> is used to specify obligatory elements in UML Marte sequence diagrams. The obligatory stereotype can concern objects, actors or operations.
AC C
• <> is used to specify obligatory relations between objects, actors. It is represented by bold line.
• <> is used to specify optionality between objects, actors. It is represented by dashed line. • <> is used to specify an alternative relation between objects, actors (ifelse). It is represented by solid line.
• <> is used to specify in which feature it is. The stereotype can concern 395 objects, actors.
4.3. Definition of OCL Constraints The introduction of variability using new stereotypes improves genericity but can generate some inconsistencies (e.g., if a mandatory subclass specializes an optional super class, the resulting model is incoherent). Thus, in order to ensure SPL design consistency, the IA defines some OCL constraints that are applied to structural and behavioral views of SPL design.
ACCEPTED MANUSCRIPT C1: Each package, class, method, attribute or association in an optional feature, must be stereotyped <>.
RI PT
Context Feature inv self.isStereotyped ("Optional") implies self.package − >forAll ((p|p.package.isStereotyped ("Optional") or (p|p.package.isStereotyped ("mandatory")) and self.class − >forAll ((c|c.class.isStereotyped ("Optional") or (c|c.class.isStereotyped ("mandatory")) and self.method − >forAll ((m|m.method.isStereotyped ("Optional") or (m|m.method.isStereotyped ("mandatory") )and self.attribute − >forAll ((a|a.attribute.isStereotyped ("Optional") or (a|a.attribute.isStereotyped ("mandatory")) and self.association − >forAll ((as|as.association.isStereotyped ("Optional") or (as|as.association.isStereotyped ("mandatory"))
C2: Each package, class, method, attribute or association in a mandatory feature, must be stereotyped
SC
<> or <>
M AN U
Context Feature inv self.isStereotyped ("mandatory") implies self.package − >forAll ((p|p.package.isStereotyped ("Optional") or (p|p.package.isStereotyped ("mandatory")) and self.class − >forAll ((c|c.class.isStereotyped ("Optional") or (c|c.class.isStereotyped ("mandatory"))and self.method − >forAll ((m|m.method.isStereotyped ("Optional") or (m|m.method.isStereotyped ("mandatory") )and self.attribute − >forAll ((a|a.attribute.isStereotyped ("Optional") or (a|a.attribute.isStereotyped("mandatory")) and self.association − >forAll ((as|as.association.isStereotyped ("Optional") or (as|as.association.isStereotyped ("mandatory"))
TE D
Overall, our SPL-UML Marte profile differs from existing profiles by introducing new stereotypes like <>, <>, <>, <>. Moreover, it defines OCL constraints which can be applied to structural and behavioral views.
5. Real-Time Reconfigurable Scheduling Based on SPL Design Extraction
EP
In this section we will present our contribution that consists of the modifications done by the IA of old parameters e.g., all parameters obtained as a result of the SPL will be used as input to our failed system in order
AC C
to obtain the feasibility of the embedded system under study. The SPL-UML Marte notation will be used to describe SPL designs extracted through our bottom-up process which extracts, from the task set parameters of multiprocessors embedded systems, the SPL design enriched with information and real-time constraints extracted from the feature model. Our approach (illustrated in figure 1) contains four steps (Name harmonization, Reverse engineering, Feature model extraction and Design elements extraction and SPL design construction) which we detail next.
RI PT
ACCEPTED MANUSCRIPT
Figure 1: A bottom-up Process to Extract SPL Design Enriched with SPL-UML Marte
classes, methods and attribute
425
SC
5.1. Name Harmonization This pre-processing step starts by identifying the semantic correspondences between the names of packages, names through interrogating WordNet. The semantic relations are examined in
M AN U
the following order: the equivalence (Synonyms), the string extension (Meronyms), and then the generalization (Hypernyms) [5]:
• Synonyms(C1,· · ·,Cn): implies that the names are either identical or synonym, e.g., Mobile-Mobile and PhoneMobile.
• Hypernyms(C1; C2,· · ·,Cn): implies the name C1 is a generalization of the specific names C2 ,· · ·, Cn, e.g., Media-Video.
• Meronyms(C1; C2): implies that the name C1 is a string extension of the name of the class C2, e.g., Image-
TE D
NameImage. *
At the end of the pre-processing step, all semantically related names would be harmonized and can then be analyzed through the FCA in the features identification step.
EP
5.2. Reverse Engineering Once the names are harmonized, the IA reverses engineer the code to construct the class and sequence diagrams required in the feature extraction step of our process. A class diagram contains all classes and enumerates the
AC C
relationships between them (association, inheritance, composition, aggregation). A sequence diagram contains Lifelines, message, operation, object...
5.3. Feature Model Extraction In this step, the IA uses FCA and LSI to extract the commonalities and variability among the harmonized task set parameters. Before explaining this step, let us first overview the basics of FCA and LSI. FCA [13] is a method of data analysis, whose main idea is to analyze data described through the relationships among a particular set of data elements. In our approach, the data represent the task set parameters being analyzed and recalculated by the IA in order to handle real-time requirements; the data description is represented through a table where the processors constitute the rows while tasks and their states (packages, classes, methods, attributes) constitute the columns of the table. From the table, a concept lattice is derived. The concept lattice permits, in the first time, to define commonalities and variations among all processors.
ACCEPTED MANUSCRIPT The top element of the lattice indicates that certain objects have elements in common (i.e., common elements), while the bottom element of the lattice show that certain attributes fit common objects (variations). Common blocks and blocks variation are composed of atomic blocks of variation representing only one feature. Besides the blocks, the lattice also indicates the relationships among elements. The following relationships (Mandatory, Optional, Xor, Require and AND) can be automatically derived from the sparse representation of the lattice and presented to the analyst.
RI PT
In our work, we suppose that the task set parameters, recalculated by the IA, are implemented by different developers. Consequently, the processors may have different structures. For example, a class in one processor can be replaced in a second processor with two classes where the attributes and methods of the original class are distributed. Moreover, since all the processors belong to the same embedded system, there are semantic relationships among the words used in the names. To define the similarity, we apply LSI. It allows to measure
SC
the similarity degree between names for packages, classes, methods and attributes.
Informally, LSI assumes that words that always appear together are related [26]. Consequently, the IA uses LSI and FCA to identify
475
features based on the textual similarity. Similarity between lines is described by a
M AN U
similarity matrix where the columns and rows represent lines vectors. LSI uses each line in the block of variations as a query to retrieve all lines similar to it, according to a cosine similarity. We use in our work based on the IA, the threshold for cosine similarity that equals to 0.70 [26]. The result of LSI used as input parameters for the FCA to group the similar tasks based on the lexical similarity and on the feasibility criteria. Thus, any task that hasn’t similar task feasibility criteria will be ignored. This process permits to identify atomic blocks of variations (Feature).
The next step in our process determines the hierarchy and constraints among features and finalizes the feature
TE D
model construction. This phase has a threshold motivation. First, the features which are composed of many elements (tasks) (package, classes, attributes, methods) are renamed based on the frequency of the names of its tasks. In addition, the organization and structure of the features are also retrieved based on the semantic criteria. In fact, to retrieve the organization of the features, we use the semantic criterion: • Hypernyms(FeatureN1, FeatureN2) − − −− > FeatureN1 is the parent of FeatureN2
EP
• Str extention(FeatureN1, FeatureN2) −− > FeatureN1 OR FeatureN2 • Synonyms(FeatureN1, FeatureN2) − − −− > FeatureN1 XOR FeatureN2
AC C
In fact, Hypernyms allow constructing the hierarchy of feature models and Str extention and Synonyms permit to determine constraints.
Finally, the constraints between the different features that are extracted with FCA and LSI are verified and some others are added based on the semantic criteria and on the real-time properties. At the end of this last step, all the features would be collected by the IA in a feature model to specify the variations between the task set parameters.
5.4. Design Elements Extraction and SPL Design Extraction In order to tolerate differences among the design of the task set parameters, we adapt the original FCA technique [26]: here, the FCA is applied by the IA to extract the common elements and the variable elements of the design. Afterward, a concept lattice is derived. The top element of the lattice indicates the common elements while the bottom element of the lattice shows variations of certain attributes. This process permits us, first, to derive design enriched with optional and mandatory.
ACCEPTED MANUSCRIPT The organization and structure of the SPL design is retrieved based on the following construct rules: • R1: Each mandatory class will be presented with her mandatory elements (attribute, method). • R2: If a relationship is mandatory, then the association ends are mandatory and it will be present in the design. • R3: If a relationship has a startAssociation or an endAssociation mandatory, will be present in the design and the optional startAssociation or endAssociation will be present and stereotyped ”recommended”. • R4: The rest of the optional element will be present in the design according to the degree of its presence in all
RI PT
the class’ diagrams. Finally, the IA proposes to represent the design of the SPL using our UML Marte profile enriched with the information and real-time constraints extracted from the feature model generated in order to re-obtain the
M AN U
SC
feasibility of embedded systems under study.
Figure 2: Part of the Formal Context Describing Mobile Systems by Class Diagram Elements.
6. Case Study
Our mobile phone SPL example is a software product family with nine tasks.
TE D
Our approach takes as input the task set parameters of a set of tasks in this application domain. To extract the class diagram, we reverse engineered the code and constructed a class diagram as discussed in section 4.2. The class diagram of processors after reverse engineering is shown in figure 3. In order to tolerate some differences among the class’ diagram, we apply the FCA to analyze elements of class diagrams. The data description is represented through a table where the processors constitute the rows, while the classes’ diagrams elements
EP
(packages, classes, methods, attributes) and relationship between classes constitute the columns of the table. After that, a concept lattice is derived (see figure 4). This later defines the commonalities and the task set variations among all processors. Due to space limitations, we apply FCA on four processors (see figure 2).
AC C
The top elements of the lattice indicate that some objects have features in common. These latter are mandatory in the class diagram, however, the others are optional. Applying FCA, LSI and semantic criteria, all the features are collected in a feature model to specify the variations between these processors [5]. The feature model of the mobile system is shown in Figure 5; the features with white circles are Optional while the features with black circles are Mandatory. In the second step, we perform the SPL design construction. In fact, all mandatory classes will be present with their mandatory methods and attributes.
M AN U
SC
RI PT
ACCEPTED MANUSCRIPT
Figure 3: The lattice for the formal context.
In the mobile phone example, the class ”PlayMediaScreen” and its attributes (tasks) ”back” and ”stop” and methods ”PlayMediaScreen()”,”PausePlay”, ”startPlay” are mandatory. Then, all mandatory relationship 550 will be presented like ”R1:C1-C2” (see figure 2). Every relationship having an associationEnd mandatory will be
TE D
presented like ”R2:C2-C4” and ”R3:C2-C3”.
Finally, the class diagram corresponding to the SPL is derived. This diagram is enriched by information extracted from the feature model illustrated in figure 5. As illustrated in figure 6, the classes have different stereotypes. For example, AddMediToAlbum belongs to the feature Media while startImage belongs to the feature Image. Now, the IA applies these output results as input parameters to the embedded system under study
EP
and the performance of the real-time scheduling is become more efficient. This is due to the fact that the reconfiguration issues are increased. Indeed, the intelligent agent should define the different solutions generated
AC C
by the SPL feature model as input parameters. In this case, the best solution that satisfies functional requirements and gives the minimum utilization factor of the system was chosen. This best solution ameliorates also the response time and hence the chances of executing more new tasks are increased as well. These results were suggested by the tool RT-SPL-Reconfig and give a feasible system which is proven also by the real-time simulator Cheddar [21].
SC
RI PT
ACCEPTED MANUSCRIPT
M AN U
Figure 4: The lattice for the formal context.
AC C
EP
TE D
Figure 5: The feature model result.
Figure 6: The class diagram result.
ACCEPTED MANUSCRIPT 7. Conclusion In this paper, we first reviewed existing works for reconfigurable homogeneous multiprocessor systems to be implemented by sporadic and periodic OS tasks that should meet real-time constraints. In this work, we propose an optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration for the minimization of the response time of constrained deadline real-time tasks and proven it correct. Secondly, we defined a new Software Product Lines (SPL) which ensures predictive and organized software reuse. This process starts from the current tasks parameters to identify a product line in a bottom-up approach. Our new
RI PT
original approach extracts from the unfeasible embedded system, the SPL design enriched with real-time constraints presented by the critical embedded systems. The enriched SPL is modeled with a UML Marte profile that assists in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time requirements.
Finally and in our future works, we are examining how to take advantage of the SPL-UML Marte notation to
SC
propose a maintenance process for SPL with the Reconfigurable real-time embedded systems. We plan also in future works to study reconfigurations of real-time tasks of distributed embedded systems to define new
M AN U
Software Product Lines satisfying real-time requirements.
8. References
[1] H. Gharsellaoui, M. Khalgui, S. B. Ahmed, Feasible Automatic Reconfigurations of Real-Time OS Tasks, isbn13: 9781466602946 Edition, IGI-Global Knowledge, USA, 2012.
TE D
[2] H. Gharsellaoui, M. Khalgui, S. B. Ahmed, An edf-based scheduling algorithm for real-time reconfigurable sporadic tasks, icsoft 2013: 377-388 Edition, Proceedings of the 8th International Joint Conference on Software Technologies, Reykjavik, Iceland, 2013.
EP
[3] V. Brocal, P. Balbastre, R. Ballester, L. Ripoll, Task period selection to minimize hyperperiod, Emerging Technologies & Factory Automation (ETFA), IEEE conference on, pp.1-4, 2011, 16th Edition, doi:10.1109/ETFA.2011.6059178, Toulouse, France, 2011.
AC C
[4] K. Kang, S. Cohen, J. Hess, W. Novak, A. Peterson, Feature-oriented domain analysis (foda) feasibility study,, Technical report CMU/SEI-90-TR-21, Software Engineering Institute,Carnegie Mellon University,. [5] J. Maazoun, N. Bouassida, H. Ben-Abdallah, A. Seria, Feature model extraction from product source codes based on the semantic aspect, icsoft2013: 154-161 Edition, Proceedings of the 8th International Joint Confer ence on Software Technologies, Reykjavik, Iceland, 2013. [6] T. Ziadi, Manipulation de lignes de produits en uml, These de doctorat, Universite de Rennes 1. [7] T. Ziadi, L. Frias, M. A. A. da Silva, M. Ziane, Feature identification from the source code of product variants (2012) 417–422. [8] S. She, R. Lotufo, T. Berger, A. Wesowski, K. Czarnecki, Reverse engineering feature models (2011) 461– 470. [9] R. Al-Msie’Deen, A. Seriai, M. Huchard, C. Urtado, S. Vauttier, H. Salman, An approach to recover feature models from object-oriented source code,in: Day Product Line 2012, 2012.
ACCEPTED MANUSCRIPT [10] J. Maazoun, N. Bouassida, H. Ben-Abdallah, A bottom up spl design method,, 2nd International Conference on Model-Driven Engineering and Software Development,. [11] H. Gharsellaoui, J.Maazoun, N. Bouassida, S. B. Ahmed, H. Ben-Abdallah, A real-time scheduling of reconfigurable os tasks with a bottom-up spl design approach, Proceedings of the 10th International Conference on Evaluation of Novel Approaches to Software Engineering, ENASE (2015) 169–176.
RI PT
[12] H. Gharsellaoui, S. B. Ahmed, Real-Time Reconfigurable Scheduling of Aperiodic OS Tasks, Proceedings of the 13th International Symposium on Parallel and Distributed Computing, ISPDC (2014) 156–161. [13] B. Ganter, R. Wille, Formal concept analysis: Mathematical foundations Springer-Verlag.
SC
[14] D. Binkley, D. Lawrie, Information retrieval applications in software maintenance and evolution, In Encyclopedia of Software Engineering (2011), 454–43. [15] C. Angelov, K. Sierszecki, N. Marian, Design models for reusable and reconfigurable state machines, L.T. Yang et al., Eds., Proc. of Embedded Ubiquitous Comput., 2005.
M AN U
[16] M. Rooker, C. Subder, T. Strasser, A. Zoitl, O. Hummer, G. Ebenhofer, Zero downtime reconfiguration of distributed automation systems: The CEDAC approach, 3rd Edition, Int. Conf. Indust. Appl. Holonic Multi Agent Syst., Regensburg, 2007. [17] Y. Al-Safi, V. Vyatkin, An ontology-based reconfiguration agent for intelligent mechatronic systems, 4th Edition, Int. Conf. Hol. Multi-Agent Syst. Manuf., vol. 4659, pp. 114-126, Regensburg, Germany, 2007. [18] R. West, K. Schwan, Dynamic window-constrained scheduling for multimedia applications, 6th Edition, IEEE 6th Int. Conf. Multi. Comput. Syst., 1999. [19] P. Balbastre, I. Ripoll, A. Crespo, Schedulability analysis of window-constrained execution time tasks for real-time control, 14th Edition, 14th Euromicro Conf. Real- Time Syst., 2002.
TE D
[20] X. Wang, M. Khalgui, dynamic low power reconfigurations of real-time embedded systems, 1st Edition, Proc. Pervas. Embedded Comput. Commu. Syst., Algarve, Portugal, 2011. [21] J. Legrand, L. Singhoff, Cheddar: a Flexible Real Time Scheduling Frame work, ACM SIGAda Ada Letters, volume 24, number 4, pages 1-8. Edited by ACM Press, ISSN: 1094-3641, 2004.
EP
[22] G. Buttazzo, J. Stankovic, RED: Robust Earliest Deadline Scheduling, 3rd Edition, Int. Workshop On Responsive Computing Systems, Austin, 1993.
AC C
[23] M. Dertouzos, Control Robotics: The Procedural Control of Physical Processes, Proceedings of the IFIP Congress, 1974. [24] M. ClauB, Modeling variability with uml. s.l., Dresden University of Technology. [25] H. Gomaa, . Designing software product lines with uml., Software Engineering Workshop Tutorial. [26] D. Binkley, D. Lawrie, Information retrieval applications in software maintenance and evolution, In Encyclopedia of Software Engineering (2011), 454–43.
ACCEPTED MANUSCRIPT
Highlights
Highly real-time reconfigurable scheduling of embedded systems.
The implementation of an Intelligent Agent that checks the system's feasibility.
The Intelligent Agent provides precious technical solutions by defining new
RI PT
SPL.
The proposed approach extracts from the unfeasible embedded system the SPL design.
Enriched SPL is modeled with UML Marte profile that assists in its
AC C
EP
TE D
M AN U
SC
comprehension.
S0747-5632(17)30268-6
DOI:
10.1016/j.chb.2017.04.026
Reference:
CHB 4925
To appear in:
Computers in Human Behavior
Received Date: 2 October 2015 Revised Date:
24 March 2017
Accepted Date: 9 April 2017
Please cite this article as: Gharsellaoui H., Maazoun J., Bouassida N., Ahmed S.B. & Ben-Abdallah H., A Software Product Line design based approach for real-time scheduling of reconfigurable embedded systems, Computers in Human Behavior (2017), doi: 10.1016/j.chb.2017.04.026. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
A Software Product Line Design Based Approach for Real-Time Scheduling of Reconfigurable Embedded Systems
SC
RI PT
Hamza Gharsellaoui1, Jihen Maazoun2, Nadia Bouassida3, Samir Ben Ahmed4 and Hanene Ben-Abdallah5 1 National Engineering School of Carthage (ENIC), Carthage University, Tunisia 2 Mir@cl Laboratory, Faculty of Economics and Management of Sfax, Sfax University, Tunisia 3 Higher Institute of Computer Science and Multimedia of Sfax, Sfax University, Tunisia 4 Faculty of Mathematical, Physical and Natural Sciences of Tunis, Tunis El Manar University, Tunisia 5 FCIT, King Abdulaziz University, Jeddah, Kingdom of Saudi Arabia [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
M AN U
Keywords: Real-Time Scheduling, Reconfigurable Embedded Systems, SPL Design, UML Marte.
Abstract
1. Introduction
EP
TE D
In this paper, we deal with the development of dynamically reconfigurable embedded systems in terms of the production of execution schedules of system tasks (feasible configuration) under hard real-time constraints. Indeed, several real-time embedded systems must be dynamically reconfigured to account for hardware/software faults and/or maintain acceptable performances. Depending on the run-time environment, some reconfigurations might be unfeasible, i.e., they violate some real-time constraints of the system. More specifically, we propose an approach that starts from a set of reconfigurations to construct a Software Product Line (SPL) that can be reused in a predictive and organized way to derive real-time embedded systems. To make sure that the SPL offers various feasible reconfigurations, we define an intelligent agent (IA) that automatically checks the system’s feasibility after a reconfiguration scenario is applied on a multiprocessor embedded system. This agent dynamically determines precious technical solutions to define a new product whenever a reconfiguration is unfeasible. The set of products thus defined by the agent can then be unified into an SPL. The originality of our approach is its capacity to extract, from the unfeasible configurations of an embedded system, an SPL design enriched with real-time constraints and modeled with a UML Marte profile. The SPL design can assist in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time requirements and to obtain a feasible system under normal and overload conditions.
AC C
Nowadays, due to the growing class of portable systems, such as personal computing and communication devices, embedded and real-time systems contain new complex software which is increasing by the time. This complexity is growing because many available software development models don’t take into account the specific needs of embedded and systems development. The software engineering principles for embedded system should address specific constraints such as hard timing constraints, limited memory and power use, predefined hardware platform technology, and hardware costs. On the other hand, the new generations of embedded control systems are addressing new criteria such as flexibility and agility [1]. For these reasons, there is a need to develop tools, methodologies in embedded software engineering and dynamic reconfigurable embedded control systems as an independent discipline. 1.1. Definitions
ACCEPTED MANUSCRIPT Each embedded system is a subset of tasks. Each task is characterized by its worst case execution times p,ψh
p,ψ h
, an offset (release time) ai
reconfiguration scenario processor p, (p
ψ h (h ∈
, a period
Ti
p,ψ h
and a deadline
p ,ψ h
Di
for each
1...M, we assume that we have M reconfiguration scenarios) and on each
∈ 1..K, we assume that we have K identical processors numbered from 1 to K), and n real-time
tasks numbered from 1 to n that composed a feasible subset of tasks entitled The general goal is to be reassured that any reconfiguration scenario ψ
h
ξold
and need to be scheduled [1].
changing the implementation of the
RI PT
(WCETs) Ci
embedded system does not violate real-time constraints: i.e. the system is feasible and meets real-time constraints even if we change its implementation after any reconfiguration scenario. In [2] and in order to obtain this optimization, the authors propose an intelligent agent-based architecture in which a software agent is reconfiguration scenario ψ
SC
deployed to dynamically adapt the system to its environment by applying reconfiguration scenarios. A means the addition, removal or update of tasks in order to save the whole system on
h
the occurrence of hardware/software faults, or also to improve its performance when random disturbances
M AN U
happen at run-time. In this paper, a reconfiguration scenario means a definition of a new Software Product Lines (SPL) which ensures predictive and organized software reuse. This process starts from the current tasks parameters to identify a product line in a bottom-up approach. In our work, a sporadic task is described by minimum inter-arrival time
Pi
p,ψ h p,ψh
case execution time (WCETs) Ci
p,ψ which is assumed to be equal to its relative deadline D h and a worst i for each reconfiguration scenario
ψ h and on each processor p.
TE D
A random disturbance is defined in the current paper as any random internal or external event allowing the addition of tasks that we assume sporadic or removal of sporadic/periodic tasks to adapt the system’s behavior. Indeed, a hard real-time system typically has a mixture of off-line and on-line workloads and assumed to be feasible before any reconfiguration scenarioψ
h
. The off-line requests support the normal functions of the
EP
system while the on-line requests are sporadic tasks to handle external events such as operator commands and recovery actions which are usually unpredictable.
AC C
1.2. Preliminaries For this reason and in this original work, we propose a new optimal scheduling algorithm based on the dynamic priorities scheduling Earliest Deadline First (EDF) algorithm principles on each processor p and for each dynamic reconfiguration scenario ψ
h
in order to obtain the feasibility of the system at run-time, meeting real-
time constraints of this system. According to [3], a hyperperiod is defined as HP = ζ ,2* LCM where LCM is the well-known Least Common Multiple of the tasks periods and
ζ
+ ζ ,
is the largest task offset. This
algorithm, in our original paper assumes that sporadic tasks span no more than one hyperperiod of the periodic tasks
HP ( p ,ψ h ) = ζ
( p ,ψ h )
,2* LCM + ζ
Common Multiple of tasks periods and
ζ
( p ,ψ h )
( p ,ψ h )
, where
LCM ( p ,ψ h )
is the well-known Least
is the largest task offset of all tasks
( p ,ψ )
τk
h
for each
ACCEPTED MANUSCRIPT reconfiguration scenario ψ
h
on each processor p. The problem is how to construct a software product lines
(SPL) based on the shared task set variable parameters of the failed (unfeasible) embedded system that forms a feature. A feature is seen in [4], as an end user, visible characteristic of the system. To represent the variability in an SPL, a feature model (diagram) is used to specify the SPL variants and variation points; it indicates the features and the constraints (and, or, require, etc) relating the features to one another [5]. A feature model can be derived through SPL development process either in top down [6] or a bottom-up [7], [8], [9] approach.
RI PT
According to [10], a top-down development process starts with a domain analysis to construct the feature model of an SPL and it’s often used for not well explored application domains and requires a high expertise in the applications domain. In contrast, a bottom-up process identifies the mandatory and variable features from the source code of a set of product variants belonging to the same domain. For this reason, we propose in our current and original work a bottom-up approach that extracts from the current task parameters the SPL design enriched
SC
with real-time constraints presented by the critical multiprocessor embedded system. Indeed, our approach proposes a bottom-up SPL design method that adapts it for extracting both the feature models from the task set parameters and the UML Marte profile that we call SPL-UML-Marte. According to the work reported in [11],
M AN U
this method is:
Firstly extracts the SPL design (class and sequence diagrams) of the different task set parameters of the multiprocessor embedded system by applying reverse engineering techniques.
Secondly, it uses the Formal Concept Analysis (FCA) technique proposed by [12], [13] to unify the design of the different parameters of the unfeasible multiprocessor embedded system to extract the design of the SPL. To do so, we use at the same time the Latent Semantic Indexing (LSI) technique defined by the authors in [14] to extract the feature model from the new parameters of the multiprocessor unfeasible embedded system.
TE D
Finally, the enriched SPL is modeled with a UML Marte profile that assists in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time constraints and requirements and to obtain a feasible system under normal and overload conditions and this is an efficient point of the originality of
EP
our work. To obtain these results, the intelligent agent calculates the residual time
( p ,ψ ) before and after h
Ri
each addition scenario and calculates the minimum of those proposed solutions in order to obtain
( p,ψ )opt Re spk h . Where
AC C
( p,ψ ) Re spk h optimal noted
( p,ψ )opt Re spk h
is the minimum of
the response time of the current system under study given by the following equation = ( p ,ψ h )
M in (R e sp k ,1
,
( p ,ψ h )
R e spk ,2
,
( p ,ψ h )
R e sp k ,3
,
( p ,ψ h )
R e sp k ,4
,
( p ,ψ h )
R e sp k ,5
,
( p ,ψ h )
R e sp k ,6
,
( p ,ψ h )
R e sp k ,7
To calculate these previous values ( p ,ψ h )
R e sp k ,1
,
( p ,ψ h )
R e spk ,2
,
( p ,ψ h )
R e sp k ,3
,
( p ,ψ h )
R e sp k ,4
,
( p ,ψ h )
R e sp k ,5
, we proposed new theoretical concepts R ( p ,ψ h ) , S ( p ,ψ h ) , s ( p ,ψ h ) , i i i
,
( p ,ψ h )
R e sp k ,6
,
( p ,ψ h )
R e sp k ,7
f i( p ,ψ h ) and Li( p ,ψ h ) for the case
)
ACCEPTED MANUSCRIPT of real-time sporadic operating system (OS) tasks. Where
( p ,ψ
Si
( p ,ψ ) is the residual time of task ( p ,ψ h ) , h σ
Ri
i
) ( p ,ψ h ) , ( p ,ψ h ) is the last release time of task h denotes the first release time of taskσ si i
f i( p ,ψ h ) denotes the estimated finishing time of task σ i( p ,ψ h ) and Li( p ,ψ h ) σ i( p ,ψ h ) for each reconfiguration scenario ψ h
σ i( p ,ψ h ) ,
denotes the laxity of task
and on each processor p.
RI PT
A tool RT-SPL-Reconfig is developed in this work to support all the services offered by the agent. This proposed tool entitled RT-SPL-Reconfig is developed based on the visual studio environment used as a software platform and coded with C# language. The feasibility of the system is evaluated after each reconfiguration scenario ψ and on each processor p to be offered by the agent.
h
SC
The organization of the paper is as follows. Section 2 introduces the state of the art of the proposed approach and gives the basic guarantee algorithm. In Section 3, we present the related work of the new approach for optimal scheduling theory. Section 4 presents the SPL-UML Marte as a profile for software product lines. Section 5
M AN U
presents the contribution of the proposed work and shows how this work is a significant extension to the state of the art of EDF scheduling and discusses all the steps of the proposed approach research. In section 6 we use a mobile phone as a use case study. Section 7 summarizes the main results and presents the conclusion of the proposed approach and describes the intended future works.
2. System Model and Assumptions
In this section we will present the state of the art of the proposed approach and the basic guarantee algorithm.
TE D
2.1. State of the Art Nowadays, several interesting studies have been published to develop reconfigurable embedded control systems. In [15] Marian et al. propose a static reconfiguration technique for the reuse of tasks that implement a broad range of systems. The work in [16] proposes a methodology based on the human intervention to dynamically reconfigure tasks of considered systems. In [17], an ontology-based agent is proposed by Vyatkin et al. to
EP
perform systems reconfigurations according to user requirements and also the environment evolution. Window-constrained scheduling is proposed in [18], which is based on an algorithm named dynamic windowconstrained scheduling (DWCS). The research work in [19] provides a window-constrained-based method to
AC C
determine how much a task can increase its computation time, without missing its deadline under EDF scheduling. In [19], a window-constrained execution time can be assumed for reconfigurable tasks in n among m windows of jobs. In the current paper, a window constrained schedule is used to separate old and new tasks that assumed sporadic on each processor p and after each reconfiguration scenarioψ
h
. Old and new tasks are
located in different windows to schedule the system with a minimum response time. In [20], a window constrained schedule is used to schedule the system with low power consumption. In the following, we only consider periodic and sporadic tasks. Few results have been proposed to deal with deadline assignment problem. Baruah, Buttazzo and Gorinsky in [1] propose to modify the deadlines of a task set to minimize the output, seen as secondary criteria of this work. So, we note that the optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration scenario ψ
h
is that we propose in the current
ACCEPTED MANUSCRIPT original work in which we give solutions computed and presented by the intelligent agent for users to respond to their requirements.
Running Example 1: To illustrate the key point of the proposed dynamic reconfiguration approach, we consider as a set of 5 characterized tasks, shown in Table 1, as a motivational example. 2
C
D
and
τ .τ E
A
and
τ
B
are periodic tasks and all the rest
1
1
2
A
B
(τ C ,τ D andτ E ) are sporadic tasks.
RI PT
S y s = τ ,τ
ξ = Sys U Sys S y s = τ ,τ and
Each task can be executed immediately after its arrival and must be finished by its deadline. First, at time t, Sys1
U = ∑ CT 2
is feasible because the processor utilization factor
i =1
i
= 0.30 ≤ 1. We suppose after, that a
i
utilization becomes
U =∑ 5
i =1
SC
reconfiguration scenario is applied at time t1 to add 3 new sporadic tasks (τ C ,τ D andτ E ) . The new processor Ci = 1 .2 1 f 1 . Therefore the system is unfeasible. In the following tables Ti
M AN U
(table 1 and table 2), the first column represents the task identifier, the second column represents the release time, the third column represents the deadline of each task which is less than or equal to its period in these examples of real time tasks, the fourth column represents the period and the five column represents the worst case execution time (WCET) of each task.
* Pi is the inter-arrival time. ai
0 0 5 5 11
Di
Ti = Pi*
Ci
10 20 15 8 12
10 20 -
2 2 5 4 1
TE D
Task A B C D E
EP
Table 1: The characteristics of the 5 tasks
To illustrate the key point of the proposed dynamically approach, we assume that there are K identical processors numbered from 1 to K, and n real-time tasks numbered from 1 to n that composed a feasible subset of
ξ
AC C
tasks entitled
old
and need to be scheduled. At time t and before the application of the reconfiguration scenario
ψ h , each one of the tasks of
ξ
o ld
is feasible, e.g. the execution of each instance in each processor is finished
before the corresponding deadline and the tasks are not assumed to be arranged in any specific order. Every processor p assigns a set of periodic tasks
TS
= {τ 1p , τ 2p , ..., τ np } . This allocation is made with an
P
allowance algorithm at the time of the design, for example by using one of the well-known techniques: first-fit (FF), next-fit (NF), best-fit (BF), worst-fit (WF). These tasks are independent and can be interrupted at any time. Every task
τ ip has an execution time (Worst Case Execution Time) Cip , one period Ti p and a deadline Dip which p
is assumed to be less than or equal to its period, e.g. Di
≤ Ti p . Every task instance k has to respect its absolute
ACCEPTED MANUSCRIPT deadline, namely the kth authority of the task
τ ip named τ ip,k must
be completed before time
Dip,k = (k − 1)Ti p + Dip .We express all the measures of time (e.g. periods, the deadlines, the calculations) as being multiple of the tick of the processor clock. Every processor p will execute its tasks in local by using EDF, it means that the priorities
Pi p of periodic tasks are dynamic and the scheduler guarantees that every instance of
every task will run before its deadline. These tasks are handled by a global scheduler (GS), which assigns them,
RI PT
to processors by using the state informations of the local schedulers. Moreover, under EDF scheduling, a task will fit on a processor as long as the total utilization of all tasks assigned to that processor does not exceed unity (the total utilization factor = 1). Finally, for reasons of simplicity, we assume that all the overheads of context exchange, scheduling of tasks and the preemption of the tasks and the migration cost of the tasks are equal to zero because we assume that all the processors of our embedded systems are identical and as a consequence
We assume now the arrival at run-time of a second subset
reconfiguration scenario ψ
h
C urrent
( t1 ) composed
ξ = C u rren t ψh
of n+m tasks. In this case a
Sysψ h means the modification of its ψh
Sys
( t1 ) = ξ
o ld
Uξ
is a subset of old tasks which are not affected by the reconfiguration scenario ψ
ξ
TE D
ξ o ld
Sys
is applied. The reconfiguration of the system
implementation that will be as follows at time t1:
Where
ξnew which is composed of m real-time tasks at time
M AN U
t1 (t1 = t + ∆t). We have a system
SC
there is no more switching time.
implement the system before the time t1) and
ψh
EP
ξ
= ξ o ld U ξ
h
n ew (e.g. they
new is a subset of new tasks in the system. We assume
that an updated task is considered as a new one at time t1. When the reconfiguration scenarioψ time t1, two cases exist:
ψh
h
is applied at
•
If tasks of
•
agent, Otherwise, the agent should provide different solutions for users in order to re-obtain the system’s
h
ψ
h
new
are feasible, then no reaction should be done by the
AC C
ψ
feasibility.
Running Example 2: In this section, we demonstrate the performance of our proposed approach for both periodic synchronous and
asynchronous, and sporadic tasks. The simulation runs on our tool RT-SPL-Reconfig and proven by the real-time simulator Cheddar [21] with a task set composed of old tasks for each reconfiguration scenario ψ
h
p,ψ (ξold ) and new tasks (ξnew ) on the processor p h
.We illustrate with a simplified example to ease the understanding of our
approach. The task set considered for this example is given in table 2 and is composed of 10 tasks. The sum of utilization of all tasks is equal to 426.1%. We have 3 identical processors in our system to schedule these tasks.
ACCEPTED MANUSCRIPT In this case, we assume that each task’s deadline is less than or equal to its period. The worst case execution times, deadlines and the time periods of all tasks are generated randomly. According to [3], a hyperperiod is defined as HP = ζ ,2* LCM
ζ
periods and
+ ζ , where LCM is the well-known Least Common Multiple of the tasks
is the largest task offset This algorithm, in our original paper assumes that sporadic tasks span no
more than one hyperperiod of the periodic tasks H P ( p ,ψ h ) = ζ
( p ,ψ h )
LCM ( p ,ψ h ) of all tasks
,2* LCM + ζ
is the well-known Least Common Multiple of tasks periods and
( p ,ψ )
τk
ζ
( p ,ψ h )
( p ,ψ h )
, where
RI PT
is the largest task offset
h for each reconfiguration scenario ψ on each processor p. In our work, the system h
runs for time units equal to hyper-period of periodic tasks because if it is feasible in this mentioned hyper-period,
SC
then we obtain the feasibility during all the running- time according to [3].
Also, in this experiment, our task set example is initially implemented by 5 characterized old tasks old
= {τ 1 ;τ 2 ;τ 3 ;τ 4 ;τ 5 } ) . These tasks are feasible because the processor utilization factor U = 1.19 ≤ 3.
These
tasks
should
meet
all
required
deadlines
defined
in
user
M AN U
(ξ
requirements
and
we
have
F easib ility ( C u rren t ξ ( t ) ) ≡ T ru e . o ld
Firstly, tasks are partitioned; task processor 2 while tasks
τ1
is affected to the first processor. Also,
1,0
)
= 0.285 ≤ 1 while the utilization factors of the processor 2 and the processor 3 are calculated as
follows:
2,0 ( 2) C 2 U = ∑ i2 = 0.372 ≤ 1 ; i =1 Ti 3 3,0 ( 2) C 3 U = ∑ i3 = 0.533 ≤ 1 . i =1 Ti
AC C
•
EP
2
•
τ 1 utilization factor is the same as the first processor 1 utilization
TE D
(U
We suppose that a first reconfiguration scenario ψ
ξ ψ new = {τ 6 ;τ 7 ;τ 8 ;τ 9 ;τ 10 } . 1
are affected to the
τ 4 and τ 5 are affected to the processor 3. We have three sets of local tasks. As there is
only one task on the first processor, then task factor
τ 2 and τ 3
1
(h = 1) is applied at time t1 to add 5 new tasks ψ1
The new processor utilization factor becomes
Therefore the system is unfeasible. Feasibility (
C u r r e n tξ
ψ
1
t
U = 4.261f 3
time units.
) = False. Indeed, if the number
of tasks increases, then the overload of the system increases too. Our optimal earliest deadline first (OEDF) algorithm is based on the following Guarantee Algorithm which is presented by Buttazzo and Stankovic in [22]. Indeed, OEDF algorithm is an extended and improved version of Guarantee Algorithm that usually guarantees the system’s feasibility.
ACCEPTED MANUSCRIPT 2.2. Guarantee Algorithm The dynamic, on-line, guarantee test in terms of residual time, which is a convenient parameter to deal with both normal and overload conditions, is presented here.
Algorithm GUARANTEE ( ξ ; σ a ) Begin
RI PT
t = get current time (); R0 = 0; d0 = t;
σa
in the ordered task linked list;
SC
Insert
ξ ' = ξ Uσ a ;
For each task
σa
σ a'
in the task set ξ ; '
such that i ≥ k do {
Ri = Ri−1 + (di - di−1) - ci;
If (Ri < 0) then return (”Not Guaranteed”);
Else return (” Guaranteed”) End.
3. Related Work
TE D
}
M AN U
k = position of
EP
This research work is based on the work reported in [11] where we have proposed a simple approach for the intelligence adaptation of a set of reconfigurations to construct a Software Product Line (SPL) that can be reused
AC C
in a predictive and organized way to derive real-time embedded systems. We propose to extend this previous proposed approach to real-time scheduling of embedded control systems, memory overload and low-power consumption constraints. Before describing in details our original proposed work, we will present some related works dealing with reconfigurations and real-time scheduling of embedded systems.
3.1. Real-Time Embedded Systems Scheduling Theory Today, real-time embedded systems are found in many diverse application areas including; automotive electronics, avionics, telecommunications, space systems, medical imaging, and consumer electronics. In all of these areas, there is rapid technological progress. Companies building embedded real-time systems are driven by a profit motive. To succeed, they aim to meet the needs and desires of their customers by providing systems that are more capable, more flexible, and more effective than their competition, and by bringing these systems to market earlier. This desire for technological progress has resulted in a rapid increase in both software complexity
ACCEPTED MANUSCRIPT and the processing demands placed on the underlying hardware [3]. In recent works, many real-time systems rely on the EDF scheduling algorithm in the case of uniprocessor scheduling theory. This algorithm has been shown to be optimal under many different conditions. For example, for independent, preemptable tasks, on a uniprocessor, EDF is optimal in the sense that if any algorithm can find a schedule where all tasks meet their deadlines, then EDF can meet the deadlines [23]. To address demands for increasing processor performance, silicon vendors no longer concentrate wholly on the miniaturization needed to increase
RI PT
processor clock speeds, as this approach has led to problems with both high power consumption and excessive heat dissipation. Instead, there is now an increasing trend towards using multiprocessor platforms for high-end real-time applications [3].
For these reasons, we will use in our work the case of real-time scheduling on homogeneous multiprocessor platforms. Before presenting our original contribution, we will present some definitions below. According to [1],
SC
each periodic task is described by an initial offset ai (activation time), a worst-case execution time (WCET) Ci, a relative deadline Di and a period Ti.
According to [22], each sporadic task is described by minimum inter-arrival time Pi which is assumed to be equal to its relative deadline Di, and a worst-case execution time (WCET) Ci. Hence, a sporadic task set will be
= {σ i ( Ci , Di ) ; i = 1..m} . Reconfiguration policies in the current paper are
M AN U
denoted as follows: Sys2
classically distinguished into two strategies: static and dynamic reconfigurations. Static reconfigurations are applied off-line to modify the assumed system before any system could start, whereas dynamic reconfigurations are dynamically applied at run-time, which can be further divided into two cases: manual reconfigurations applied by users and automatic reconfigurations applied by intelligent agents [1], [20]. This paper focuses on the dynamic reconfigurations of assumed mixture of off-line and on-line workloads that should meet deadlines
this assumption does not hold.
TE D
defined according to user requirements. The extension of the proposed algorithm should be straightforward when
3.2. Existing UML Profiles for SPL
EP
Several studies (e.g., [24], [6], [25]) have been interested in modeling product lines with UML 2.0, the standard for object-oriented analysis and design. In particular, they focused on defining profiles to manage the concept of variability in the SPL. The proposed UML profiles contain stereotypes, tagged values and constraints that can be
AC C
used to extend the UML meta-model. Claub [24] proposes a UML profile that extends the meta-model of the UML class diagram with the stereotypes <
ACCEPTED MANUSCRIPT considering the feature model and did not add features information to their diagrams. This information is very useful in case of feature evolution.
4. SPL-UML Marte: A Profile for Software Product Lines In this section, we present our UML Marte profile named SPL-UML Marte.
RI PT
4.1. Extensions for Class Diagrams In the context of SPL, the IA proposes to introduce different types of variability that are modeled using the following stereotypes:
• <
stereotype applies for classes only.
SC
• <
• <
diagrams. It is represented by bold line.
M AN U
• <
• <
• <
TE D
4.2. Extensions for Sequence Diagrams
Based on the [11] work, in our profile, the UML Marte sequence diagram is extended with the following stereotypes:
• <
EP
• <
AC C
• <
• <
• <
4.3. Definition of OCL Constraints The introduction of variability using new stereotypes improves genericity but can generate some inconsistencies (e.g., if a mandatory subclass specializes an optional super class, the resulting model is incoherent). Thus, in order to ensure SPL design consistency, the IA defines some OCL constraints that are applied to structural and behavioral views of SPL design.
ACCEPTED MANUSCRIPT C1: Each package, class, method, attribute or association in an optional feature, must be stereotyped <
RI PT
Context Feature inv self.isStereotyped ("Optional") implies self.package − >forAll ((p|p.package.isStereotyped ("Optional") or (p|p.package.isStereotyped ("mandatory")) and self.class − >forAll ((c|c.class.isStereotyped ("Optional") or (c|c.class.isStereotyped ("mandatory")) and self.method − >forAll ((m|m.method.isStereotyped ("Optional") or (m|m.method.isStereotyped ("mandatory") )and self.attribute − >forAll ((a|a.attribute.isStereotyped ("Optional") or (a|a.attribute.isStereotyped ("mandatory")) and self.association − >forAll ((as|as.association.isStereotyped ("Optional") or (as|as.association.isStereotyped ("mandatory"))
C2: Each package, class, method, attribute or association in a mandatory feature, must be stereotyped
SC
<
M AN U
Context Feature inv self.isStereotyped ("mandatory") implies self.package − >forAll ((p|p.package.isStereotyped ("Optional") or (p|p.package.isStereotyped ("mandatory")) and self.class − >forAll ((c|c.class.isStereotyped ("Optional") or (c|c.class.isStereotyped ("mandatory"))and self.method − >forAll ((m|m.method.isStereotyped ("Optional") or (m|m.method.isStereotyped ("mandatory") )and self.attribute − >forAll ((a|a.attribute.isStereotyped ("Optional") or (a|a.attribute.isStereotyped("mandatory")) and self.association − >forAll ((as|as.association.isStereotyped ("Optional") or (as|as.association.isStereotyped ("mandatory"))
TE D
Overall, our SPL-UML Marte profile differs from existing profiles by introducing new stereotypes like <
5. Real-Time Reconfigurable Scheduling Based on SPL Design Extraction
EP
In this section we will present our contribution that consists of the modifications done by the IA of old parameters e.g., all parameters obtained as a result of the SPL will be used as input to our failed system in order
AC C
to obtain the feasibility of the embedded system under study. The SPL-UML Marte notation will be used to describe SPL designs extracted through our bottom-up process which extracts, from the task set parameters of multiprocessors embedded systems, the SPL design enriched with information and real-time constraints extracted from the feature model. Our approach (illustrated in figure 1) contains four steps (Name harmonization, Reverse engineering, Feature model extraction and Design elements extraction and SPL design construction) which we detail next.
RI PT
ACCEPTED MANUSCRIPT
Figure 1: A bottom-up Process to Extract SPL Design Enriched with SPL-UML Marte
classes, methods and attribute
425
SC
5.1. Name Harmonization This pre-processing step starts by identifying the semantic correspondences between the names of packages, names through interrogating WordNet. The semantic relations are examined in
M AN U
the following order: the equivalence (Synonyms), the string extension (Meronyms), and then the generalization (Hypernyms) [5]:
• Synonyms(C1,· · ·,Cn): implies that the names are either identical or synonym, e.g., Mobile-Mobile and PhoneMobile.
• Hypernyms(C1; C2,· · ·,Cn): implies the name C1 is a generalization of the specific names C2 ,· · ·, Cn, e.g., Media-Video.
• Meronyms(C1; C2): implies that the name C1 is a string extension of the name of the class C2, e.g., Image-
TE D
NameImage. *
At the end of the pre-processing step, all semantically related names would be harmonized and can then be analyzed through the FCA in the features identification step.
EP
5.2. Reverse Engineering Once the names are harmonized, the IA reverses engineer the code to construct the class and sequence diagrams required in the feature extraction step of our process. A class diagram contains all classes and enumerates the
AC C
relationships between them (association, inheritance, composition, aggregation). A sequence diagram contains Lifelines, message, operation, object...
5.3. Feature Model Extraction In this step, the IA uses FCA and LSI to extract the commonalities and variability among the harmonized task set parameters. Before explaining this step, let us first overview the basics of FCA and LSI. FCA [13] is a method of data analysis, whose main idea is to analyze data described through the relationships among a particular set of data elements. In our approach, the data represent the task set parameters being analyzed and recalculated by the IA in order to handle real-time requirements; the data description is represented through a table where the processors constitute the rows while tasks and their states (packages, classes, methods, attributes) constitute the columns of the table. From the table, a concept lattice is derived. The concept lattice permits, in the first time, to define commonalities and variations among all processors.
ACCEPTED MANUSCRIPT The top element of the lattice indicates that certain objects have elements in common (i.e., common elements), while the bottom element of the lattice show that certain attributes fit common objects (variations). Common blocks and blocks variation are composed of atomic blocks of variation representing only one feature. Besides the blocks, the lattice also indicates the relationships among elements. The following relationships (Mandatory, Optional, Xor, Require and AND) can be automatically derived from the sparse representation of the lattice and presented to the analyst.
RI PT
In our work, we suppose that the task set parameters, recalculated by the IA, are implemented by different developers. Consequently, the processors may have different structures. For example, a class in one processor can be replaced in a second processor with two classes where the attributes and methods of the original class are distributed. Moreover, since all the processors belong to the same embedded system, there are semantic relationships among the words used in the names. To define the similarity, we apply LSI. It allows to measure
SC
the similarity degree between names for packages, classes, methods and attributes.
Informally, LSI assumes that words that always appear together are related [26]. Consequently, the IA uses LSI and FCA to identify
475
features based on the textual similarity. Similarity between lines is described by a
M AN U
similarity matrix where the columns and rows represent lines vectors. LSI uses each line in the block of variations as a query to retrieve all lines similar to it, according to a cosine similarity. We use in our work based on the IA, the threshold for cosine similarity that equals to 0.70 [26]. The result of LSI used as input parameters for the FCA to group the similar tasks based on the lexical similarity and on the feasibility criteria. Thus, any task that hasn’t similar task feasibility criteria will be ignored. This process permits to identify atomic blocks of variations (Feature).
The next step in our process determines the hierarchy and constraints among features and finalizes the feature
TE D
model construction. This phase has a threshold motivation. First, the features which are composed of many elements (tasks) (package, classes, attributes, methods) are renamed based on the frequency of the names of its tasks. In addition, the organization and structure of the features are also retrieved based on the semantic criteria. In fact, to retrieve the organization of the features, we use the semantic criterion: • Hypernyms(FeatureN1, FeatureN2) − − −− > FeatureN1 is the parent of FeatureN2
EP
• Str extention(FeatureN1, FeatureN2) −− > FeatureN1 OR FeatureN2 • Synonyms(FeatureN1, FeatureN2) − − −− > FeatureN1 XOR FeatureN2
AC C
In fact, Hypernyms allow constructing the hierarchy of feature models and Str extention and Synonyms permit to determine constraints.
Finally, the constraints between the different features that are extracted with FCA and LSI are verified and some others are added based on the semantic criteria and on the real-time properties. At the end of this last step, all the features would be collected by the IA in a feature model to specify the variations between the task set parameters.
5.4. Design Elements Extraction and SPL Design Extraction In order to tolerate differences among the design of the task set parameters, we adapt the original FCA technique [26]: here, the FCA is applied by the IA to extract the common elements and the variable elements of the design. Afterward, a concept lattice is derived. The top element of the lattice indicates the common elements while the bottom element of the lattice shows variations of certain attributes. This process permits us, first, to derive design enriched with optional and mandatory.
ACCEPTED MANUSCRIPT The organization and structure of the SPL design is retrieved based on the following construct rules: • R1: Each mandatory class will be presented with her mandatory elements (attribute, method). • R2: If a relationship is mandatory, then the association ends are mandatory and it will be present in the design. • R3: If a relationship has a startAssociation or an endAssociation mandatory, will be present in the design and the optional startAssociation or endAssociation will be present and stereotyped ”recommended”. • R4: The rest of the optional element will be present in the design according to the degree of its presence in all
RI PT
the class’ diagrams. Finally, the IA proposes to represent the design of the SPL using our UML Marte profile enriched with the information and real-time constraints extracted from the feature model generated in order to re-obtain the
M AN U
SC
feasibility of embedded systems under study.
Figure 2: Part of the Formal Context Describing Mobile Systems by Class Diagram Elements.
6. Case Study
Our mobile phone SPL example is a software product family with nine tasks.
TE D
Our approach takes as input the task set parameters of a set of tasks in this application domain. To extract the class diagram, we reverse engineered the code and constructed a class diagram as discussed in section 4.2. The class diagram of processors after reverse engineering is shown in figure 3. In order to tolerate some differences among the class’ diagram, we apply the FCA to analyze elements of class diagrams. The data description is represented through a table where the processors constitute the rows, while the classes’ diagrams elements
EP
(packages, classes, methods, attributes) and relationship between classes constitute the columns of the table. After that, a concept lattice is derived (see figure 4). This later defines the commonalities and the task set variations among all processors. Due to space limitations, we apply FCA on four processors (see figure 2).
AC C
The top elements of the lattice indicate that some objects have features in common. These latter are mandatory in the class diagram, however, the others are optional. Applying FCA, LSI and semantic criteria, all the features are collected in a feature model to specify the variations between these processors [5]. The feature model of the mobile system is shown in Figure 5; the features with white circles are Optional while the features with black circles are Mandatory. In the second step, we perform the SPL design construction. In fact, all mandatory classes will be present with their mandatory methods and attributes.
M AN U
SC
RI PT
ACCEPTED MANUSCRIPT
Figure 3: The lattice for the formal context.
In the mobile phone example, the class ”PlayMediaScreen” and its attributes (tasks) ”back” and ”stop” and methods ”PlayMediaScreen()”,”PausePlay”, ”startPlay” are mandatory. Then, all mandatory relationship 550 will be presented like ”R1:C1-C2” (see figure 2). Every relationship having an associationEnd mandatory will be
TE D
presented like ”R2:C2-C4” and ”R3:C2-C3”.
Finally, the class diagram corresponding to the SPL is derived. This diagram is enriched by information extracted from the feature model illustrated in figure 5. As illustrated in figure 6, the classes have different stereotypes. For example, AddMediToAlbum belongs to the feature Media while startImage belongs to the feature Image. Now, the IA applies these output results as input parameters to the embedded system under study
EP
and the performance of the real-time scheduling is become more efficient. This is due to the fact that the reconfiguration issues are increased. Indeed, the intelligent agent should define the different solutions generated
AC C
by the SPL feature model as input parameters. In this case, the best solution that satisfies functional requirements and gives the minimum utilization factor of the system was chosen. This best solution ameliorates also the response time and hence the chances of executing more new tasks are increased as well. These results were suggested by the tool RT-SPL-Reconfig and give a feasible system which is proven also by the real-time simulator Cheddar [21].
SC
RI PT
ACCEPTED MANUSCRIPT
M AN U
Figure 4: The lattice for the formal context.
AC C
EP
TE D
Figure 5: The feature model result.
Figure 6: The class diagram result.
ACCEPTED MANUSCRIPT 7. Conclusion In this paper, we first reviewed existing works for reconfigurable homogeneous multiprocessor systems to be implemented by sporadic and periodic OS tasks that should meet real-time constraints. In this work, we propose an optimal scheduling algorithm based on the EDF principles and on the dynamic reconfiguration for the minimization of the response time of constrained deadline real-time tasks and proven it correct. Secondly, we defined a new Software Product Lines (SPL) which ensures predictive and organized software reuse. This process starts from the current tasks parameters to identify a product line in a bottom-up approach. Our new
RI PT
original approach extracts from the unfeasible embedded system, the SPL design enriched with real-time constraints presented by the critical embedded systems. The enriched SPL is modeled with a UML Marte profile that assists in the comprehension, reconfiguration as well as evolution of the SPL in order to satisfy real-time requirements.
Finally and in our future works, we are examining how to take advantage of the SPL-UML Marte notation to
SC
propose a maintenance process for SPL with the Reconfigurable real-time embedded systems. We plan also in future works to study reconfigurations of real-time tasks of distributed embedded systems to define new
M AN U
Software Product Lines satisfying real-time requirements.
8. References
[1] H. Gharsellaoui, M. Khalgui, S. B. Ahmed, Feasible Automatic Reconfigurations of Real-Time OS Tasks, isbn13: 9781466602946 Edition, IGI-Global Knowledge, USA, 2012.
TE D
[2] H. Gharsellaoui, M. Khalgui, S. B. Ahmed, An edf-based scheduling algorithm for real-time reconfigurable sporadic tasks, icsoft 2013: 377-388 Edition, Proceedings of the 8th International Joint Conference on Software Technologies, Reykjavik, Iceland, 2013.
EP
[3] V. Brocal, P. Balbastre, R. Ballester, L. Ripoll, Task period selection to minimize hyperperiod, Emerging Technologies & Factory Automation (ETFA), IEEE conference on, pp.1-4, 2011, 16th Edition, doi:10.1109/ETFA.2011.6059178, Toulouse, France, 2011.
AC C
[4] K. Kang, S. Cohen, J. Hess, W. Novak, A. Peterson, Feature-oriented domain analysis (foda) feasibility study,, Technical report CMU/SEI-90-TR-21, Software Engineering Institute,Carnegie Mellon University,. [5] J. Maazoun, N. Bouassida, H. Ben-Abdallah, A. Seria, Feature model extraction from product source codes based on the semantic aspect, icsoft2013: 154-161 Edition, Proceedings of the 8th International Joint Confer ence on Software Technologies, Reykjavik, Iceland, 2013. [6] T. Ziadi, Manipulation de lignes de produits en uml, These de doctorat, Universite de Rennes 1. [7] T. Ziadi, L. Frias, M. A. A. da Silva, M. Ziane, Feature identification from the source code of product variants (2012) 417–422. [8] S. She, R. Lotufo, T. Berger, A. Wesowski, K. Czarnecki, Reverse engineering feature models (2011) 461– 470. [9] R. Al-Msie’Deen, A. Seriai, M. Huchard, C. Urtado, S. Vauttier, H. Salman, An approach to recover feature models from object-oriented source code,in: Day Product Line 2012, 2012.
ACCEPTED MANUSCRIPT [10] J. Maazoun, N. Bouassida, H. Ben-Abdallah, A bottom up spl design method,, 2nd International Conference on Model-Driven Engineering and Software Development,. [11] H. Gharsellaoui, J.Maazoun, N. Bouassida, S. B. Ahmed, H. Ben-Abdallah, A real-time scheduling of reconfigurable os tasks with a bottom-up spl design approach, Proceedings of the 10th International Conference on Evaluation of Novel Approaches to Software Engineering, ENASE (2015) 169–176.
RI PT
[12] H. Gharsellaoui, S. B. Ahmed, Real-Time Reconfigurable Scheduling of Aperiodic OS Tasks, Proceedings of the 13th International Symposium on Parallel and Distributed Computing, ISPDC (2014) 156–161. [13] B. Ganter, R. Wille, Formal concept analysis: Mathematical foundations Springer-Verlag.
SC
[14] D. Binkley, D. Lawrie, Information retrieval applications in software maintenance and evolution, In Encyclopedia of Software Engineering (2011), 454–43. [15] C. Angelov, K. Sierszecki, N. Marian, Design models for reusable and reconfigurable state machines, L.T. Yang et al., Eds., Proc. of Embedded Ubiquitous Comput., 2005.
M AN U
[16] M. Rooker, C. Subder, T. Strasser, A. Zoitl, O. Hummer, G. Ebenhofer, Zero downtime reconfiguration of distributed automation systems: The CEDAC approach, 3rd Edition, Int. Conf. Indust. Appl. Holonic Multi Agent Syst., Regensburg, 2007. [17] Y. Al-Safi, V. Vyatkin, An ontology-based reconfiguration agent for intelligent mechatronic systems, 4th Edition, Int. Conf. Hol. Multi-Agent Syst. Manuf., vol. 4659, pp. 114-126, Regensburg, Germany, 2007. [18] R. West, K. Schwan, Dynamic window-constrained scheduling for multimedia applications, 6th Edition, IEEE 6th Int. Conf. Multi. Comput. Syst., 1999. [19] P. Balbastre, I. Ripoll, A. Crespo, Schedulability analysis of window-constrained execution time tasks for real-time control, 14th Edition, 14th Euromicro Conf. Real- Time Syst., 2002.
TE D
[20] X. Wang, M. Khalgui, dynamic low power reconfigurations of real-time embedded systems, 1st Edition, Proc. Pervas. Embedded Comput. Commu. Syst., Algarve, Portugal, 2011. [21] J. Legrand, L. Singhoff, Cheddar: a Flexible Real Time Scheduling Frame work, ACM SIGAda Ada Letters, volume 24, number 4, pages 1-8. Edited by ACM Press, ISSN: 1094-3641, 2004.
EP
[22] G. Buttazzo, J. Stankovic, RED: Robust Earliest Deadline Scheduling, 3rd Edition, Int. Workshop On Responsive Computing Systems, Austin, 1993.
AC C
[23] M. Dertouzos, Control Robotics: The Procedural Control of Physical Processes, Proceedings of the IFIP Congress, 1974. [24] M. ClauB, Modeling variability with uml. s.l., Dresden University of Technology. [25] H. Gomaa, . Designing software product lines with uml., Software Engineering Workshop Tutorial. [26] D. Binkley, D. Lawrie, Information retrieval applications in software maintenance and evolution, In Encyclopedia of Software Engineering (2011), 454–43.
ACCEPTED MANUSCRIPT
Highlights
Highly real-time reconfigurable scheduling of embedded systems.
The implementation of an Intelligent Agent that checks the system's feasibility.
The Intelligent Agent provides precious technical solutions by defining new
RI PT
SPL.
The proposed approach extracts from the unfeasible embedded system the SPL design.
Enriched SPL is modeled with UML Marte profile that assists in its
AC C
EP
TE D
M AN U
SC
comprehension.