A solid state time-division multiplier

138

Annales de l'Association internationale pour le Calczd analogique

A

SOLID

STATE

TIME-DIVISION

N° 3

MULTIPLIER

-

-

Juillet 1962

"

by A. F U C H S ~* a n d H. G A F N I ** SUMMARY A multiplier, which is to form one of the units of a small transistorized analogue computer, is described. The multiplier is of the time division type proposed by Goldberg. Its main parts are, an integrator, switching circuits and a filter amplifier. The design specifications of these elements are derived from the accuracy and bandwidth properties of the multiplier. Tests carried out on an experimental model have shown that the accuracy is better than 0,5 % and the phase shift is less than 2° for 17 cps.

1. Introduction. Several versions of time division multipliers have been described in the literature [1-3], but a treatment of errors an8 frequency response limitations in transistorized versions has not yet appeared. Further, transistorized multipliers already discussed did not meet the accuracy and bandwidth requirements posed by the design of small inexpensive general purpose analogue computers. A suitable block diagram was recently published [4] but details on the circuits and on the accuracy and speed of response were not given. The purpose of this paper is to report an attempt to establish specifications and analyse errors for the different circuits of the multiplier. The principle of operation is the same as that described by Goldberg [1] with the difference that the present realisation uses only solid state elements.

The second variable q-Y, and its negative - - Y , are alternatively switched by $2 to the input of an amplifier A acting as a filter. An output proportional to the product XY is obtained. The time periods T~ and T2 required for the output of the integrator to rise and fall between q-E and --E, may be expressed as 2 ERC T, -- K - - X

[

C

Ix

] I

"

~

L . . . . . . . . . . -Y

.....

III

R/Z

Y

Fig. 1. - - Blockdiagram of the multiplier. closed loop L (shown within dashed lines). The voltage X and another voltage switched by $1 between reference values K and - - K are summed at the input of an integrator I. The time integral (fig. 2) of the output is then applied to a voltage sensitive bistable drcuit, which changes states when the input reaches the voltage limits E and --E. This bistable supplies signals to the electronic switches $1 and $2. * Manuscrit regu le 22 septembre 1961. ** Scientific Department, Israel Ministry of Defence.

T=

K+X

(1)

where R and C are the integrating elements. The average value of the output of A is

Vout =

YT - - 2Y T2 T

(2)

where T denotes the sum of T1 and T.,. Substituting from (1) into (2), it may be seen that the output voltage takes the form

2. The Principle of Operation. A block-diagram of the multiplier is given in figure 1. One of the variables, X, modulates the time division Of a rectangular waveform generated by the

2 ERC ;

XY Vo°t = - K

(3)

3. Specification of the Integrator. Integrator characteristics are determined mainly by the gain, bandwidth and drift of the operational amplifier used. It is convenient to express the gain of a transistorized amplifier in terms of a transfer impedance, ZT, relating output voltage to input current. For the case of the amplifiers considered for the present application, Zw could be approximated in the frequency domain of interest by Zo z (p) (4) 1 q- pTo p denotes the Lalapce operator, To describes the cutv~

Fig. 2 .-- The waveform at the output of the integrator.

139

A. Fuchs : A solid state time-division multiplier

off frequency oo of the amplifier and Zo is the d.c. value of the transfer impedance. The transfer function of the integrator has been found [4] to be

H(p) =

Vo(p) v,(p)

_ ---

z~(p) R[I+pCZ~(p)

(5)

+

~)

+

lu Z,.,

(14)

all notations being explained in figure 3, Z2

x ~

Zo

EOM

(6)

R (1 + p C~,,Zo)

where

Eo,,,= EM(1

l

Substituting (4) into (5) one obtains H(p) = --

ing output voltage (if R,, <
To

Coq = C -b --

(7)

go

Equations (5) and (6) suggest that when the integrator is operated at repetition frequencies even slightly higher than ~oo, the accuracy is not affected. The only change will be that Coq must be substituted for C in the appropriate expressions.

Fig. 3. - - Equivalent drift generators of the operational amplifier.

Eo,~ can be compensated by a change & X (drift referred to X) of the input voltage X if Zi AX = E o • - Z.

(15)

Substituting Eo~ from (14) this takes the form

Errors are however introduced by the finite transfer impedance Zo as detailed below.

k X = EM -b I=Zt

When a step voltage V, is applied to the integrator input, the output as a function of time can be obtained from (5) as follows

The term E• ZffZ. may here be neglected since it does not affect the time division. The relative error originating from drift is

Vo(t) =

[1 - -

exp (.

--)1 (8)

3M --

Zo Ceq

This voltage will reach a predetermined value Vo in a time t~ g'iven by (9) 11 --

Vo -- R % Vi

Vo R

(1

2 Vi Z0

T',. -

2 ERC~q K -- X 2 ERC~a

. (1 +

[~ +

K + X

ER Zo (K -- X) ER

Zo (K + x)

~-

(I +

8z)

8z --

K Z0

ER K (~) .....

([[8)

4. Transistor Switches.

.);

(1o) .l

The transistor has inherent advantages when used as a switch; it introduces however statis and dynamic errors. In its open circuit state, the switch permits the flow of a small current I~o, and when closed, it maintains a small voltage V~. Both I~o and Vc, change with temperature and therefore full compensation is not possible. The resultant error introduced will generally be of order of 10 mV. A parallel switch (fig. 4) was selected in the present design since it offers the following advantages as compared with a serial switch: a small voltage Vb is rea~

(11) _y

R RI

R2

(12)

E q u a t i o n (12) yields the specification of Zo for a given maximum value of the error as:

Zo >

07)

Once the accuracy requirement is set, the permissible drift generators can be specified in the form

Y~

ER

Xm~

(9)

X V.,,~ =

Xm,~

--

E~ q- IuZ~ < (~M)m~.xXmax )

Correspondingly expressions for the time periods T', and T%_ and the output voltage Vo,t, taking into account finite gain, can be derived (Appendix A). T'~ =

Eu -I- I= Zl

A X

Zo

--v, -~

(16)

(13)

Another inherent source of error in the integrator is the drift caused mainly by temperature variations. Figure 3 illustrates the equivalent voltage and current offset generators 15]. It can be shown that the result-

Fig. 4. - - The switching circuit.

quired to drive the switch, the load on the source supplying Vu is constant, and the conduction resistance of the transistor switch is independent of Y, Symmetrical transistors [6] were considered for this application but unsymmetrical ones in their inverted connection were finally adopted because they introduce the lowest offset [6].

Annales de l'Association internationale pour le Calcul analogique

140 .

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The output of the multiplier, taking into account imperfections of the switches at low frequencies, is XY (Vout)~

-

-

K

(I -~ 2 8s)

09)

.

.

.

.

This inequality into account the at maximum for determined from may be obtained

2 R,,n

tq l h / ( t , + t._,)

=

2 R, R._,/(R~ q- R._,)

l<,.

-

-

~/R,,. R.r r

(21)

Fig. 5. ~ The delay of the switch. a) The output of the integrator. b) The waveform on the switch S:. the rise and fall times of the waveform (b) and T their sum, the average of the output of the amplifier A may be written as Y (T + A T ) - - 2 Y (T= + ATe) T-I-AT

(22)

K

[, - -

(K -~- - X =) AT 4ERCK

]

(23)

The absolute error has a maximtun value for X = K/'~/3. The maximm-n relative error 8T may thus be expressed as K" AT 3re = (24) 6 ERC~q X,,,,~.~ From (23) it follows that design efforts must be directed to keep AT as low as possible. The error can be limited to a certain m,~imum value 8~,m,,~ by choosing the maximum repetition frequency so that

/,,,.~ <

3 8 T,,,,.~ X .... KAT

Juillet 1962 .

is obtained from (1) and (24) taking fact that the repetition frequency is X equals zero. Since E and R are considerations outlined below, C,,~ in the form Ciaq

--

As a first step in the practical design of a multiplier, the signal range and the constants K, E, R had to be determined. With available transistor types it appears convenient to choose a signal range o.f ___10 volts. When the value of X covers this range, it is required that the ratio T ....../T.,i. should not exceed 3. This limitation is explained by the necessity of a moderate range of variation in the repetition frequency in order to make filtering feasible. Further there is the requirement that the smallest time interval be much longer than T (Paragraph 4). Altogether it seemed convenient to limit the maximum value of the ratio T1/T., to less than ten. According to equation (1) it is found that if a value of 12.5 volts is given to K, the above requirements are satisfied. The choice of E is a compromise between the requirement of a small error 8z (12) and hence a low value of E, and the necessity of a sufficiently high voltage range at the output of the integrator I. Since it was found convenient to design the bistable element (fig. 1) with a hysteresis of 4 volts, a value of 2 volts was chosen for E. The value of R was calculated with the aid of (18) and was found to be 125 K. Ron and Rorr were thereby evaluated on the basis of relationships and data given by Parks [6]. Experimental tests made by varying the value of R, have shown that the above choice resulted in minimum static errors. The basic constants so far derived, are summarised below. The maximum errors allowed, are also given. K =

By introducing the expressions for T~ and T~_ [equation (1)], it is fotmd that XY

- - -

.

5. Description of the Multiplier.

ve

V(o,,& -

.

2 E R f .....

Transistor switches are, further, limited in their speed of operation. The waveform at the output of the integrator and the corresponding waveform on the switch S.., are given in figure 5. If T~ and T., denote

(Vout) T =

.

(2o)

Ro,~ and R,,rr are the resistances of the transistor switch in the closed and open states, respectively. If Ro~ and Rorr are known, the values of the series resistors R~ and R._, (fig. 4) can be calculated with the aid of (B 5) R1 R.

RI + R..,

N" 3 .

K

as shown in Appendix B. 8.~ is given by the expression

a~ =

.

(25)

12.5V;

8z' 8,~ =

E =

10a/30°C;

2V; 8T =

R =

125K

2.10a~/30°C

Applying these values to inequality (13), the transfer impedance of the an~plifier is seen to be 16 megohms. The form of the amplifier is defined further by drift considerations. The above limitation on 8s, yields with the aid of (18) to the condition E~ -4- I,v 1 2 5 . 1 0 a < 10 mV This requirement can be satisfied neither with single ended transistors nor even with differential stages built of inexpensive transistors. Therefore a chopper stabilised differential amplifier of germanium transistors was adopted. The total drift of such an amplifier is approximately 100/,V which is negligible in the present application. The bandwidth requirements of the ampli* 8,r is allowed to be larger than the other errors since this makes it possible to increase the bandwidth.

A. Fuchs ." A solid state time-division multiplier fier are closely connected with the choice of the switching transistors. The latter represent the main limitation in speed of operation. Relatively low priced 2 N 582 transistors were chosen, yielding rise and fall times of 0.2 /,S and 0.4 btS. Substituting these values in (25), one arrives to a repetition frequency of order 8000 cps. The same value was adopted as a design target for the bandwidth of the amplifier. The circuit of the whole amplifier consisting of a two stage differential amplifier and a chopped amplifier, is given is figure 6. The design was based on an 2x2N269 2x2N393

2x2HIG26

6,BK

O--I0 V

~,7 I00~

T~ 2NI307

141

An additional error of 0.1.% was caused by temperature variations because of drift in the transistor switches.

7, Conclusion. A multiplier which in most respects equals the relative performance of similar valve multipliers has been described. It appears sufficiently accurate for most analogue computer applications. It should be possible to increase the bandwidth with the advent of high frequency, low price, switching transistors. Similarly temperature variations will be of less significance in the future.

8. Acknowledgement. Thanks are due to our colleagues in the Computer Group for helpful criticism. This work was carried out under the auspices of the Scientific Department, Israel Ministry of Defence.

tN 0

-•OUT

A,PPEcNDIX A. Equation (8) may be rewritten in the form

2NI306

q"lOV +lOV

47K

~K

,OK

OK I0~ lOOK

2.2KI39K ~ II~IF

i

l

~

~,1.0. 47.0. " IN461

.4.,

DI

+IOV 4x 2N404

+IOV

R

Vt

Zo,

Vo R

In the case considered

Vi

IOK

ooo/,.

I.l,oo

Vo

t = - - Z o co. In (:t + - - - - )

is very small and

Zo

therefore the approximation

t = -co.

_ '~C*'

V0 R

V0

R V((1

(a2)

- - . )

2 Vl Zo

is valid. Substitutin S Vo = - - 2 E ; Vt = k 4- x into this expression the fall time period TI~ is obtained as

OCh2

Wl

T,.. = T, 0 + - - - - )

IK

(A3)

2 Zo Ceq

Fig. 6. - - The operational amplifier. operational amplifier, recently described by one o{ the authors [7]. The integrator output is connected to the conventional bistable circuit, included in figure 7. The main part of the filter as given in the same figure 'is a capacitor C, connected as usual in integrators. In order to make filtering more efficient, a T network containing an inductance was used in the feedback network of the output amplifier.

A similar expression is easily derived for the fall time period T._,,.

,SK

,..K

"K

'~-00,~

,00,, i'~

6. Performance. Performance tests were carried out at two different maximurn repetition frequencies, namely 20 Kcps and 3 Kcps. Static accuracies of 0.4% and 0.3r% and zero offsets of 50 mV and :tO mV were measured in the faster and slower models respectively. Bandwidth was defined by the frequency at which the phase shift reached 2'0. The corresponding values measured in the two designs were 17 cps and 4.5 cps. The filter was adjusted so that the response to a step input does not overshoot by more than 20,% and the ripple be kept below 20 mV peak to peak.

(a:t)

IOV X K

125K lOOK

IOV

]

125K Y =~

IOOpF

p OlOK F ~

= Z70(pF

oO 5mH

Fig. 7. - - Diagram of the multiplier.

"~K

Annales de /'Association internationale pour /e CalcM analogique

142

The output of the multiplier takes the form Y (T~ + T.~)

(V°,,& =

T,,. +

T1

l+

Te

- -

- - - -

T, + To

Tt~ =

T'28

----

and the expression of the output to

2 (T~ + T,_,) Zo Co,

(, + .-7~ )

(B3)

K(l -- 82)--X

2 Z. Coq Ti e + Te e

l+

K

Juillet 1962

K (, - - 8,) + X 2 ERC

T1 + Te

Straightforward calculations yield after suitable approximations XY ER

(v°,, ,),. -

-

2ERC

T.,

(a4)

V

-

The time intervals T, and T., [equation (1)] are consequently modified to TI~ and Te,,

2 Y T.,,.

- -

N° 3

(a~)

(V,,,,,)~ =

Y (TI.~ + Te.~) - - 2 Y Te~ T ~ + T.,~

-- y

(B4)

2 X q- K (8= - - 8~) 2 X - - K (8,_, + 8,)

The error is minimum if 8t equals 8.2. In this case following (Bt), (B2) the condition APPENDIX B.

R, R.: The input circtfit of the integrator I is given in figure 8. The sum of R~ and R,_, must be chosen so that R,,° << (R, + R o) << R,,,.r

x--d,,

Fig. 8.

--

The input circuit of the integrator. V,,ut - -

W h e n the switch S, is closed (Ro,), a current li, flows into the input of the integrator. ".Ii.~ =

X

~- + X

K

K

R1 + Ro. + R1 R~o/Ro. (1

--

(m)

G)

where ROll

81=2

R, m/(R~ + R,,)

In the case the switch S, is open (R.n.), li,, takes the form X l,.e

where

--

K +

--

R

R

X

K

R

R

K --

R 1 -}- R,. -}- R, R,./R.,r (B2)

(, - ~ . , )

R, R,,/(R, + R,,) R,,rr

XY K

(1 +

8,)

(B6)

XY K

(1 q- 2 3B)

(B7)

REFERENCES

K

R

(BS)

Since the summing resistors used in the output amplifier are identical to those used in the integrator amplifier, the error introduced by the switch $2 is also (1 + 8). A good approximation of the output considering both errors is therefore

R2

RI

V K n Ro.

must be satisfied. Straightforward calculation yields V,,,,t --

-K

-

R~ + R._,

[1] E.A. GOLDBERG, <{A High Accuracy Time Division Multiplier >>, RCA Rev., vol. 13, Sept. 1952, pp. 265-274. [2] H. SCHMID, ~ Transistorised Four Quadrant Time Division Multiplier with an Accuracy of 0.1% )>, IRE Trans on El. Comp. EC-7, March 1958; pp. 41-47. [3] H. JAMES, G.S. EVANS, <{System Engineering in Theory and Practice)>, Brit. IRE, vol, 21, No. 1, Jan. 1961, pp. 41-48. [4] C.M. CUNDALL, J.K. SAGGERSON, G. SHAW, <~A Transistor D.C. Amplifier for Use in Analogue Computers ,~, Proc. lEE, Suppl. No. 18, vol. 106, May 1959; pp. 1354-!.364. [5] R.L. KONIGSBERG, ~, IRE Trans on El. Comp. EC,9, No. 3, Sept. 1960; pp. 352-358. [6] G.H. PARKS, <~Symetrical Transistors ~>, Brit. IRE, tot. 21, No. i, Jan. 1961; pp. 79-88. [7] A. FUCHS, <~A Solid State Oper.'ttlonal Amplifier ~>, to be published in the Proc. of the Int. Meeting on Analogue Computation Opatija 196l.