A static fault detection system for digital integrated circuits

Technical note

A static fault detection system for digital integrated circuits R Nagarajan, Tan Le Lay and Goh Mei Lin

A personal computer based static fault detection system for digital integrated circuits (IC) is described. The system detects functional as well as logical faults and declares a 'go/no go' condition for ICs. The process of developing a database containing test vectors and control vectors for testing various ICs is illustrated by examples. The system interface hardware is simple to implement and its Microsoft C based software is flexible to accommodate expansion of the database for new ICs. The application of the testing scheme can be extended to test digital circuits constructed on printed circuit boards. Keywords: fault detection, database, digital ICs

Many commercially available digital integrated circuit (IC) testers are designed to perform static (or functional) tests to ensure the 'go/no go' conditions of a selected, but large, range of ICs. These testers have a fixed database which cannot be extended to accommodate testing of newly emerging ICs. Their hardware is dedicated and built-in, and is inaccessible for external interface connections. The accessibility of tester hardware and the flexibility of databases extend the applications of conventional IC testers to testing digital circuits constructed on printed circuit boards. Another set of IC testers, on the other hand, have facilities for performing static as well as dynamic (or parameteric) tests on a few selected ICs and hence they are quite expensive. Efforts are being made to develop static testers which have the advantage of flexibility and cost effectiveness. Interesting earlier work on the design of an economical and flexible IC tester has been carried out by West et al. 1. This tester is based School of Industrial Technology, Universiti Sains Malaysia, Penang, Malaysia Paper received: 5 July 1993. Revised: 20 July 1994

on the Intel 8085 processor and is able to detect functional as well as logical faults (such as stuck at ONE and stuck at ZERO). This tester has a manual switch arrangement which has to be set every time an IC is tested, thus demanding a considerable amount of human interaction. Recent work of Whahab et al. 2"3 describes another testing scheme based on the Intel 8085 processor. This tester is capable of detecting possible short circuits between any two pins ('stuck pins') in addition to stuck at ZERO and stuck at ONE. The IC under test (ICUT) is tested by a set of carefully formed test sets. The database of the IC tester has many test sets each pertaining to a type number of the ICUT. An important feature of the test set of an ICUT is that it consists of scalar, vector and matrix data words. This feature enables the test system to easily locate the particular test set among many in the database, to identify input-output (I-O) pins and pins for power input (Vcc and GND) and to perform the complete test in order to verify the correct functioning of the ICUT. The test procedure, however, requires the pins for Vcc and GND to

be connected manually to a power supply, thus requiring some amount of interaction between the human operator and the test system. The set of ICs which cannot be tested by this scheme includes ()pen collectors and tristate logic. This paper presents a more automated scheme based on a personal computer (PC) which can manage a large size database, append test sets for new ICs, take fast decisions and allow programming in high level languages (such as C). The hardware and software are designed so that the test system can detect all logical faults and can test more varieties of small and medium scale ICs including several from the CMOS family. Operator interaction is reduced to a minimum in that all he or she has to do is to lock the IC in the ZlF base provided for the ICUT, and to key in the IC type number. The system performs the complete testing and declares a go/no go result on the PC screen.

INTERFACE HARDWARE The IC test system consists mainly of a PC (IBM compatible, XT, 80386 based), a PCL 720 DAS LAB card, a few Intel 8255 programmable peripheral interface (PPI) chips, a set of trisate buffers, a pair of reed relays and a ZlF base. A schematic diagram of the external hardware is shown in Figure 1. The PCL 720, a digital I-O card for the PC, provides 32 input and 32 output lines 4. These digital I-O lines

0141-9331/95/$09.50 © 1995 Elsevier Science B.V. All rights reserved Microprocessors and Microsystems Volume 19 Number 1 February 1995

57

A static fault detection system: R Nagarajan et al.

C>CSI ~> C S 2

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Figure 1

Hardware interface

are available at eight addressable ports which are brought out of the PC through four connectors. Since the test system proposed in this work is designed to test an IC which has a maximum of 24 pins, 24 input lines and 24 output lines of the PCL 720 card are utilized and the rest of the I-O lines are reserved for future expansion. The card has a group of DIP switches by which the base address of the ports can be set.

Power-ground

circuit

The tester is expected to test a wide range of ICs, some of which require high source currents. Since the PPIs

58

been made to identify the pin numbers of Vcc and GND in a large number of varieties of TTL and CMOS, SSI and MSI chips having eight to 24 pins ~. It was found that there are only nine pins of the ZlF base which can be the Vc~ and GND pins of any ICUT within these surveyed varieties. These pin numbers are presented ,~ Figure 3. It is assumed that an ICUT is locked in the ZIF base in such a way that pin 1 of the ICUT coincides with pin 1 of the base. The complexity of the tester circuit is, hence, much reduced by having nine PGCs connected to nine selected pins of the ZIF base. This requires only nine pairs of control lines and a single PPI (i.e. PPI 1 in Figure I) to control them. Of the remaining six lines of PPI 1, two are used to switch on/off either of two reed relays and the rest are reserved for future expansion. Figure 3 also shows how the ZlF base pins are connected to Z terminals of PGCs. Port A (PA) pins 0 and 1 of PPI 1 are the control lines of the PGC that is connected to ZIF base pin 4, and so on.

are not intended to provide high source currents 5, an external power source (the power-ground circuit, PGC) is used. The PGC is shown in Figure 2 and is able to provide a source current of 700 mA at a maximum voltage of 120V. This circuit is controlled by a two bit word on Line 1 (L1) and Line 2 (L2), as detailed in the table in Figure 2. Since the Vcc and GND pin-numbers of an ICUT are not known a priori, one can easily accept that each one of the 24 pins of the ICUT (or the pins of ZIF base) is to be connected to a PGC. This makes the tester circuit highly complex, involving 24 PGCs and two PPIs as each PGC requires two control lines from the PPI. A careful survey has

Microprocessors and Microsystems Volume 19 Number 1 February 1995

The hardware in Figure 1 has 24 tristate buffers (74LS241, all enabled) 6 which connect the ports of PPI 2 to all pins of the ZIF base. It is noted that the nine selected pins of the ZlF base are also connected to the set of PGCs. The data sent from PPI 2 through buffer lines which are connected to output pins of the ICUT are to be chosen so that they are inverted data of expected outputs. The reason for this will be explained through later examples. This portion of the hardware is responsible for data transfer between the ICUT and the PC, and is simpler when compared to the hardware of Reference 2, Figure 1 which involves 24 tristate buffers and two PPIs. The output response of the ICUT as well as its input data are sampled by another set of three 74LS241 buffers. The buffer handles 8 bit data and is controlled by a single control line. The (3 x 8) decoder 74LS138 gives the required control bits to the tristate buffers so that the 24 bit data from all IO pins is multiplexed and read by the PC. The chip select control signals (CS) to PPI 1 and PPI 2 are provided by the

A static

fault detection system: R Nagarajan et al.

POWER (P)

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ZIF basepin connectionsto PPI 1

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NA :Not Allowed

L I

L2

Z

I

0

Vcc

0

I

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0

0

HiZ

I

I

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HiZ: High Impedance

Figure2

Power-groundcircuit

decoder. The PC compares the measured I-O data from the ICUT with the expected (or correct) I-O data which is in the tester database and ensures the 'go/no go' condition of the ICUT. The tester is also required to test ICs from the CMOS family (4000 and 74C series). For testing CMOS digital ICs, Vcc has to be raised to a level between 3 to 15V. A set of two reed relays, operated by unused output lines of PPI 1, is provided to select a V~:c of either 5 V for TTL ICs or 12 V for CMOS ICs. Both 5 V and 12 V voltage supplies are available in the PCL 720 card and are brought out of the PC through its connectors.

DATABASE AND SOFTWARE DEVELOPMENT

know the function and pin numbers of the ICUT is able to perform testing. The main functions of the tester software are: •

searching for the required set of data (test set) pertaining to an ICUT from the entire database. A test set consists of test vectors and control vectors. • testing the ICUT with the help of a selected test set and ascertaining the pass/fail condition by comparing the measured I-O data with expected (correct) I-O data. Each test set in the database has to be carefully designed so that complete and exhaustive testing is performed on the ICUT.

Database development The tester software has to be flexible in order to append test sets, whenever needed, for any new ICUT. The software has also to be user friendly so that any operator who does not even

The database consists of test sets of many ICs. Each test set has two groups of vectors, viz. the control vectors and the test vectors.

The control vectors have information about the identification of various pins such as V~, GND, NC (no connection), I-O, clock and control pins. It also has information about the value of Vcc to be applied. The test vector has sets of carefully selected input and expected (or correct) output data patterns of the ICUT. The input data patterns include those of incompletely specified (don't care) terms. They are arranged in such a manner that all possible functional and logical faults can be detected. There is no standard procedure available in the literature for generating a test set 7. However, a specific procedure is proposed in this work for generating suitable test sets. A test set is required to test: •

the I-O functions of the ICUT thoroughly and exhaustively • the functions of control pins, if any • the functions of clock pins, if any. The control and test vectors from a test set are sent one by one to various pins of the ICUT and the responses of the ICUT are measured and verified for their correctness. The test vectors in the test set are to be arranged in such a manner that, during the entire testing, no two pins are given identical input data and also that no two output pins produce identical output data. In other words, the test vectors if arranged one below the other should not have columns having identical I-O data. To achieve this, a few additional (or redundant) test vectors may be included in the test set. This criterion

Microprocessors and Microsystems Volume 19 Number 1 February 1995

59

A static fault detection system: R Nagarajan et al. Table 1 Testset for Example 1: (a) input and expected (correct) output data words in bits and in hex; (b) data words sent from PPI 1 and PPI 2 a

Test number

1 1 E

2 2 D

3 3 O

4 4 E

5 5 D

6 6 O

7 7 G

18 8 O

19 9 D

20 10 E

21 11 O

22 12 D

23 13 E

24 14 V

ZIF base pin no. ICUT pin no. Pin function

1 2 3 4 5

1 1 0 0 0

1 0 0 1 0

1 0 1 0 0

0 1 1 0 0

1 1 0 0 1

0 1 0 1 0

0 0 0 0 0

1 0 1 0 1

0 1 1 0 1

0 0 1 1 0

1 0 0 1 1

0 1 1 1 0

0 0 0 1 0

1 1 1 1 1

E8 00 9C 00 30 00 44 00 08 00

49 25 75 1F 69

E: Enable input; D: Data input; O: Data output; G: GND; V: V,, Data bits of ZIF base pins 8 to 17 are at ZERO

PPI 1 (hex)

one or more identical columns. A quick observation of Table la reveals that column 1 and column 5 have identical data. Therefore, a possible stuck pin fault between pin 1 and pin 5 of the ICUT cannot be detected by test numbers 1 to 4. The same condition appears for pins 3 and 8, pins 2 and 11 and pins 4 and 9. The introduction of one or more redundant test vectors solves this problem. Test vector 5 is included for this purpose. Table lb indicates the data words (in hex) sent to the ICUT from PPI 1 and PPI 2. Since ZIF base pin numbers 24 and 7 (i.e. pins 14 and 7 of the ICUT) require Vcc and G N D potentials and Vcc is to be 5 V, PPI 1 has to send out data words as given in Table lb. PPI 2 gives its data words to the ZlF base in accordance with the data needed for testing the ICUT. A closer look at Table lb shows that the pin of PPI 2 connected to the output pin of a buffer in ICUT carries a data bit w h i c h

PPI 2 (hex)

Testnumber

PA

PB

PC

PA

PB

PC

1 2 3 4 5

04 04 04 04 04

08 08 08 08 08

20 20 20 20 20

C8 B8 34 44 08

00 00 00 00 00

49 25 35 57 69

is found to be successful in determining the functional faults as well as logical faults including stuck pins. The process of designing test and control vectors of the ICUT is illustrated by the following examples.

input (E) is high, the ICUT is enabled and the output follows the state of the input. Its output goes in to the Hi Z state when E is low. The ICUT is locked in the ZlF base so that their pins numbered 1 coincide. Since each tristate buffer of the ICUT has two inputs, four tests are sufficient for determining any functional fault. Referring to Table la, test numbers 1 to 4 can easily detect any functional faults. However, these test vectors, though staggered, produce

Example 1: Test set for the 74LS 126 The ICUT, 74LS126, is an enable-high quad tristate buffer. When the enable

Table 2 Testset for Example 2: (a) input and expected (correct) output data words in bits and in hex; (b) data words sent from PPI 1 and PPI 2 a

1 1

Test number 1 2 3 4 5 6 7 8 9 10

2 2

3 3

4 4

5 5

6 6

7 7

8 8

9 9

10 10

OE O0 Do Dt

O1 02

D2 D3 O3 G

0 0 0 0 0 0 0 0 1 I

0 1 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 1 I

1 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 1

0

I

0 1 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 I

0 0 0 0 0 0 0 0 0 0

15 11

16 12

LE 0 4

0 1

0 0 0 0 1 0 0 0 1 0

17 13

18 14

19 15

20 16

21 17

D4 Ds 05

06

D6 D7 0 7 V

ZlF base pin ICUT pin Pin function

0 0 0 0 1 0 0 0 1 1

0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 0 1 0 1 1

60 02 01 1 8 0 2 01 06 02 01 01 82 01 00 03 81 00 02 61 00 02 19 00 02 07 E6 01 99 A A 82 AB

0 0 0 0 0 1 0 0 0 0

OE: output enable; O: output bit; D: input bit; G: GND; V: V,~,; LE: latch enable Data bits of ZlF base pins 11 to 14 are at ZERO

60

Microprocessors and Microsystems Volume 19 Number 1 February 1995

0 0 0 0 0 1 0 0 0 1

22 18

0 0 0 0 0 0 0 1 0 0

23 19

0 0 0 0 0 0 0 1 0 1

24 20

1 1 1 1 1 1 1 1 1 1

A static fault detection system: R Nagarajan et al. Table 2b

PPI 2 (hex)

PPI 1 (hex) Test number

PA

PB

PC

PA

PB

PC

1 2 3 4 5 6 7 8 9 10

00 00 00 00 00 00 00 00 00 00

48 48 48 48 48 48 48 48 48 48

20 20 20 20 20 20 20 20 20 20

2C 54 4A 4D 4C 4C 4C 4C E6 AA

83 83 83 03 82 83 83 83 01 82

33 33 33 33 B3 53 2B 35 99 AB

Example 2: Test set for the 74LS373

in to the Hi Z state and any data forced onto the buffer output pin is available for measurement. The sets of input and expected (correct) output data words from all pins of the ZIF base for each test are

is the inverse of the expected (or correct) output data bit from the buffer when it is enabled. This process is helpful in detecting any open circuit at an output pin within the chip. When the buffer is disabled, its output goes

Table 3 a

given in Table la. These are stored in the database of the PC and are used for comparing them with the actual (measured) data words from the ICUT.

The ICUT, 74LS373, is a transparent latch with tristate outputs. It consists of eight latches for bus organized system applications. The flip-flop appears transparent to the data when the latch enable (LE) control is high. Data appears on the bus when output enable (OE) control goes low. When OE is high, the chip outputs are driven to the Hi Z state. The designed test set has to verify whether the output is actually driven to the Hi Z state when the chip is disabled. Table 2a details the test vectors which have two additional

Test set for Example 3: (a) input and expected (correct) output data words in bits and in hex; (b) data words sent from PPI I and PPI 2

1 1

2 2

3 3

4 4

5 5

6 6

7 7

8 8

17 9

18 10

19 11

20 12

21 13

22 14

23 15

24 16

Test number

Qs

Qt

Q0

Q2

Q6

Q7

Q3

Vss

Q8

Q4

Q9

Co

CE

Ck

R

Vdd

ZlF base pin ICUT pin Pin function

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 1 ! 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1

0 1 0 1 0 0 0 0 0 0 1 0 1 0 t 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0

1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 ] 1 ! l 1 1 1 1 1 1 1 1 1 1 1 1

2000 20 00 20 00 20 00 20 00 40 00 40 00 10 00 1000 02 00 02 00 00 00 00 00 80 00 80 00 08 00 08 00 04 00 04 00 00 00 00 00 00 00 00 00 20 00 20 00

13 1B 17 1B 11 15 11 15 11 15 1D 55 5D 05 0D 05 01 05 01 85 81 25 21 15 19

Q: output bit; Co: carry out; CE: clock enable; Ck: clock; R: reset Data bits of ZlF base pins 9 to 16 are kept at ZERO

Microprocessors and Microsystems Volume 19 Number 1 February 1995

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A static fault detection system: R Nagarajan et al. Table 3b

PPI1 (hex) Test number 1

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

18 19 20 21 22 23 24 25

PA

PB

PC

PA

PB

PC

01 01 01 01 01 01 01 01 01 01 01 01 01

08 08 08 08 08 08 08 08 08 08 08 08 08

10

10 10 10 10 10 10 10 10 10 10 10

DE DE DE DE DE BE BE EE EE FC FC FE FE

00 00 00 00 00 00 00 00 00 00 00 00 00

E3 EB E3 EB E1 E5 E1 E5 E1 E5 ED A5 AD

01 01 01

08 08 08

08 08 08 08 08 08 08 08 08

00 00 00 00

F5 FD F5

01 01 01 01 01 01 01 01 01

7E 7E F6 F6

FA FA FE FE FE FE DE DE

00 00 00 00 00 00 00 00

tests (Nos 9 and 10) exclusively for testing stuck pins and tristate logic. Table 2b provides the PPI data words.

Example 3: Test set for the MC14017B This example details how the clock input and inputs having incompletely specified terms are tested. The MC14017B is a CMOS five-stage Johnson decade counter with built in code converter 7. The ten decoded outputs are normally low and go high at their appropriate decimal time period. The output changes occur on the positive-going edge of the clock pulse. It has a CARRY OUT output useful for cascading. Table 3a provides I-O pin data and Table 3b gives data from PPIs. Test vectors are arranged in Table 3a so that even the stuck pin fault is detected without performing redundant tests. Even though the testing of various functions of the ICUT is spread

62

PPI 2 (hex)

10 10 10 10 10

10 10 10 10 10 10 10 10

F1 F5 F1 75 71 D5 D1 E5 E9

out in Table 3a, tests 1 to 4 specifically verify the function of RESET, tests 5 to 10 verify the CLOCK, tests 11 to 16 verify CLOCK ENABLE and the rest verify counter operation and the data from CARRY OUT.

Software development

Besides its main functions, as listed earlier, the tester software has two additional requirements, viz. to add test sets for new ICs and to read, modify or delete all or part of the test set belonging to an IC. The tester software is written in Microsoft C, which has libraries containing various builtin functions which include functions for accessing the operating system, formatted I-O, memory allocation and string manipulation. All of these functions are useful in the IC testing software. The data file stores the data of all ICs that can be tested by the testing system. Data are arranged in a struc-

Microprocessors and Microsystems Volume 19 Number 1 February 1995

tured form for conventional handling. All information necessary to identify and test an IC are gathered under a structure. They are: IC type number, number of test sets, number of IC pins, Vcc and GND pin numbers, control word (data from PPI 1) for PGC, data from PPI 2, and input and expected (correct) output patterns. Each IC has an array (record) of these structured data and all such records for various ICs are stored in the data file as the database of the test system. The position of a record in the data file is identified by its record number. There are two other files used to support the database. One is used to keep track of the total number of IC records. This information is needed when appending the data file. The other file stores all IC type numbers and their respective record numbers. CONCLUSION An IC testing scheme based on an IBM compatible PC has been illustrated. The method of developing test sets for a few ICUTs has been explained by examples. Test sets for other ICs can be generated in a similar manner. The scheme is useful in IC system design laboratories and manufacturing centres where quality assurance is a prime concern. The PGC is one of the main components in building the test hardware. The suggested hardware is made simpler by choosing selected pins of the ZlF base for connecting PGCs. An ideal hardware set-up should have PGCs connected to all pins of the ZIF base. To the authors' knowledge, a circuit which has the same function as the PGC is not available in IC form. If a PGC is produced as an IC chip, the tester hardware can be made less complex and more cost effective. If many ICUTs of the same type from a manufacturing line are to be tested, the entire test system can be further simplified and made more automated.

REFERENCES 1 West, G L, Nagle, H T and Nelson, V P 'A microcomputer controlled testing system for digital integrated circuits' IEEE Trans. Ind. Electr. Control Instrum. Vol. 27 (1980) pp 279-283

A static fault detection system: R N a g a r a j a n et al.

2 Wahab, A A, Nagarajan, R and Jerew D H 'A microprocessor based static tester for digital integrated circuits' Int. J. Electr. Vol 54 (1983) pp 913-920

3 Wahab, A A, Nagarajan, R and Jerew, D H 'A simpie IC tester using a database technique' Microprocessors Microsyst. Vol 10 (1986) pp 161-168 4 'Total solution for PC based industrial and laboratory automation- PCL 720 digital I-O and counter card' Advanteck Vol 21 (1991 ) pp 2-25 5 Microsystems Components Hand Book, Intel (1990)

6 Fast and LS TTL Data Book, Motorola Inc, USA (1980) 7 CMOS Logic Data Book, Motorola Inc, USA (1990) 8 Miller, M (Ed) Developments in Integrated Circuit Testing Academic Press, Sandiego (1987)

~ ~, ~~

Ramachandran Nagarajan received a BE (hons) in electrical engineering, an MTech. in control systems engineering and a PhD in adaptive control from the University of Madras (1961), l i t Kanpur (1969) and the University of Madras (I 977) respectively. He has worked in various teaching and research positions in India, Iraq and England. He is currently with the School of Industrial Technology, Universiti Sains Malaysia as a visiting Associate Professor and Chairman, Division of Quality Control & Instrumentation. His areas of interest include computer aided testing, adaptive control, robot path planning and expert systems.

Tan Le Lay obtained a BTech (hons) in quality control and instrumentation from the School of Industrial Technology, University of Sains Malaysia in 1993. He is now working as a quality and reliability engineer in Intel Technology, Penang. His research area includes the design of electronic and microprocessor based systems.

......

Marilyn Goh Mei Lin obtained her bachelor degree in quality control and instrumentation from the School of Industrial Technology, Universiti Sains Malaysia, in 1993. Presently, she is working as an in-line quality control engineer at AMD, Penang. Her area of research interest includes circuit board testing and device failure analysis.

M i c r o p r o c e s s o r s and M i c r o s y s t e m s V o l u m e 19 N u m b e r 1 F e b r u a r y 1995

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