A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Current Applied Physics 12 (2012) 1503e1509

Contents lists available at SciVerse ScienceDirect

Current Applied Physics journal homepage: www.elsevier.com/locate/cap

A study on the performance of metal-oxide-semiconductor-field-effecttransistors with asymmetric junction doping structure Hyunho Park, Byoungdeog Choi* School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746, Republic of Korea

a r t i c l e i n f o

a b s t r a c t

Article history: Received 26 March 2012 Accepted 18 April 2012 Available online 26 April 2012

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric sourceedrain junction transistor was successfully extracted by using the split CeV technique. Crown Copyright Ó 2012 Published by Elsevier B.V. All rights reserved.

Keywords: Diode Junction doping Band-to-band tunneling GIDL Channel doping

1. Introduction Complementary metal-oxide semiconductor (CMOS) scaling has been the primary tool for improving the performance of deepsubmicron bulk CMOS used in very large-scale integration (VLSI) systems [1]. However, band-to-band tunneling (BTBT) presents a scaling limit to future CMOS devices [2], which has a heavily doped pn junction exists between the drain of the transistor and the substrate [3]. When very heavy doping (for example the halo) in the area of the source or drain is used to suppress short-channel effects, the band-to-band tunneling (BTBT) problem is aggravated [4,5]. Tunneling leakage in the heavily doped junction increases power dissipation in the bulk metal-oxide-semiconductor fieldeffect-transistors (MOSFETs). Moreover, it can cause unwanted threshold voltage shifts in the partially depleted silicon-oninsulator SOI case, which lead to additional sub-threshold drainto-source leakage [6]. In a deep-submicron MOSFET channel, the junction doping concentration increases and the junction profile becomes more abrupt, inducing a higher electric field in the devices [7e9]. In order to analyze the characteristics of the current in a MOSFET accurately, the basic diode junction current should be first understood and evaluated. The gate-induced-drain leakage (GIDL) current, induced by the high electric field between the gate and drain, has become a major leakage current component in

* Corresponding author. Tel.: þ82 31 299 4589; fax: þ82 31 290 4971. E-mail address: [email protected] (B. Choi).

MOSFETs [10]. The classical theory of GIDL current generation has been applied to high drain-to-gate biases [11]. Ultra short-channel transistors require lower power supply levels to reduce their internal electric fields and power consumption. The requirement of lower power forces a reduction in the threshold voltage, which in turn substantially increases the off leakage current. This increase of the off leakage current is due to the weak inversion state leakage and is a function of the threshold voltage [9]. The key challenge in scaling MOSFET is finding a way to maintain good short channel performance without sacrificing the drive current [12]. To reduce threshold, voltage (Vth) roll-off characteristics and drain induced barrier lowering (DIBL), channel doping should be increased [13]. In order to suppress short-channel effects and reduce the junction leakage, an asymmetric junction profile transistor with a deep doped source junction was proposed [14]. We studied the diode current characteristics in the pn junctions of the source/drain to the substrate according to the level of doping of MOSFETs. The GIDL current was analyzed for short channel MOSFETs with junction doping dependence. And the body bias effect for the GIDL current in the asymmetric source/drain junction transistor was studied in terms of the BTBT of electrons in the reverse biased channel to the drain pn junction. An accurate and comprehensive failure analysis is important to acquire useful information that can be used to achieve excellent transistor performance and high yield. The doping profiles calculated by capacitanceevoltage (CeV) measurements work well for large-area devices and lightly-doped devices, but they are not very suitable for heavily doped devices [15]. And MOSFET gate has an

1567-1739/$ e see front matter Crown Copyright Ó 2012 Published by Elsevier B.V. All rights reserved. doi:10.1016/j.cap.2012.04.026

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509

2. Experimental N-type MOSFETs (NMOS) were fabricated by state-of-the art 40 nm CMOS technology to have gate oxide thickness of less than 10 nm. The channel length was 150 nm, and the width of the transistor was 1.5 mm. Channel doping of various levels was implemented for low, medium and high threshold voltages (Vth). These conditions corresponded to doping levels of 5  1012, 6.5  1012, 8.0  1012 cm-2, respectively. The measured transistor had an asymmetric source/drain junction structure. To make an asymmetric junction structure, conventional diffused junction ion implantation (4  1014 cm-2), halo doping (5  1013 cm-2), and lightly-doped drain (LDD, 3  1013 cm-2) ion implantation were done in the source junction, and only LDD and halo without the deep diffused ion were implanted in the drain junction. To analyze the channel doping dependence for electrical performance, two boron (B) implantations were carried out to doping levels of 5  1012 and 6.5  1012 cm-2, respectively. A precision semiconductor parametric analyzer (Agilent 4156C) applied terminal voltages on the MOSFETs while sensing the corresponding terminal currents. CeV was measured with the Agilent 4294A precision impedance analyzer. 3. Results and discussion

10

0

10

-2

10

-4

10

-6

10

-8

10

-10

10

-12

10

-14

10

-16

0.0

Low Doping Junction High Doping Junction

0.2

(1)

where I0 (I0,scr or I0,qnr) is the saturation current and n is the diode ideality factor. When current flows through the device, diode terminal voltage, consisting of the diode voltage (V) and an ideal diode series resistance (rs), is generated. Eq. (1) shows that the pn junction diode current has two current components, the spacecharge region (scr) current and recombination/generation and quasi-neutral region (qnr) current [23]. Fig. 1(a) shows the pn junction diode current for the low doping junction, which is the source of the transistor, and that for the high doping junction,

0.4

0.6

0.8

1.0

Voltage [V]

b

-2

10

ΔV1

-3

10

ΔV2

-4

10

-5

10

-6

10

Low Doping Junction High Doping Junction

-7

10

0.6

0.7

0.8 0.9 Voltage [V]

1.0

Fig. 1. (a) Forward diode current versus voltage for low and high doping levels with series resistance. (b) Series resistance for two doping conditions.

which is the drain of the transistor. The linearity of curve in Fig. 1(b) at the high current region is expressed as DV ¼ Irs, where rs is calculated as rs ¼ DV/I. The series resistance for each doping case from Fig. 1 was 32 U for the high doping junction and 750 U for the low doping junction. Assuming I[I0, Eq. (1) can be written as

I½dV=dI ¼ Irs þ nKT=q

The current of a pn junction is often written as a function of the diode voltage, V as

   



qðV Irs Þ qðV Irs Þ 1 þIo;qnr exp 1 I ¼Io;scr exp nscr kT nqnr kT

a

Current [A]

additional limitation. The small gate area has very small capacitances that are difficult to measure, making CeV based techniques difficult or impossible to implement. Therefore, it is very difficult to obtain doping profiles because of rapid scaling of devices [16]. We tried to obtain the doping profile for an asymmetric source/drain junction MOSFET with a short gate length and ultra thin oxide thickness by electrical measurements. The doping profile was compared with the simulation results. Effective mobility needs to be analyzed to evaluate current degradation in a reliability problem. Effective mobility (meff) is sensitive to the definitions and values of effective channel length (Leff) and source/drain resistance (RSD) [17]. The significant mobility degradation in very short channel devices causes errors in linear current measurement techniques. Device performance is believed to be ultimately limited by the carrier injection velocity from the source to the channel [18]. A few papers reported the relationship between low-field mobility and high-field carrier velocity [19,20]. Mobile channel charge density measurement is known as the split CeV technique [21,22], which was originally proposed to measure the interface trap density but was later adapted for measurements of effective mobility. We successfully extracted the effective mobility of the short channel MOSFETs with asymmetric source/ drain junction transistor by using the split CeV technique.

Current [A]

1504

(2)

Fig. 2 shows I[dV/dI] vers us I plot for each junction doping case. The slopes (rs) can be extracted from the curves. There was no difference in the results between the slope method and the derivations from Fig. 1. Diode current increased as the temperature increased. The series resistance of the diode induced current saturation, as shown in Fig. 3. CeV characteristics are shown in Fig. 4(a) and (b) for each doping level according to temperature. The capacitance of the diode increased as the temperature increased due to the BTBT current [24]. However, there was no significant difference in the doping levels at the same temperature, as shown in Fig. 4(c). From these diode current characteristics, we tried to analyze the effects of doping dependence on the gate-induceddrain leakage (GIDL) current of 4-terminal (gate, source, drain and body) MOSFETs. BTBT is only possible in the presence of a high electric field and when band bending is larger than the energy band gap [25,26]. The electric field at the SieSiO2 interface also depends

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509

0.14

1505

-4

10

high doping junction low doping junction

0.12 Rs= 754 Ω

0.08

nKT/q = 0.048, n = 1.85

0.06

Rs= 39 Ω

-8

10

300K 350K 400K

-10

0.04 0.02

Current [A]

I[dV/dI]

-6

10

0.10

10

nKT/q = 0.030, n = 1.17

0.0

1.0x10

-3

2.0x10

-3

-12

10

Junction Current [A]

0.0

0.2

0.4

0.6

0.8

1.0

Voltage [V] Fig. 2. Typical I[dV/dI] versus current experimental plot of Eq. (2). Fig. 3. Diode current at high doping condition according to temperature.

on the doping concentration in the diffusion region and the difference between the drain voltage, VDS, and the gate voltage, VGS [27]. Leakage components were extracted by DC measurements, as shown in Fig. 5(a). Pure junction leakage (JLKG) is the reverse diode current between the source/drain junction and the substrate. Subthreshold current was measured by sweeping VGS and VDS with the connecting gate and drain SMUs. The GIDL current was measured by sweeping drain (VDS ¼ 0e3V) when gate was 0 V, and source and body was grounded. The reverse diode current was not a significant component of the transistor leakage current due to the low electric field at the junction. The major leakage component was the subthreshold leakage due to the enlarging depletion region at the drain junction. Fig. 5(b) shows that the reverse diode leakage in the

b 300K 325K 350K

2.4

2.8 300K 325K 350K

2.6

2.2 2.0 1.8

2.4 2.2 2.0 1.8 1.6

1.6 0.0

(3)

The tunneling current is a function of the electric field [28], which can be expressed as a function of the doping concentration (N) at

2.8 2.6

Capacitance [pF]

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2qNðVAPP þ V0 Þ : EJ ¼ εSi

Capacitance [pF]

a

MOSFETs had negligible dependence on the doping level. When high voltage was applied to the drain with the gate grounded, a deep-depletion region was formed under the gate-to-drain overlap region. Electron-hole pairs were generated when the valence band electrons tunneled into the conduction band to be collected by the drain and substrate, separately. The maximum electric field (EJ) can be expressed as

0.2

0.4

0.6

0.8

0.0

1.0

0.2

c

0.4

0.6

0.8

1.0

Reverse Bias [V]

Reverse Bias [V] 2.6

Low Doping Junction High Doping Junction

Capacitance [pF]

2.4 2.2 2.0 1.8 @300K

1.6 0.0

0.2

0.4

0.6

0.8

1.0

Reverse Bias [V] Fig. 4. CeV characteristics for (a) low doping profile, (b) high doping profile, and (c) unified plots of (a) and (b) at room temperature.

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509

1E-6

1E-8

a

All currents GIDL + JLKG pure JLKG Subthreshold current

1E-10

1E-12

1E-14 0.0

0.5

1.0

1.5

2.0

2.5

3.0

10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10 -15 10 -1.0

Low Ch. Doping High Ch. Doping -0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Gate to Source Voltage, VGS [V]

Drain Voltage, VDS [V]

b

-2

Drain Current, IDS [A]

a Drain Current, IDS [A]

1506

b

1E-11

-14.0

0.5

Log(IDS/N )

-16.0 1E-12

1E-13

high doping junction low doping junction 1E-14 0.0

-18.0

Slope=-5.85

-19.0

-21.0 -22.0 0.2

0.5

1.0

1.5

2.0

0.4

0.6

2.5

0.8

1/N

Drain Voltage, VDS [V] Fig. 5. (a) Leakage current components extracted from 4-terminal MOSFET DC measurements. (b) Pure junction leakage (JLKG) currents of low and high doping junction profiles.

the dominant tunneling point. Therefore, the BTBT current can be simplified as


 pffiffiffiffi B JBB ¼ A N exp pffiffiffiffi N

-17.0

-20.0

(4)

where A and B are constants determined by the fabrication process and materials. Channel doping concentration is the only variable of tunneling current. Fig. 6(a) shows the GIDL current according to channel doping concentration. The GIDL current of the high doping case is 2 orders higher than that of the low doping case. Eq. (4) shows the relationship between log (IDS/N0.5) and 1/N0.5. Fig. 6 (b) shows that the GIDL current increases with the increase of channel doping concentration at the gate voltage, VGS ¼ 0.5 V, so a linear fitting equation with a slope of 5.85 was obtained. Therefore, the linear relationship between the GIDL current and channel doping concentration was in good agreement with the BTBT, Eq. (3). Fig. 7 shows the drain current curves for low and high drain junction cases, respectively. For the high drain junction case, the subthreshold current was higher than that of the low drain case and the GIDL current was increased. The drain current of the high drain case at high gate-to-drain voltage was more affected by the avalanche impact ionization, and the GIDL current was significantly enhanced due to higher junction doping. Therefore, the low drain junction structure can be a good structure for MOSFETs to achieve reduced GIDL current. Fig. 8(a) shows the drain current versus the gate voltage curve of NMOS with high Vth channel and the deep

1.0

1.2

0.5

Fig. 6. (a) Drain current curves for different channel doping concentrations (normal and high Vth) (b) plot of log (IDS/N0.5) versus 1/N0.5.

drain junction for different body bias voltages. For the low drain junction case, the GIDL current could not be extracted because it was at the level of the noise current. As the body bias increased, the drain surface fully depleted, and the holes generated in the drain surface were swept away by the applied body bias. The GIDL current increased with increase of the drain-to-body bias and also flowed through the channel to the drain junction. From Eq. (3), the tunneling current was determined by the drain-to-gate bias -2

Drain Current, IDS [A]

Drain Current, IDS [A]

-15.0

10 -3 10 -4 10 -5 10 -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10 -15 10 -0.5

Shallow Drain Junction Deep Drain Junction

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Gate to Source Voltage, VGS [V] Fig. 7. Drain current versus gate voltage curves for the low doped drain junction and the high doped drain junction by change terminals of source and drain on the same NMOS.

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509 20

10

-7

10

Drain Current, IDS [A]

VBS=0V VBS=-0.5V VBS=-1.0V

-8

10

-9

10

-10

10

-0.5

0.0

Simulation : A 2-D device simulation

18

10

(Taurus-Medici by Synopsis Inc.)

17

10

16

10

15

10

14

0.0

0.1

0.2

0.3

0.4

Depth [um]

1

-1.6x10

Fig. 10. Doping profiles of n-channel MOSFET by the threshold voltage method, simulation and SIMS profile.

1

-1.8x10

0.5

ln[ID/(|VDG|(VDG+Vbi) )]

19

10

10

0.5

Gate to Source Voltage, VGS [V]

b

Vth method SIMS Simulation

-3

Doping Concentration [cm ]

a

1507

1

-2.0x10

1

-2.2x10

1

-2.4x10

1

-2.6x10

1

-2.8x10

0.4

Vb=0V Vb=-0.5V Vb=-1.0V

0.5

0.6

0.7

0.8

0.9

1.0

0.5

1/(|VDG|+Vbi)

Fig. 8. (a) Leakage current curves of high doping NMOS for various body bias voltages (b) the measured plot of ln[IDS/jVDSj(VDSþVbi)0.5] versus 1/(jVDGjþV0)0.5.

because the drain voltage (VDS) is equal to the drain-to-body bias. The theory of tunneling current predicts [29]


B IDS ¼ AEs exp  Es

(5)

where Es is the vertical electric field at the silicon surface, and A and B are constants. Fig. 8(b) shows the measured ln[IDS/jVDSj(VDSþVbi)0.5] versus 1/(jVDGjþV0)0.5, which is derived from Eqs. (3)e(5). The GIDL current increased as the drain voltage increased. However, when the body bias was increased, the increase of the GIDL current was smaller

than that of the lower drain voltage case. Therefore, the body bias directly modulated the band bending in the drain junction and the magnitude of the GIDL current. The total field in the junction is a vector sum of the electric fields of all directions in a transistor, so increasing the drain voltage would result in an overall stronger total field but the difference of the GIDL current is reduced due to the body bias voltage. Fig. 9 shows the drain current (IDS) versus gate voltage (VGS) transfer curve of an n-channel MOSFET with a shallow junction drain and a normal junction source. We identified some major transistor characteristics at room temperature. The threshold voltage (Vth) by the gm (transconductance) max extraction method was 672 mV and the threshold drain current method Vth (gate voltage for drain current 1 nA) was 260 mV [30]. Transconductance (gm) was also shown in linear scale and the maximum transconductance (gm_max) was 4.4  105 S. We applied the threshold voltage method to extract the channel doping profile which is measured as a function of the substrate bias [31]. We measured body bias effect (BBE) for extracting a threshold voltage shift by using the unit gate voltage. The threshold voltage, when the gate voltage is measured from the gate to the source, is given by

VT ¼ VFB þ 2fF þ

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2qKs ε0 NA ð2fF  VBS Þ : Cox

(6)

The threshold voltage changed by about 316 mV as the substrate voltage changed by (VBS) 1 V. The doping profile was obtained by

-4

5.0x10

-4

4.0x10

-4

3.0x10

-4

2.0x10 Drain Current Transconductance

-4

1.0x10 0.0

1.5

2.0

2.5

Transconductance, Gm [S]

Drain Current, IDS [A]

-1

10 -2 10 VDS = 0.05 / 3.0V -3 10 VB = 0V -4 10 VS = GND -5 10 Room temp. -6 10 -7 10 -8 10 -9 10 -10 10 -11 10 -12 10 -13 10 -14 10 -15 10 -0.5 0.0 0.5 1.0

3.0

Gate Voltage, VGS [V] Fig. 9. IDSeVg curves and transconductance (gm) for NMOS transistor (VDS ¼ 0.05 and 3.0 V, W/L ¼ 1.5 mm/150 nm, VDS ¼ 0.05/3.0 V, VS ¼ ground, and VBS ¼ 0 V).

Fig. 11. Effective and field-effect mobilities versus gate voltage curve extracted by drain conductance calculation.

1508

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509

ueff ¼

gd L WQn

(10)

The drain conductance (gd) is defined as

gd ¼

vIDS  ; vVDS VGS ¼const

(11)

and the mobile channel charge density is approximated by

Qn ¼ Cox ðVGS  VT Þ:

Fig. 12. Effective mobilities with various channel doping conditions extracted from split CeV method as a function of effective electric field with universal mobility curve (channel dose A: 2.5E12, B: 6.5E12 and C: 9.5E12 cm2).

plotting the threshold voltage against (2FFVBS)1/2 and determining the slope m ¼ DVth/D(2FFVBS)1/2 of this plot. Iterations of calculating were carried out to extract 2FF by using the threshold voltages as a function of (2FFVBS)1/2 and we could obtain a slope, m. The doping concentration is calculated as [32]

  2 m2 Cox NA W ¼ ; 2qKs ε0

(7)

and the profile depth is

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Ks ε0 ð2fF  VBS Þ : W ¼ qNA

(8)

We used an initial value j2FFj ¼ 0.6 V, took the slope of the Vth versus (2FFVBS)1/2 plot, and found a new NA. With the values of NA, we could calculate a new FF and plot the Vth versus (2FFVBS)1/2 curve, and this process was repeated. A two-dimensional device simulation (TauruseMedici of Synopsis) was done with the same doping concentrations, channel implants, and gate oxide thickness to compare the accuracy of the doping profile extracted by the threshold voltage method [33]. The results were in good agreement with the simulation results, as shown in Fig. 10. SIMS profile data was also compared with results of Vth method and simulation. SIMS data was relatively different compared to other method. It was considered that the SIMS sample didn’t have exact dopant diffusion and heat budget of real chip device, however Vth method was done on real transistor test element group (TEG) and exactly showed all dopant behavior with process integration and heat. Therefore, Vth method could be an excellent candidate method for evaluating and analyzing of short channel MOSFET device in wafer level transistor characterization. The drain current is a combination of drift and diffusion currents as

ID ¼

Wueff Qn VDS kT dQn  Wueff ; L q dx

(9)

where Qn is the mobile channel charge density (C/cm2). Effective mobility (meff) is usually measured at drain voltages of typically 50e100 mV. A lower VDS is better, because the channel charge would be more uniform from source to drain [32]. Solving for the effective mobility (meff) gives

(12)

We could solve for meff, and obtain a relation between the gate voltages versus meff from drain voltage versus drain current curves. And field-effect mobility (mFE ¼ Lgm/WCoxVDS) also extracted from VDSeIDS curves, as shown Fig. 11. But the calculated effective mobilities were smaller than the expected value. This smaller value is due to the mobile charge density approximation error. In other words, first, a channel charge exists in the sub-threshold region but VGSeVth ensures device operation above Vth (drift-limited regime); second, the gate oxide capacitance (Cox) is not the effective oxide capacitance; and third, an inversion layer resides slightly below the SiO2/Si interface. Exact effective mobility can be obtained by applying the direct measurement of Qn from CGC measurement [32]. The mobile channel charge density measurement technique is known as the “split CeV” technique, measuring the capacitances between the gate and sourceedrain and between the gate and the substrate [21,22]. When the channel of a MOSFET is in on-state conduction, the electron flow has a non-uniform distribution along the channel and the electron mobility varies with depth [33]. The effective mobility depends on lattice scattering, ionized impurity scattering, and surface scattering. Previous studies have shown that effective mobility has a universal behavior independent of substrate bias, oxide thickness and NA. The majority of the electrons in the inversion layer are subject to an effective electric field (Eeff) [34]. The gate bias voltage (VGS), on which a small AC signal is superposed, is varied from the accumulation to the inversion regime. This total gate signal induces a small signal current flowing as the sourceedrain current (ISD) and the substrate current (IBS), which can be separately monitored. We measured the inversion charge using the normal split CeV setup. The gate-to-channel capacitance (CGC) is measured using the connection between the gate and the sourceedrain connected together via the substrate grounded. The mobile channel charge density (Qn) was be derived as

ZVGS Qn ¼

CGC dVGS :

(13)

N

Similarly, the bulk charge density (Qb) was derived using the gate-to-substrate capacitance (CGB). The effective electric field can be expressed as

Eeff ¼

Qb þ hQn : Kn ε0

(14)

The value of the parameter h is usually taken as 1/2 for electron mobility [35]. Fig. 12 shows the effective mobility versus effective electric field curve of an NMOS transistor with various channel doping conditions characterized by an universal mobility curve [36]. The effective mobility was 203 cm2 V1s1 at the operating electric field (Eeff ¼ 0.86 MV/cm). 4. Conclusions The diode currents of MOSFET junctions according to doping level were characterized in detail. The observed current of the

H. Park, B. Choi / Current Applied Physics 12 (2012) 1503e1509

quasi-neutral region of the high doping junction was lower than that of the low doping case because of the series resistance. As temperature increased, the diode current increased but the slope of the space-charge region decreased due to lattice scattering. The series resistance (rs) was extracted from the currentevoltage curves for different junction doping concentrations. GIDL current characteristics were analyzed and discussed for MOSFETs with an asymmetric source/drain junction structure according to channel and junction doping levels. Body bias and lateral electric field on the GIDL current contributed to the total electric field in the channelto-drain junction and enhanced the GIDL current. By the threshold voltage measurement, we successfully extracted the channel doping profile of a very short channel MOSFET device with a shallow doped drain junction and found that the result was in good agreement with the simulation result. Also we successfully obtained the effective mobility from the split CeV method for short channel MOSFET with asymmetric junction structure. This transistor can be applied for a more in-depth reliability analysis of various hot carrier injection cases.

[12]

[13]

[14]

[15]

[16]

[17] [18] [19]

[20]

Acknowledgment [21]

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2009-0083540) References [1] Y. Taur, C.H. Wann, D.J. Frank, 25 nm CMOS design considerations, IEDM Tech. Dig. (1998) 789e792. [2] G.G. Shahidi, SOI technology for the GHz era, IBM J. Res. Dev. 46 (2002) 121e131. [3] P.M. Solomon, J. Jopling, D.J. Frank, C. D’Emic, W.E. Haensch, Universal tunneling behavior in technologically relevant P/N junction diodes, J. Appl. Phys. 95 (2004) 5800. [4] Y. Taur, E.J. Nowak, CMOS devices below 0.1 mm: how high will performance go? IEDM Tech. Dig. (1997) 215e218. [5] B. Yu, C.H.J. Wann, E.D. Nowak, K. Noda, C. Hu, Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET’s, IEEE Trans. Electron Devices 44 (1997) 627e634. [6] M. Horiuchi, K. Ohoyu, Reduction of PN junction leakage current by using poly-Si interlayered SOI wafers, IEEE Trans. Electron Devices 42 (1995) 876e882. [7] T. Chen, T.Y. Chan, I.C. Chen, P.K. Ko, C. Hu, Subbreakdown drain leakage current in MOSFET, IEEE Electron Device Lett. 8 (1987) 515e517. [8] S. Geissler, B. Porth, J. Lasky, J. Johnson, S. Voldman, A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices, IEDM Tech. Dig. (1991) 839e842. [9] W.R. Tonti, W.P. Noble, W.W. Abadeer, S.W. Mitti, W.E. Haensch, Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors, Proc. IRPS Tech. Dig. (1991) 306e309. [10] Y.K. Choi, D. Ha, T.J. King, J. Bokor, Investigation of gate-induced drain leakage (gidl) current in thin body devices: single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs, Jpn. J. Appl. Phys. 42 (2003) 2073e2076. [11] X. Yuan, J.E. Park, J. Wang, E. Zhao, D. Ahlgren, T. Hook, J. Yuan, V. Chan, H. Shang, C.H. Liang, R. Lindsay, S. Park, H. Choo, Gate-induced-drain-leakage

[22] [23] [24]

[25] [26] [27] [28] [29] [30]

[31] [32]

[33]

[34] [35]

[36]

1509

current in 45-nm CMOS technology, IEEE Trans. Device Mater. Reliability 8 (2008) 501e508. B. Agrawal, V.K. De, J.D. Meindl, Device parameter optimization for reduced short channel effects in retrograde doping MOSFET’s, IEEE Trans. Electron Devices 43 (1994) 365e368. X. Chen, Q.C. Ouyang, G. Wang, S.K. Banerjee, Improved hot-carrier and shortchannel performance in vertical nMOSFETs with graded channel doping, IEEE Trans. Electron Devices 49 (2002) 1962e1968. S.J. Ahn, G.T. Jung, C.H. Cho, S.H. Shin, J.Y. Lee, J.G. Lee, H.S. Jeong, K.N. Kim, Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics, VLSI Tech. Dig. (2002) 176e177. G.J.L. Ouwerling, Physical parameter extraction by inverse device modelling: application to one- and two-dimensional doping profiling, Solid-State Electron. 33 (1990) 757e771. G.P. Carver, Influence of short-channel effects on dopant profiles obtained from the DC MOSFET profile method, IEEE Trans. Electron Devices 30 (1983) 948e954. J.R. Schrieffer, Effective carrier mobility in surface-space charge layer, Phys. Rev. 97 (1955) 641e646. M. Lundstrom, Z. Ren, Essential physics of carrier transport in nanoscale MOSFETs, IEEE Trans. Electron Devices 49 (2002) 133. A. Lochtefeld, D.A. Antoniadis, Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress, IEEE Trans. Electron Devices 22 (2001) 591e593. M. Saitoh, N. Yasutake, Y. Nakabayashi, K. Uchida, T. Numata, Understanding of strain effects on high-field carrier velocity in (100) and (110) CMOSFETs under quasi-ballistic transport, IEDM Tech. Dig. (2009) 1e4. J. Koomen, Investigation of the MOST channel conductance in weak inversion, Solid-State Electron. 16 (1973) 801e810. C.G. Sodini, T.W. Ekstedt, J.L. Moll, Charge accumulation and mobility in thin dielectric MOS transistors, Solid-State Electron. 25 (1982) 833e841. D.K. Schroder, Semiconductor Material and Device Characterization, second ed. Wiley, New York, 1998. A. Aziz, F. Raoult, O. Bonnaud, Electrical conduction phenomena versus temperature in a lateral polysilicon pn junction: analysis and modeling, Mater. Chem. Phys. 32 (1992) 368e373. A. Schenk, J. Appl. Phys. 71 (1992) 3339. G. Vincent, A. Chantre, D. Bois, Electric field effect on the thermal emission of traps in semiconductor junctions, J. Appl. Phys. 50 (1979) 5484e5487. T.Y. Chan, J. Chen, P.K. Ko, C. Hu, The impact of gate-induced drain leakage current on MOSFET scaling, IEDM Tech. Dig. (1987) 718e721. G.A.M. Hurkx, On the modelling of tunnelling currents in reverse-biased p-n junctions, Solid-State Electron. 32 (1989) 665e668. Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, Cambridge Univ. Press, New York, 1998. H.G. Lee, S.Y. Oh, G. Fuller, A simple and accurate method to measure the threshold voltage of an enhancement-mode MOSFET, IEEE Trans. Electron Devices 29 (1982) 346e348. D.W. Feldbaumer, D.K. Schroder, MOSFET doping profiling, IEEE Trans. Electron Devices 38 (1991) 135e140. H. Park, K. Lee, D. Baek, J. Kang, B. So, S. Kwon, B. Choi, Electrical extraction of one dimensional doping profile and effective mobility for metal-oxidesemiconductor field-effect transistor, Jpn. J. Appl. Phys. 50 (2011) 01AA01. M.G.L. van den Heuvel, R.J.E. Hueting, E.A. Hijzen, M.A.A. t Zandt, Improved method for determining inversion layer mobility of electrons in trench MOSFETs, IEE Proc. Circuits Devices Syst. 151 (2004) 225e230. A.G. Sabnis, J.T. Clemens, Characterization of the electron mobility in the inverted <100> Si surface, IEDM Tech. Dig. (1979) 18e21. S.C. Sun, J.D. Plummer, Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces, IEEE Trans. Electron Devices 27 (1980) 1497e1508. S. Takagi, On the universality of inversion layer mobility in Si MOSFET’s: part II-effects of surface orientation, IEEE Trans. Electron Devices 41 (1994) 2363e2368.