- Email: [email protected]
A technique for modelling p-n junction depletion capacitance of multiple doping regions in integrated circuits
Solid-Stare Elecnonics Vol. 29, No. 8, pp. 113-777, Printed in Great Britain
1986
0038-llOU86 $3.00 + 0.00 Pqamon loumals Ltd
A TECHNIQUE FOR MODELLING p-n JUNCTION DEPLETION CAPACITANCE OF MULTIPLE DOPING REGIONS IN INTEGRATED CIRCUITS RAYMONDP~KHAM and DANIELF. ANDERSON Texas InstrumentsIncorporated,P.O. Box 1443, Houston, TX 77001, U.S.A. (Received 7 December
1983; in revised form 18 September 1984)
Abstract-The continuing advancements in integrated circuit technology have placed new burdons on the circuitdesign engineer, who must rely extensively upon computersimulationto correctlypredictcircuitbehavior. One challenge is to develop better modelling techniques to more accurately deal with complex p-n junction struchues often used in modem VLSI designs. This paper presents an easily implemented method for deriving parameterswhich accurately model the behavior of MOS VLSI structurescontaining complex p-n junction capacitancecomponents. The methodology is applicable to both planarand laterally diffused junctions, whether formed by diit ion implantation or by diffusion from a finite or infiite source. The theories behind the equationsused and results of the applicationof this new techniqueare discussed. A flow chartfor a fitterprogram based on the new method is presentedand described. The correspondingprogramwritten for the Tl-59 scientific mWrammable calculator is available. Final model parametersare given and are shown to produce a numerical capkance model which is accurate to within 2%:
1. INTRODUCTION
Cj(Vr)
Accurate modelling of parasitic capacitance components in today’s MOS VLSI designs is gaining rapidly in importance and complexity. The use of more accurate junction capacitance models to describe the behavior of diffused areas which comprise the source and drain regions of MOSFET transistors, as well as many interconnect structures, is becoming more critical to proper circuit design. At the same time, this modelling has become a more involved exercise owing to the use of certain interconnect structures which are now possible due to various innovative process techniques. Precise models for junction capacitance are important in at least two areas. First, for general simulation of propagation delays, p-n junction capacitance plays a greater role as the ratio of gate &lay to total stage delay continues to decline. Second, junction capacitance can be a critical performance factor in dynamic chargesharing circuits such as signal sensing in Dynamic RAMS, particularly DRAM’s exploiting diffused bit lines. This paper presents several important innovations in modelling methodology. These have been incorporated into a versatile fitter program which can derivep-n junction capacitance model parameters of greatly improved accuracy for all the various junction capacitance components which may coexist for any given process.
= (A * KPN)/m
(1 - (V,/2@r))m
(1)
where: Cj(V,) is the p-n junction capacitance as a timction of the applied reverse-bias voltage (units in pF); A is the area of the p-n junction (units in mm’); KPN is the capacitance per unit ama of the junction, normalized (with respect to $3) under 0 V bias. (units in pF mm-‘); +F is the effective Fermi potential of the more lightly doped side, assuming a one-sided junction (units in V); V, is the junction reverse bias voltage (units in V); m is the effective junction grading coefficient. 3. EXTENSIONOF THE TIIEORY
In MOS VLSI, a junction diffused into a homogeneous bulk is usually accompanied by otherp-n junction capacitance components (see Fig. 1). In the simplest case, there is the junction formed between a source/drain diffusion and the field (channel-stop) implant, which serves to isolate the active structures. Also, a buried contact between a source/drain diffusion and heavily doped polysilicon can result in two additional junctions, with the bulk and with the field implant. These junctions have properties differing from the fast two, since outdiffusion of phosphorous from the polysilicon source produces markedly different doping profiles. As all four junction capacitance components may coexist within a single structure, it challenges the designer to derive a model which can describe the combined effects, since 2. TIIEORETICALDERIVATIONS none of the individual components can be quantified by Classical derivations concerning capacitance of p-n direct measurement. junctions under reverse-bias conditions have been deThese four components of junction capacitance are scribed in the literature [l-4]. These derivations have led illustrated in Fig. 1 and summarized below: to the following general equation which has been adopted for use in calculation of depletion layer capaciC. is the capacitance per tit area of a source/drain tance in SPICE simulations: to bulk junction.
713
774
R.
RNKHAM
and D. F.
1
ANDERSON
of parameters which are known from the process flow and to minimize the number of variables, modifiers for KPN are used such that: for C,; for C;;
KPN(eff)
= KPNW
KPN’(eff)
= KPN’m
and
where N, = doping concentration of the bulk; N, = effective doping concentration of the field implant, in the case of a junction with a source/drain region; N: = effective doping concentration of the field implant, in the case of a junction with a buried contact region. These modifiers describe how KPN is changed at the junctions with field implanted regions relative to the junctions with the bulk. The four expanded equations can thus be written: C, = (A, * KPN)/w
(1 - (V,/24F))”
(2d
P-BULK
(1 - (V,/2#‘,))ma
C, = (A, * KPNm)/m Fig. 1. MOSFET structure showing area and sidewall components for arsenic implanted source/drain and phosphorous diffused extended buried contact interconnect.
(2W C: = (A: * KPN’)/w
(1 - (V,/2@‘))“’
(2d
C: = (A: * KPN’a)/m C, is the capacitance per unit area of a source/drainto-field-implant junction. CL is the capacitance per unit area of a buried contact to bulk junction. CL is the capacitance per unit area of a buried contactto-field-implant junction.
Traditionally, the value of KPN has been calculated by measuring the capacitance value of a test diode under 0 V bias. The term (1 - V,/24F)m reduces to 1 when V, = 0, so KPN is easily solved by using eqn (1). While this method has some merit when applied to circuits with grounded substrates, one must assume that the theory relating to eqn (l), i.e. KPN is constant, holds for V, values from 0 to V, V. The matter is further complicated because many circuits incorporate either an external or on-chip substrate voltage supply which is used to bias the bulk negative (for NMOS) with respect to V, [5]. This is done to decrease the p-n junction depletion layer capacitance and to reduce the so-called “body” or backgate bias effect [5,6]. On such circuits, a bias of 0 V is never encountered. Thus, evaluating KPN at this voltage will result in a mathematical model of reduced accuracy. One new procedure proposed by this paper involves deriving an effective value for KPN by solving eqn (1) at points encompassing the full range of V, values to be encountered by the circuit, and setting KPN equal to the mean of these calculated values. This method was incorporated in the fitter program developed in conjunction with this paper and was found to greatly reduce the average fit error of the capacitance model. Equation (1) could be applied to each of the four capacitance components, with different values for each parameter being the result. However, to take advantage
* (1 - (Vr/2r#~F:))~;. 4.
(2d)
DESCRIPTIONOF TEST STRUCTURJBAND MEASUREMENTTFCIiNIQUFS
The modelling procedure presented here was implemented on test structure4 processed in Scaled NMOS (SMOS) technology [7]. The process traits of the structures germane to the purposes of this paper are:
1) self-aligned arsenic ion implanted source/drain regions; 2) single-level polysilicon doped with phosphorous; 3) buried contacts between polysilicon and sour& drain regions, The planar junction area for each of the four capacitance components was measured from composite die plots. Junction depths were measured from SEM photos of typical structures. A description of the test structures can be found in Table 1. C-V measurements were taken at 27°C using a Boonton model 72BD capacitance meter with an externally supplied bias voltage varied from - 8.0 to - 1.6 V. Capacitance was recorded at steps of +0.8 V. Voltages Table 1. Junction area components of test structure.s @nits in mn?) StlUcNre
A,
A*
A:
A:
1
45.522E-3 25.304E-3 8.219E3 3.250E3
426.720E-6 6.828 E-3 224.028E-6 176.022E-6
0” 31.613E-3 7.903E-3
: 355.600E-6 1.788E-3
: 4
Note thatA, andA; were multipliedby Xj aadXl, ~.specriv~ly. x, was mcBsured Bs0.5 /Lm,x,! as 1.0 /.un.
Mcdelling junction capacitance of multiple-doped regions
more positive than - 1.6 V were excluded, as an on-chip bias generator is assumed. The C-V measurements were taken on a random sampling of 18 test bars from various wafers and production lots in order to encompass a typical range of parametric variations. From this sampling, a mean capacitance value was determined at each of the bias voltages for each of the four test devices, and all values were then corrected for stray capacitance due to the test pads and interconnect. 5. EXTRACTIONOF CAPACITANCE COMPONENTS area values and mean C-V values were determined, the four individual components were extracted by solving the following simultaneous equations for C,, C,, CL, and Cj at each voltage K: Once the
C&l)
= A.(l)C.
+ A,(l)C,
+ A:(l)C:
+ A:(l)C:
775
Cti(2)
= k(2)C.
+ A,(2)C, + A:(2)C:
+ A:(2)C:
L,(3)
= %(3)C.
+ A,(3)C. + A:(3)C:
+ A:(3)C:
c-,(4)
= A.(4)C. + A,(4)C, + A:(4)C:
+ A:(4)C:
where Cti(l-4) = measured total capacitance of each of the four test structures at each bias voltage V,, minus stray capacitance. A&1-4) = measured source/drain diffused area of each test strucmre. A:( l-4) = measured buried contact area of each test structure. A.(1-4) = measured periphery of sour&drain diffised area of each test structure multiplied by junction depth X,. A:( 14) = measured periphery of buried contact area of each test structure multiplied by junction depth Xj. The solution of these simultaneous eqati0nS Was eased by use of the determinant matrix program resident
Q
START
Soiw KPN as function
Enter VR max ,VR min, VR increment,$,a No
ot m =c h8a8)avR
Enter C (meashfws
Next
vR,8tore in array# t
0
Initialize Registers
C$ meaal,Nettl~
1Solve moan W Error 1 1
Solve mean KPN
1
Solve In Cx(measI 8 in (1 tVR/2oFK) Next Cx(meas),Next VR
G No
4
initialize Regirten
Last
Cx(model 3 S
(Tgig-)
0 C
Fig. 2. Flow chart of the.fitter programused to derive the model parameters.
R. PINKHAM and D. F. ANDERSON
776
in the Master Library module of the ‘II-59 Scientific Programmable Calculator [Sl .
centage error calculated. The mean of these values is the average percentage error of the model. The steps outlined above are repeated to derive all model parameters for each of the junction components. 6. DERIVATION OF MODEL PARAMRTRRS BY It should be noted that since the other parameters are THR FITTER PROGRAM adjusted by the program as N, is varied, an accurate On examining the four expanded equations (2a)model can result even though the individual calculated (2d), it is seen that terms may be combined to produce parameters are grossly in error. The correct procedure to the familiar universal equation of the form, follow is to find the parameters of the junction to bulk component first, then solve for the corresponding fieldC, = (Ax* KPNxm)/m(l - (v,/2@9"* implant junction component by iterating N, until a (3) matching value for effective KPN is achieved. where the “x” terms represent parameters pertaining to 7. RESULTS one of the four extracted components. For example "m," represents m, m’, m,,or ml. Table 2 lists the model parameters derived by impleThe use of this universal equation eased the develmentation of the fitter program as written for the TI-59. opment of the fitter routine, as it allowed each of the Figure 3 demonstrates the correlation of the values calcapacitance components to be described by a single culated from the model and the original extracted values. algorithm. Although four model components were used hi this Figure 2 shows a flow chart of the fitter program. analysis, the algorithms used by the fitter program allow Note that upon setting the range and step value of the it to be applied to simple structures with fewer junction reverse-bias voltage V,, the ambient test temperature T,, components, as well as to structures of even greater is entered in order to determine the intrinsic carrier concomplexity. centration s(T) by the formula: ni(T) = 2(2~~T/hZ)3'2(mfm,*)3/4eE8(4) where EB = bandgap of silicon; h = Planck’s constant; m* and m,* = effective mass for electrons and holes, re&ectively. Values for N, and N, are next entered to allow calculation of +Fx by the equation: 4Fx = kT/q * ln(NJhi).
8. CONCLUSION A new procedure has been developed to accurately model p-n junction capacitance components inherent in MOS VLSI source/drah~ and extended buried contact
(5)
In the case of capacitance components involving junctions with the bulk, i.e. C, and Cl, the N, value equals N,, the bulk doping concentration. Since this is known from the process flow, t$Fxcanbe immediately derived . for these components. However the capacitance compo. , nents which involve junctions with the field implant, i.e. .' C, and Cl, N, is a fitted parameter and 4Fx is recalculated for each iteration. -i Next, the C,(measured) values for one of the extracted capacitance components, at each bias voltage V,, are entered in a sequential array which is used by subsequent routines. The fist of these routines uses the linear regression function of the TI-59 to derive the grading coefficient m,. This subroutine computes a best fit plot of In C, vs ln(1 - V,/24F,), then calculates the slope (m)of the fitted line [91. The final parameter, effective KPN, is derived by solving eqn (1) using the computed value of mXand each of the array values, then finding the mean value as outlined in Section 3. The accuracy of each of the model components is -3.2 -1.6 -6.4 -4.6 -40 determined by substituting the calculated parameters into v, , Volts eqn (3) and creating a new array of C,(model) vs V,. Fig. 3. Composite plots of modelled and extracted values of Each point of this array is then compared with the corre- Co, CS, Ca ‘, and Cs ’ vs bias voltage V,. Solid and dashed lines are modelled values. sponding value of the fiit array, and the resulting per-
Modelling junction capacitance of multiple-doped regions Table 2. Calculated parameters Parameter
N.
6
KG/ KPN’ m m’ m,
, ;; N:
Value
3.000 El4 crne3 0.257 0.366 0.362 50.422 44.967
V v V pF mm-’ DF mm-’
0.4924
0.3910 0.1821 0.3184 2.038 El6 cme3 1.769 El6 cme3
interconnect structures. The analysis was performed on NMOS test structures, but is equally suitable for use on PMOS or CMOS processes. Process tolerant data sampling was employed. Improved accuracy of complex p-n junction capacitance models has resulted from extending the classical equations to better model actual device structures and operating conditions. Complete documentation of the fitter program as written for the
177
TI-59 Scientific Programmable Calculator is available from the authors. RBFERENCES
1. A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, New York, 1967, pp. 169-179. 2. B. G. Streetman, Solid State Electronic Devices, Second Edition, Prentice-Hall, Englewood Cliffs, NJ, 1972, pp. 173-176, pp. 183-185. 3. A. B. Glaser and G. E. Subak-Sharpe, Integrated Circuit Engineering, Bell Labs. Inc., Murray Hill, NJ, 1977, pp. 16-17. 4. ‘s: M. Sze, Physics of Semiconductor Devices, John Wiley & Sons. New York. 1969. DD. 84-96. 5. C. Rho&s and R. .hnk&& Electronic Design, 29, 20, 179-184 (1981). 6. R. H. Crawford, ‘MOSFET in Circuit Design,” Texas Instruments Electronics Series, pp. 594-597. 7. C. Rhodes, R. Pinkham, E Vale& and R. Ramsey, IEEE J. Solid-St. Circuits, SC16, 594-597 (1981). 8. TI’Programmable 58159 Master Library Manual, Texas
Instruments Inc., 1977, p. 9. 9. TI Programmable 58159 Personal Programming Manual, Texas hruments Inc., 1977, pp. V-36, V-37.10. R. S. Muller and T. I. Kamins. Device Electronics for Integrated Circuits, John Wiley’& Sons, New Yo& 1977, pp. 120-122.
1986
0038-llOU86 $3.00 + 0.00 Pqamon loumals Ltd
A TECHNIQUE FOR MODELLING p-n JUNCTION DEPLETION CAPACITANCE OF MULTIPLE DOPING REGIONS IN INTEGRATED CIRCUITS RAYMONDP~KHAM and DANIELF. ANDERSON Texas InstrumentsIncorporated,P.O. Box 1443, Houston, TX 77001, U.S.A. (Received 7 December
1983; in revised form 18 September 1984)
Abstract-The continuing advancements in integrated circuit technology have placed new burdons on the circuitdesign engineer, who must rely extensively upon computersimulationto correctlypredictcircuitbehavior. One challenge is to develop better modelling techniques to more accurately deal with complex p-n junction struchues often used in modem VLSI designs. This paper presents an easily implemented method for deriving parameterswhich accurately model the behavior of MOS VLSI structurescontaining complex p-n junction capacitancecomponents. The methodology is applicable to both planarand laterally diffused junctions, whether formed by diit ion implantation or by diffusion from a finite or infiite source. The theories behind the equationsused and results of the applicationof this new techniqueare discussed. A flow chartfor a fitterprogram based on the new method is presentedand described. The correspondingprogramwritten for the Tl-59 scientific mWrammable calculator is available. Final model parametersare given and are shown to produce a numerical capkance model which is accurate to within 2%:
1. INTRODUCTION
Cj(Vr)
Accurate modelling of parasitic capacitance components in today’s MOS VLSI designs is gaining rapidly in importance and complexity. The use of more accurate junction capacitance models to describe the behavior of diffused areas which comprise the source and drain regions of MOSFET transistors, as well as many interconnect structures, is becoming more critical to proper circuit design. At the same time, this modelling has become a more involved exercise owing to the use of certain interconnect structures which are now possible due to various innovative process techniques. Precise models for junction capacitance are important in at least two areas. First, for general simulation of propagation delays, p-n junction capacitance plays a greater role as the ratio of gate &lay to total stage delay continues to decline. Second, junction capacitance can be a critical performance factor in dynamic chargesharing circuits such as signal sensing in Dynamic RAMS, particularly DRAM’s exploiting diffused bit lines. This paper presents several important innovations in modelling methodology. These have been incorporated into a versatile fitter program which can derivep-n junction capacitance model parameters of greatly improved accuracy for all the various junction capacitance components which may coexist for any given process.
= (A * KPN)/m
(1 - (V,/2@r))m
(1)
where: Cj(V,) is the p-n junction capacitance as a timction of the applied reverse-bias voltage (units in pF); A is the area of the p-n junction (units in mm’); KPN is the capacitance per unit ama of the junction, normalized (with respect to $3) under 0 V bias. (units in pF mm-‘); +F is the effective Fermi potential of the more lightly doped side, assuming a one-sided junction (units in V); V, is the junction reverse bias voltage (units in V); m is the effective junction grading coefficient. 3. EXTENSIONOF THE TIIEORY
In MOS VLSI, a junction diffused into a homogeneous bulk is usually accompanied by otherp-n junction capacitance components (see Fig. 1). In the simplest case, there is the junction formed between a source/drain diffusion and the field (channel-stop) implant, which serves to isolate the active structures. Also, a buried contact between a source/drain diffusion and heavily doped polysilicon can result in two additional junctions, with the bulk and with the field implant. These junctions have properties differing from the fast two, since outdiffusion of phosphorous from the polysilicon source produces markedly different doping profiles. As all four junction capacitance components may coexist within a single structure, it challenges the designer to derive a model which can describe the combined effects, since 2. TIIEORETICALDERIVATIONS none of the individual components can be quantified by Classical derivations concerning capacitance of p-n direct measurement. junctions under reverse-bias conditions have been deThese four components of junction capacitance are scribed in the literature [l-4]. These derivations have led illustrated in Fig. 1 and summarized below: to the following general equation which has been adopted for use in calculation of depletion layer capaciC. is the capacitance per tit area of a source/drain tance in SPICE simulations: to bulk junction.
713
774
R.
RNKHAM
and D. F.
1
ANDERSON
of parameters which are known from the process flow and to minimize the number of variables, modifiers for KPN are used such that: for C,; for C;;
KPN(eff)
= KPNW
KPN’(eff)
= KPN’m
and
where N, = doping concentration of the bulk; N, = effective doping concentration of the field implant, in the case of a junction with a source/drain region; N: = effective doping concentration of the field implant, in the case of a junction with a buried contact region. These modifiers describe how KPN is changed at the junctions with field implanted regions relative to the junctions with the bulk. The four expanded equations can thus be written: C, = (A, * KPN)/w
(1 - (V,/24F))”
(2d
P-BULK
(1 - (V,/2#‘,))ma
C, = (A, * KPNm)/m Fig. 1. MOSFET structure showing area and sidewall components for arsenic implanted source/drain and phosphorous diffused extended buried contact interconnect.
(2W C: = (A: * KPN’)/w
(1 - (V,/2@‘))“’
(2d
C: = (A: * KPN’a)/m C, is the capacitance per unit area of a source/drainto-field-implant junction. CL is the capacitance per unit area of a buried contact to bulk junction. CL is the capacitance per unit area of a buried contactto-field-implant junction.
Traditionally, the value of KPN has been calculated by measuring the capacitance value of a test diode under 0 V bias. The term (1 - V,/24F)m reduces to 1 when V, = 0, so KPN is easily solved by using eqn (1). While this method has some merit when applied to circuits with grounded substrates, one must assume that the theory relating to eqn (l), i.e. KPN is constant, holds for V, values from 0 to V, V. The matter is further complicated because many circuits incorporate either an external or on-chip substrate voltage supply which is used to bias the bulk negative (for NMOS) with respect to V, [5]. This is done to decrease the p-n junction depletion layer capacitance and to reduce the so-called “body” or backgate bias effect [5,6]. On such circuits, a bias of 0 V is never encountered. Thus, evaluating KPN at this voltage will result in a mathematical model of reduced accuracy. One new procedure proposed by this paper involves deriving an effective value for KPN by solving eqn (1) at points encompassing the full range of V, values to be encountered by the circuit, and setting KPN equal to the mean of these calculated values. This method was incorporated in the fitter program developed in conjunction with this paper and was found to greatly reduce the average fit error of the capacitance model. Equation (1) could be applied to each of the four capacitance components, with different values for each parameter being the result. However, to take advantage
* (1 - (Vr/2r#~F:))~;. 4.
(2d)
DESCRIPTIONOF TEST STRUCTURJBAND MEASUREMENTTFCIiNIQUFS
The modelling procedure presented here was implemented on test structure4 processed in Scaled NMOS (SMOS) technology [7]. The process traits of the structures germane to the purposes of this paper are:
1) self-aligned arsenic ion implanted source/drain regions; 2) single-level polysilicon doped with phosphorous; 3) buried contacts between polysilicon and sour& drain regions, The planar junction area for each of the four capacitance components was measured from composite die plots. Junction depths were measured from SEM photos of typical structures. A description of the test structures can be found in Table 1. C-V measurements were taken at 27°C using a Boonton model 72BD capacitance meter with an externally supplied bias voltage varied from - 8.0 to - 1.6 V. Capacitance was recorded at steps of +0.8 V. Voltages Table 1. Junction area components of test structure.s @nits in mn?) StlUcNre
A,
A*
A:
A:
1
45.522E-3 25.304E-3 8.219E3 3.250E3
426.720E-6 6.828 E-3 224.028E-6 176.022E-6
0” 31.613E-3 7.903E-3
: 355.600E-6 1.788E-3
: 4
Note thatA, andA; were multipliedby Xj aadXl, ~.specriv~ly. x, was mcBsured Bs0.5 /Lm,x,! as 1.0 /.un.
Mcdelling junction capacitance of multiple-doped regions
more positive than - 1.6 V were excluded, as an on-chip bias generator is assumed. The C-V measurements were taken on a random sampling of 18 test bars from various wafers and production lots in order to encompass a typical range of parametric variations. From this sampling, a mean capacitance value was determined at each of the bias voltages for each of the four test devices, and all values were then corrected for stray capacitance due to the test pads and interconnect. 5. EXTRACTIONOF CAPACITANCE COMPONENTS area values and mean C-V values were determined, the four individual components were extracted by solving the following simultaneous equations for C,, C,, CL, and Cj at each voltage K: Once the
C&l)
= A.(l)C.
+ A,(l)C,
+ A:(l)C:
+ A:(l)C:
775
Cti(2)
= k(2)C.
+ A,(2)C, + A:(2)C:
+ A:(2)C:
L,(3)
= %(3)C.
+ A,(3)C. + A:(3)C:
+ A:(3)C:
c-,(4)
= A.(4)C. + A,(4)C, + A:(4)C:
+ A:(4)C:
where Cti(l-4) = measured total capacitance of each of the four test structures at each bias voltage V,, minus stray capacitance. A&1-4) = measured source/drain diffused area of each test strucmre. A:( l-4) = measured buried contact area of each test structure. A.(1-4) = measured periphery of sour&drain diffised area of each test structure multiplied by junction depth X,. A:( 14) = measured periphery of buried contact area of each test structure multiplied by junction depth Xj. The solution of these simultaneous eqati0nS Was eased by use of the determinant matrix program resident
Q
START
Soiw KPN as function
Enter VR max ,VR min, VR increment,$,a No
ot m =c h8a8)avR
Enter C (meashfws
Next
vR,8tore in array# t
0
Initialize Registers
C$ meaal,Nettl~
1Solve moan W Error 1 1
Solve mean KPN
1
Solve In Cx(measI 8 in (1 tVR/2oFK) Next Cx(meas),Next VR
G No
4
initialize Regirten
Last
Cx(model 3 S
(Tgig-)
0 C
Fig. 2. Flow chart of the.fitter programused to derive the model parameters.
R. PINKHAM and D. F. ANDERSON
776
in the Master Library module of the ‘II-59 Scientific Programmable Calculator [Sl .
centage error calculated. The mean of these values is the average percentage error of the model. The steps outlined above are repeated to derive all model parameters for each of the junction components. 6. DERIVATION OF MODEL PARAMRTRRS BY It should be noted that since the other parameters are THR FITTER PROGRAM adjusted by the program as N, is varied, an accurate On examining the four expanded equations (2a)model can result even though the individual calculated (2d), it is seen that terms may be combined to produce parameters are grossly in error. The correct procedure to the familiar universal equation of the form, follow is to find the parameters of the junction to bulk component first, then solve for the corresponding fieldC, = (Ax* KPNxm)/m(l - (v,/2@9"* implant junction component by iterating N, until a (3) matching value for effective KPN is achieved. where the “x” terms represent parameters pertaining to 7. RESULTS one of the four extracted components. For example "m," represents m, m’, m,,or ml. Table 2 lists the model parameters derived by impleThe use of this universal equation eased the develmentation of the fitter program as written for the TI-59. opment of the fitter routine, as it allowed each of the Figure 3 demonstrates the correlation of the values calcapacitance components to be described by a single culated from the model and the original extracted values. algorithm. Although four model components were used hi this Figure 2 shows a flow chart of the fitter program. analysis, the algorithms used by the fitter program allow Note that upon setting the range and step value of the it to be applied to simple structures with fewer junction reverse-bias voltage V,, the ambient test temperature T,, components, as well as to structures of even greater is entered in order to determine the intrinsic carrier concomplexity. centration s(T) by the formula: ni(T) = 2(2~~T/hZ)3'2(mfm,*)3/4eE8(4) where EB = bandgap of silicon; h = Planck’s constant; m* and m,* = effective mass for electrons and holes, re&ectively. Values for N, and N, are next entered to allow calculation of +Fx by the equation: 4Fx = kT/q * ln(NJhi).
8. CONCLUSION A new procedure has been developed to accurately model p-n junction capacitance components inherent in MOS VLSI source/drah~ and extended buried contact
(5)
In the case of capacitance components involving junctions with the bulk, i.e. C, and Cl, the N, value equals N,, the bulk doping concentration. Since this is known from the process flow, t$Fxcanbe immediately derived . for these components. However the capacitance compo. , nents which involve junctions with the field implant, i.e. .' C, and Cl, N, is a fitted parameter and 4Fx is recalculated for each iteration. -i Next, the C,(measured) values for one of the extracted capacitance components, at each bias voltage V,, are entered in a sequential array which is used by subsequent routines. The fist of these routines uses the linear regression function of the TI-59 to derive the grading coefficient m,. This subroutine computes a best fit plot of In C, vs ln(1 - V,/24F,), then calculates the slope (m)of the fitted line [91. The final parameter, effective KPN, is derived by solving eqn (1) using the computed value of mXand each of the array values, then finding the mean value as outlined in Section 3. The accuracy of each of the model components is -3.2 -1.6 -6.4 -4.6 -40 determined by substituting the calculated parameters into v, , Volts eqn (3) and creating a new array of C,(model) vs V,. Fig. 3. Composite plots of modelled and extracted values of Each point of this array is then compared with the corre- Co, CS, Ca ‘, and Cs ’ vs bias voltage V,. Solid and dashed lines are modelled values. sponding value of the fiit array, and the resulting per-
Modelling junction capacitance of multiple-doped regions Table 2. Calculated parameters Parameter
N.
6
KG/ KPN’ m m’ m,
, ;; N:
Value
3.000 El4 crne3 0.257 0.366 0.362 50.422 44.967
V v V pF mm-’ DF mm-’
0.4924
0.3910 0.1821 0.3184 2.038 El6 cme3 1.769 El6 cme3
interconnect structures. The analysis was performed on NMOS test structures, but is equally suitable for use on PMOS or CMOS processes. Process tolerant data sampling was employed. Improved accuracy of complex p-n junction capacitance models has resulted from extending the classical equations to better model actual device structures and operating conditions. Complete documentation of the fitter program as written for the
177
TI-59 Scientific Programmable Calculator is available from the authors. RBFERENCES
1. A. S. Grove, Physics and Technology of Semiconductor Devices, John Wiley & Sons, New York, 1967, pp. 169-179. 2. B. G. Streetman, Solid State Electronic Devices, Second Edition, Prentice-Hall, Englewood Cliffs, NJ, 1972, pp. 173-176, pp. 183-185. 3. A. B. Glaser and G. E. Subak-Sharpe, Integrated Circuit Engineering, Bell Labs. Inc., Murray Hill, NJ, 1977, pp. 16-17. 4. ‘s: M. Sze, Physics of Semiconductor Devices, John Wiley & Sons. New York. 1969. DD. 84-96. 5. C. Rho&s and R. .hnk&& Electronic Design, 29, 20, 179-184 (1981). 6. R. H. Crawford, ‘MOSFET in Circuit Design,” Texas Instruments Electronics Series, pp. 594-597. 7. C. Rhodes, R. Pinkham, E Vale& and R. Ramsey, IEEE J. Solid-St. Circuits, SC16, 594-597 (1981). 8. TI’Programmable 58159 Master Library Manual, Texas
Instruments Inc., 1977, p. 9. 9. TI Programmable 58159 Personal Programming Manual, Texas hruments Inc., 1977, pp. V-36, V-37.10. R. S. Muller and T. I. Kamins. Device Electronics for Integrated Circuits, John Wiley’& Sons, New Yo& 1977, pp. 120-122.