A top-down constraint-driven design methodology for analog integrated circuits

A top-down constraint-driven design methodology for analog integrated circuits

Book Reviews A Top-Down Constraint-Driven Design Methodology for Analog Integrated Circuits H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E...

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Book Reviews

A Top-Down Constraint-Driven Design Methodology for Analog Integrated Circuits H. Chang, E. Charbon, U. Choudhury, A. Demir, E. Felt, E. Liu, E. Malavasi, A. SangiovanniVincentelli and I. Vassiliou, Kluwer Academic Publishers, NorweU, MA, 1997, 366pp., US$115.00, UK£81.65, Dfl.215.00 The first comment that may be made on this book is the remarkable number of authors who are listed as having written its contents, even though there is no indication that individual chapters are the work of individual authors. Indeed, the style throughout appears to be the same, which may indicate only one principal writer of this text. It is left for the reader to ponder which one, if indeed this is the case. The material of this text is based on on-going research activity at the University of California at Berkeley, which is considering new computeraided design methodologies for analogue and mixed analogue/digital IC design, working from a top-down hierarchical level. Chapter 1 is a good introduction to the past work on analogue CAD, and notes silicon compilation, knowledge-based techniques, hybrid systems and human-driven systems, leading to the specific methodology of constraint-driven design, which is the subject of the following chapters. Chapter 2 introduces this methodology, which briefly consists of two phases, namely: (i) the mapping of performance specifications onto bounds on all physical parasitics relevant to the implementation; and (ii) enforcing each bound during the physical assembly of the design. A technique of 'constraint graphs' is employed in this procedure. Simulation and behaviour modelling is central to the procedures, together with architectural mapping and optimization. Bottom-up verification is done after layout synthesis.

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Chapters 3-8 cover this material, following which three further chapters giving examples of practical design exercises are given. Overall, this is an interesting text for all who are concerned with analogue CAD and research in software developments in this subject area. The claim that this design methodology will result in a high probability of right-first-time silicon must be judged against other existing methodologies, and is not necessarily proven by this publication. This is, however, a book which should be available to students and others who are actively engaged in analogue CAD research, if only for the very extensive list of over 300 references with which the book concludes.

M.S. Harris Synthesis of Finite State Machines: Functional Optimization T. Kam, T. Villa, R. Brayton and A. SangiovanniVincentelli, Kluwer Academic Publishers, Norwell, MA, 1997, 282pp., US$110.00, UK£78.10, Dr.205.00 This is yet a further book detailing activities at the University of California at Berkeley, although the affiliation of one of the authors (T.K.) is now listed as the Intel Corporation. The book is stated to be the first of two monographs addressing the synthesis of finite state machines, this one addressing functional optimization, with the subsequent one addressing logic optimization. It is possibly a pity that these two associated subject areas could not have been combined into one text, at the expense of losing a score of one in the tally of university department publications. Functional optimization is defined as the computation of all permissible sequential functions for a given topology of interconnected finite state machines and the selection of a 'best' function from the set of permissible ones, the