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Accelerated ageing of IMPATT diodes
132
World Abstracts on Microelectronics and Reliability
One of the methods to understand the characteristics of the short channel M O S F E T s is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the twodimensional method. In this paper, the drain breakdown characteristics for the short channel M O S F E T s are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.
Experimental characterization of MOST's scaled down to the I pm level. HtDEO SUNAMt, YASUO WADA and NORIKAZU HASHIMOTO. Microelectron. Reliab. 20, 803 (1980). Fundamental MOS device performances are experimentally analyzed for the projected three levels of scaled-down, silicon-gate devices envisioned in the next decade. The final third-level device having 20 n m thick gate oxide and 0.7,am effective channel length will have vertical dimension only 0.35 times that of the present 3pro lithography level. Principal device characteristics discussed are threshold voltage, source to drain breakdown voltage, and effective carrier mobility under practical applied voltage conditions, mainly for dynamic MOS memory operation. It is found that breakdown voltage reduction is the main obstacle hindering down-scaling, and also that the mobility lowering in the shorter channel length region reduces the merits of down-scaling. MOS device performances for the coming 1 ,urn geometry level LSi's under practical operation conditions are discussed on the basis of the experimental results obtained. Modelling of submicrometer gate field effect transistors. B. CARNEZ, A. CAPPY, G. SALMER and E. CONSTANT. Acta Electronica 23 (2) 165 (1980) (in German). The development of low noise amplifiers and receivers for communication and radar applications needs components that can operate up to increasing frequencies and that present decreasing geometric sizes: this leads to new effects resulting from the non stationary electron dynamics. This paper presents a new theoretical model for field effect transistor (FET) based on the macroscopic m o m e n t u m and energy conservation equations that accounts for these p h e n o m e n a while keeping sufficiently simple to be suitable for a deskcomputer. From this model, the noise properties of submicrometer FET's can be derived. In addition, the potential advantages of FET's made from other semi-conductor materials than GaAs (InP or (Ga, In) As) are investigated.
Gallium arsenide metal field effect transistor reliability study. D. M EIGNANT.Acta Electronica 23 (2) 151 (1980) (in German ). The increasing use of gallium arsenide field effect transistors in microwave systems requires the estimation of the reliability of these components. Therefore the degradation of low noise transistors without SiO2 coating and without thickening the ohmic contacts and gate pad have been studied. Results are very promising: a mean time before failure (MTBF) of 2 x 106 hours at 100°C for the ohmic contacts is measured. Moreover, for transistors biased at m i n i m u m noise figure, degradations of the entire device are very slight: in more than 5000 hours, the variations of the noise figure and of the associated gain are smaller than 0.5 dB. Errors in life prediction due to temperature inaccuracies, i. W. STANLEY. Microelectron. Reliab. 21 (2) 173 (1981). An assessment is made of the errors in life prediction that can occur for high power dissipation semiconductor components
undergoing thermally accelerated life tests if allowances are not made for differences in die temperature between individual components of the same type.
Recoverable ionic contaminant induced failures on n-channel memory products. R. S. HEMMERT. Microelectron. Reliab. 21 ( 1 ) 63 (1981 ). For an n-channel M O S F E T device technology, thick oxide threshold voltage degradation on a device adjacent to a thin oxide device with exposed gate oxide and tapers frequently causes chip failure. If the thin gate oxide and tapers are completely covered, then threshold voltage stability can be attained using phosphosilicate glass to better ionic contaminants. A first order theory is proposed that relates circuit topology, electrical requirements, and ionic contaminant drift in oxides to chip failure. The model predicts the hierarchy of failing circuits within a chip and the recovery of these failures when left on temperature-bias testing. The latter implies that burn-in conditions must be carefully chosen to avoid recovery during temperature-bias testing. Failure to do so will allow this failure mode to go undetected and result in overly optimistic reliability projections for application conditions. C M O S iategrated circuit reliability. GEORGE L. SCHNABLE and ROBERT B. COMIZZOLI. Microelectron. Reliab. 21 (1) 33 (1981). This paper summarizes recently published data on C M O S integrated circuit failure rates, and provides information on the effects of voltage, temperature, device complexity, and packaging on C M O S failure rates. Other factors which can affect failure rate are also indicated, including designs, materials, processes, in-process controls, screening tests, and product maturity. Data on failure rates of N M O S and P M O S integrated circuits are provided to enable comparison with C M O S data. It is concluded that available data do not indicate any consistent reliability difference for C M O S versus N M O S or P M O S integrated circuits. Because of the many advantages of C M O S integrated circuit technology, continued increase in usage of C M O S circuits has been forecast, accompanied by further increases in C M O S integrated circuit reliability.
Power gallium arsenide metal field effect transistor: design and technology. P. BAUDET. Acta Electronica 23 (2) 119 (1980) (in German). Problems raised by power operation of GaAs metal semiconductor field effect transistors (MESFET's) are reviewed. Burn out mechanisms are also included. Then requirements for material and design of power M E S F E T ' s are presented. In addition the fabrication of a 1 pm multifinger gate structure power M E S F E T is described and its performances at 12 G Hz are reported. Accelerated ageing of IMPATT diodes. F. N. SINNADURAI. Microelectron. Reliab. 21 (2l 209 (1981). An investigation conducted to determine suitable reliability test methods for I M P A T T diodes has shown that elevated temperature accelerated their normal degradation in a predictable way only when the diodes were stressed with normal d.c. power applied and controlled in a constant-voltage mode. Normal degradation was manifested initially by an increase in thermal resistance and ultimately by short-circuits, both of which were caused by the progressive interaction of the constituents of the contact metallizations. Initial instabilities and infant mortalities had to be eliminated by burning-in the diodes before overstress results could be related to long-term wearout. Thereafter, simple d.c. was adequate to assess life expectancy because the changes in thermal resistance could be used to estimate consequent changes in r.f. performance. Sequence test method for reliability evaluation of semiconductor devices. VITTAL S. CANDADE. Microe/ectron. Reliab. 21 (2) 225 (1981). The failure-rate 2, of a device can be determined using Arrhenius model ;. = A e -~i~'1. The number of thermal cycles a device can withstand can be
World Abstracts on Microelectronics and Reliability
One of the methods to understand the characteristics of the short channel M O S F E T s is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the twodimensional method. In this paper, the drain breakdown characteristics for the short channel M O S F E T s are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.
Experimental characterization of MOST's scaled down to the I pm level. HtDEO SUNAMt, YASUO WADA and NORIKAZU HASHIMOTO. Microelectron. Reliab. 20, 803 (1980). Fundamental MOS device performances are experimentally analyzed for the projected three levels of scaled-down, silicon-gate devices envisioned in the next decade. The final third-level device having 20 n m thick gate oxide and 0.7,am effective channel length will have vertical dimension only 0.35 times that of the present 3pro lithography level. Principal device characteristics discussed are threshold voltage, source to drain breakdown voltage, and effective carrier mobility under practical applied voltage conditions, mainly for dynamic MOS memory operation. It is found that breakdown voltage reduction is the main obstacle hindering down-scaling, and also that the mobility lowering in the shorter channel length region reduces the merits of down-scaling. MOS device performances for the coming 1 ,urn geometry level LSi's under practical operation conditions are discussed on the basis of the experimental results obtained. Modelling of submicrometer gate field effect transistors. B. CARNEZ, A. CAPPY, G. SALMER and E. CONSTANT. Acta Electronica 23 (2) 165 (1980) (in German). The development of low noise amplifiers and receivers for communication and radar applications needs components that can operate up to increasing frequencies and that present decreasing geometric sizes: this leads to new effects resulting from the non stationary electron dynamics. This paper presents a new theoretical model for field effect transistor (FET) based on the macroscopic m o m e n t u m and energy conservation equations that accounts for these p h e n o m e n a while keeping sufficiently simple to be suitable for a deskcomputer. From this model, the noise properties of submicrometer FET's can be derived. In addition, the potential advantages of FET's made from other semi-conductor materials than GaAs (InP or (Ga, In) As) are investigated.
Gallium arsenide metal field effect transistor reliability study. D. M EIGNANT.Acta Electronica 23 (2) 151 (1980) (in German ). The increasing use of gallium arsenide field effect transistors in microwave systems requires the estimation of the reliability of these components. Therefore the degradation of low noise transistors without SiO2 coating and without thickening the ohmic contacts and gate pad have been studied. Results are very promising: a mean time before failure (MTBF) of 2 x 106 hours at 100°C for the ohmic contacts is measured. Moreover, for transistors biased at m i n i m u m noise figure, degradations of the entire device are very slight: in more than 5000 hours, the variations of the noise figure and of the associated gain are smaller than 0.5 dB. Errors in life prediction due to temperature inaccuracies, i. W. STANLEY. Microelectron. Reliab. 21 (2) 173 (1981). An assessment is made of the errors in life prediction that can occur for high power dissipation semiconductor components
undergoing thermally accelerated life tests if allowances are not made for differences in die temperature between individual components of the same type.
Recoverable ionic contaminant induced failures on n-channel memory products. R. S. HEMMERT. Microelectron. Reliab. 21 ( 1 ) 63 (1981 ). For an n-channel M O S F E T device technology, thick oxide threshold voltage degradation on a device adjacent to a thin oxide device with exposed gate oxide and tapers frequently causes chip failure. If the thin gate oxide and tapers are completely covered, then threshold voltage stability can be attained using phosphosilicate glass to better ionic contaminants. A first order theory is proposed that relates circuit topology, electrical requirements, and ionic contaminant drift in oxides to chip failure. The model predicts the hierarchy of failing circuits within a chip and the recovery of these failures when left on temperature-bias testing. The latter implies that burn-in conditions must be carefully chosen to avoid recovery during temperature-bias testing. Failure to do so will allow this failure mode to go undetected and result in overly optimistic reliability projections for application conditions. C M O S iategrated circuit reliability. GEORGE L. SCHNABLE and ROBERT B. COMIZZOLI. Microelectron. Reliab. 21 (1) 33 (1981). This paper summarizes recently published data on C M O S integrated circuit failure rates, and provides information on the effects of voltage, temperature, device complexity, and packaging on C M O S failure rates. Other factors which can affect failure rate are also indicated, including designs, materials, processes, in-process controls, screening tests, and product maturity. Data on failure rates of N M O S and P M O S integrated circuits are provided to enable comparison with C M O S data. It is concluded that available data do not indicate any consistent reliability difference for C M O S versus N M O S or P M O S integrated circuits. Because of the many advantages of C M O S integrated circuit technology, continued increase in usage of C M O S circuits has been forecast, accompanied by further increases in C M O S integrated circuit reliability.
Power gallium arsenide metal field effect transistor: design and technology. P. BAUDET. Acta Electronica 23 (2) 119 (1980) (in German). Problems raised by power operation of GaAs metal semiconductor field effect transistors (MESFET's) are reviewed. Burn out mechanisms are also included. Then requirements for material and design of power M E S F E T ' s are presented. In addition the fabrication of a 1 pm multifinger gate structure power M E S F E T is described and its performances at 12 G Hz are reported. Accelerated ageing of IMPATT diodes. F. N. SINNADURAI. Microelectron. Reliab. 21 (2l 209 (1981). An investigation conducted to determine suitable reliability test methods for I M P A T T diodes has shown that elevated temperature accelerated their normal degradation in a predictable way only when the diodes were stressed with normal d.c. power applied and controlled in a constant-voltage mode. Normal degradation was manifested initially by an increase in thermal resistance and ultimately by short-circuits, both of which were caused by the progressive interaction of the constituents of the contact metallizations. Initial instabilities and infant mortalities had to be eliminated by burning-in the diodes before overstress results could be related to long-term wearout. Thereafter, simple d.c. was adequate to assess life expectancy because the changes in thermal resistance could be used to estimate consequent changes in r.f. performance. Sequence test method for reliability evaluation of semiconductor devices. VITTAL S. CANDADE. Microe/ectron. Reliab. 21 (2) 225 (1981). The failure-rate 2, of a device can be determined using Arrhenius model ;. = A e -~i~'1. The number of thermal cycles a device can withstand can be