- Email: [email protected]
DC converter applications
Microelectronics Journal 35 (2004) 225–233 www.elsevier.com/locate/mejo
Advanced power semiconductors and ICs for DC/DC converter applications Dan Kinzer Research and Development, 233 Kansas St, International Rectifier, El Segundo, CA, USA
Abstract This paper describes recent advances in power semiconductor devices, integrated circuits, and packages for DC/DC converter applications. Special emphasis is placed on the latest discrete power MOSFET devices and packages. Features and trends in ICs for control of synchronous buck converters are highlighted as well. The paper will also cover a new class of miniaturized hybrid assembly that sets new efficiency standards for high current low output voltage applications. q 2003 Elsevier Ltd. All rights reserved. Keywords: Power MOSFET; DC/DC converter; Voltage regulator modules; Controller; PWM
1. Introduction One of the most exciting areas of power semiconductors and power electronics in general is the area of DC/DC converters. The rapid advancement in this field is driven by the ever-increasing current requirements of advanced VLSI circuits, especially microprocessors. The demands of this load include currents above 100 A, voltages approaching only 1 V and going lower, full load transient response approaching 100 ns, voltage regulation accuracy of 1% or less, efficiency above 90%, motherboard space consumption less than 20 cm2, and of course, cost that goes down every year even as the requirements get tougher. Achieving these goals requires a concerted effort in topology, control, drive, MOSFET, packaging and thermal design. The purpose of this paper is to illustrate some of those trends, discuss how some of those performance requirements are achieved, and indicate some directions for the future. Some examples will be chosen from embedded point of load, Voltage regulator modules (VRM) and isolated DC/DC converter designs.
2. Controllers and drivers The most pervasive topology for high performance DC/DC converters today is the synchronous buck
E-mail address: [email protected] (D. Kinzer). 0026-2692/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2692(03)00185-X
topology. This typically has a multiphase controller, which may range from 2 to 8 or even as much as 12 phases. Each phase drives two MOSFETs, which are optimised for high side and low side application. The high side switch controls the duty cycle and thus the output voltage, while the low side switch operates as a rectifier to keep inductor current flowing when the control FET is off. There are many ways to partition the phases, including single and dual phase controllers that synchronize themselves with other like ICs, master –slave configurations, and monolithic multiphase controllers. All of these may or may not include on-board gate drivers, depending on the capability of the process technology and the cost of full integration. In some case, at currents less than 10 A/phase, a single phase controller may integrate the gate drive as well as the MOSFETs themselves. An example of a representative three-phase PWM Controller with on-board MOSFET drivers which meets VRM 9.0 specification is shown in Fig. 1. It has a 5-Bit DAC for programming output voltage from 1.075 to 1.85 V in 25 mV steps and 1.0% output voltage accuracy over temperature. It employs a lossless average inductor current sensing technique and matches phase current with an internal transconductance amplifier (Fig. 2). Control is voltage mode, with programmable frequency from 50 to 500 kHz/phase. Other useful features include soft start, power good feedback, current limit using the synchronous FET Rdson to sense, overcurrent and overvoltage protection, and an easily implementable droop compensation circuit. This capability is required by Intel to
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Fig. 1. Schematic of a three-phase DC/DC converter.
keep the voltage in the right range under transient conditions. At full load, the power dissipation is somewhat reduced, while the voltage overshoot upon transition to light load is minimized. At light load, the voltage can be increased to get higher performance without excessive power consumption, and the undershoot going to full load is prevented. The specification and circuit performance are shown in Fig. 3. Some of the features that need to be incorporated into controllers in the future are scalability in the number of phases, a solution to the large amount of capacitance required in the circuit today, and the ability to climb up in frequency without excessive losses. There must be accurate current sharing, lossless sensing, and transient response on the order of one or two cycles. It must be accurate under all conditions, and of course take up a minimum of space. Examples of tiny Micro leadframe packages are given in Fig. 4. There is not a single answer today as to the appropriate process technology to implement these controllers. Many controllers still employ bipolar technology with minimum feature sizes above 1 mm. These technologies are quite suitable for analog and drive functionality, but may be limited in their ability to approach megahertz operation. Other controller areas implemented in full BCDMOS technologies, especially in circuits requiring higher input voltage capability, integrated MOS gate drive or full integration of the power transistor. Some such technologies have the ability to come close to the discrete MOSFET in performance figures of merit. System economics limits the output power of such circuits because the application cannot afford to use the high cost silicon in such complex technology for the power device. It is also difficult to obtain monolithic devices in the 10– 20 mV range and below because of the ohmic metal drops in the top surface drain and source connections, while discrete devices are
achieving resistances as low as 2 mV. Some companies are starting to offer more complete digital functionality in a controller, which allows more of the function to be implemented in standard CMOS technology with BiCMOS needed primarily for the I/Os. These technologies may employ CMOS and LDMOS structures using design rules extending down to 0.25 u.
3. Power MOSFETs The MOSFET is definitely the device of choice for DC/DC converter switch requirements today. It has a unique combination of ultralow conduction losses, low loss drive, high frequency capability, negligible storage time and robust SOA. There has been a tremendous amount of work on optimizing the MOSFET, and the main categories of device today are the planar DMOS vertical MOSFET, the trench vertical MOSFET and the lateral MOSFET. Today, large volumes of all types are performing the function,
Fig. 2. Lossless average inductor current sensing and phase matching.
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Fig. 3. Droop compensation compared to Intel specification.
although lateral MOSFETs are primarily offered as part of integrated solutions and not as discrete devices. The trench MOSFET may appear to be a relative newcomer to the scene, but in fact V-groove and U-groove trench structures were fabricated as early as the 1970s. However, it really was not until the development of advanced plasma etch techniques in the early to mid-90s that a suitable quality structure could be attained. Even today, the device brings substantial challenges in the area of process control, cleanliness, geometric tolerancing, trench filling, corner rounding and high quality gate oxidation. For some manufacturers, these issues have been mastered to the extent that high volume production is now common. The challenge that remains is to design the devices in such a way that they perform with maximum efficiency in today’s applications.
Fig. 4. Microleadframe packaging for IC controllers.
Fig. 5. Schematic drawing of state of the art trench FET.
The trench device in Fig. 5 (not to scale) shows some of the attributes of the device. The channel is arranged on the trench sidewall, while the gate electrode consists typically of the polysilicon that is used to fill the trench. High packing density is achieved by the vertical channel orientation, and by the relatively unrestricted current flow path form the channel through the epi layer to the underlying substrate material. As illustrated, it is preferred if the trench bottom oxide is thicker than the sidewall oxide in order to minimize the gate to drain overlap capacitance. By the same token, it is also beneficial to reduce the trench width, provided that the small radius of curvature does not cause current crowding and high electric field stress at the trench bottom. The P-base region defined the channel length, which of course is preferably as short as possible to lower both its resistance and the gate-source overlap capacitance. The source metallization must come in contact with the source and the base in a very low resistance fashion to ensure low resistance as well as keep the parasitic NPN bipolar inherent in the structure from turning on. A state of the art device may have a pitch as shown in the range of 2.4 u as has also been reported. The selection of the pitch is driven by application, depending on whether the device is to be optimized for highest packing density and therefore lowest conduction loss, or for low gate charge to achieve high speed and low switching loss. For low conduction loss, the normal figure of merit for the transistor is the Rdson X Area product, which determines the current density capability of the device. For high frequency
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Fig. 6. Forecasted trend in 30 V silicon FET Rdson.
operation, the switching charge Qswitch is defined which adds the amount of charge Cgs must receive to switch the current to the amount of charge Cgd must receive to slew the voltage. This charge is approximately proportional to chip area and inversely proportional to Rdson, which leads to the technology independent figure of merit Rdson X Qswitch. The expected trends in these figures of merit for 30 V rated silicon MOSFETs are shown in Figs. 6 and 7. It is worth noting on these charts that the planar DMOS performance shown in 2001, while the trench MOSFET of today is leading the roadmap to achieve this years levels. Recently, some data presented at ISPSD has indicated that lateral devices can come close to achieving the levels indicated for 2003 in the charge for Rdson X area, although those devices had breakdown voltage of only 15 V and were limited to small active area test structures where metal series resistance is only a small factor. The switching figure of merit Rdson X Qswitch is the characteristic where lateral devices are expected to perform competitively at low enough voltage and current. Another point to consider is the apparent saturation of the silicon roadmap in Rdson X Area, with a slowing rate of improvement. This means that all the relatively easy to tackle source of parasitic resistance such as substrate, contact, and top metal resistance have been substantially eliminated. The limitation appears to be due in part to
Fig. 7. Forecasted trend in 30 V silicon FET switching figure of merit.
the required channel length to withstand the rated 30 V without punchthrough, and the feasible packing density of the trenches. The second limitation is the ‘theoretical silicon limit’, which is determined from the minimum resistivity and thickness of the drain drift region required to withstand the voltage, assuming a uniform vertical current conduction within that region. The smaller the pitch and the spacing between trenches, the closer the device may approach that ideal limit. In order to break those limits, a new technology will need to be introduced. One must consider either the use of field contouring or charge balancing techniques to be able to enhance blocking voltage beyond the theoretical 1D planar junction limit, or one must consider the use of alternate high mobility or high critical field materials such as GaAs and GaN.
4. Discrete packaging Packaging for power MOSFETs must meet some important criteria. The package should add minimum electrical resistance to the device, considering that some MOSFET chips are now measured in microohms instead of milliohms. It should also have a very low thermal resistance to get the heat out, and an ability to channel that heat to the place where it is most effectively removed from the system. It should also be very low inductance, and of course low cost, robust, and friendly to the environment. Pictured in Fig. 8 are some widely used packages and a new package concept called the DirectFET. The SO8 is most common. It is 1.7 mm tall, and current must flow through a large number of typically 50 u gold wire bonds in parallel. The bonds are usually constrained to remain near the die edge, which results in a fairly large resistance in the wires as well as the die top metallization. Most of the heat must exit the package through the drain leads into the board the device is mounted on and from there to the ambient. The copper strap SO8 helps the situation by replacing the gold wires with the strap, which effectively shunts the top metal and wire resistance. This also creates a thermal path to
Fig. 8. Comparison of surface mount FET packages.
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and the losses in the package resistance are mostly eliminated. When a heat sink and forced air are applied, the current out of the same footprint is nearly doubled. This is only possible with a package that allows top side heat sink attachment. Fig. 11 shows the important point that even with nearzero thermal impedance to the printed circuit board, most applications use relatively small footprint trace and thus cannot remove much heat. That is why a low thermal resistance path away form the board is such a big advantage. In motherboards, it is preferred to keep heat away form the board, as there is already a heat overload from the microprocessor.
5. Integrated package solutions
Fig. 9. Package resistance of various common packages.
the source leads, allowing heat to exit both sides and lowering the thermal resistance into and through the board. The new DirectFET lowers the package profile to less than half, and places the junction directly in contact to the board through the same solder process used to mount other surface mount components. This effectively eliminates almost all the die free package resistance, and opens up a new cooling path through the top of the package that was not there before. A comparison to other package is shown in Fig. 9. The graph in Fig. 10 shows the improvement in efficiency and power handling capability gained through the new packaging. The efficiency is improved by 3% at 19 A, largely because the junction temperature is cooler
Excellent gains are possible in system efficiency and ease of use through a combination of the kinds of control, power semiconductor and packaging technologies discussed so far, as shown in Fig. 12. One of the advantages of integration is close coupling of controller and MOSFET to eliminate layout parasitics. Another is the close coupling of the Schottky diode and synchronous FET that are paralleled to make sure the body diode of the FET conducts as little as possible during the deadband period when both FETs are off. Yet another is due to the inclusion of debiasing capacitance on the input to eliminate ground noise and allow for clean signals to come from the controller or driver to the MOSFET gates. Other improvements come from the package thermal design. This is driven by the die to substrate thermal impedance, connection to the underlying board, and the ability to extract heat from both sides of the package. Important factors in the design include distributing the heat
Fig. 10. Efficiency and power handling improvement of DirectFET in a typical application with and without heatsink.
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Fig. 11. Thermal resistance of DirectFET topside and bottomside.
generation points across the package, making a low thermal impedance connection to the top of the die, and reducing the thermal resistance through the substrate itself.
6. Embedded motherboard applications These modules provide a flexible platform for single or multiphase power. They may include the full functionality of an integrated phase controller, or just be limited to the gate drive and power. Single, two-phase dual, or two-phase single output can easily be accommodated. A scalable architecture with a phase controller in each module and
Fig. 13. Comparison of discrete and integrated package.
a multiphase controller externally is also an attractive option for 100 A and higher. This technology is quite capable supporting the transient load conditions that are pushing the frequencies into the 1 – 2 MHz range per phase. The schematic drawings in Fig. 13 shows the concept of the simplification of layout and board design possible with the integrated package solution. Shown are the four-phase controller IC, the modules themselves, the inductors and the capacitors. The most striking thing about the solution is the performance of the total solution, as shown in Fig. 14.
7. Voltage regulator modules Many desktop computers manufacturers still prefer to supply the power to the processor through a plug in card called a VRM. This saves real estate on the motherboard, but has the disadvantage of adding height to the board and adding the interconnect resistance in the power path. This
Fig. 12. Integrated package (iPowIR) conceptual diagram.
Fig. 14. Efficiency of integrated and discrete package solutions.
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Fig. 15. Two sides of a VRM demonstration board for 100 A using DirectFET.
Fig. 18. IR1176 synchronous rectifier controller/driver in a secondary side application circuit within a forward converter.
Fig. 16. VRM efficiency and current capability with advanced FET components.
can degrade the transient response and overall regulation accuracy. The design in Fig. 15 is capable to deliver 100 A in less than 25 cm2 of board space. The top photo shows the eight power FETs in four phases on one side of the board, and the bottom photo shows the inductors, driver ICs and four-phase controller similar to the integrated package approach (Fig. 16). This level of output current is possible because of the DirectFET, and was accomplished by adding a heat sink to remove heat from the top of the packages. This is the only 25 A/phase solution that operates without paralleling FETs today. The heat sink for doing this is available in many configurations today and is becoming a more common element of the PC system designer’s solution set. The result
Fig. 17. Self-oscillating primary side circuit for isolated DC/DC converter.
in Fig. 18 shows an efficiency of greater than 86% at 100 A at 1.7 V output, and nearly 84% at 1.3 V out.
8. The isolated DC/DC converter Another class of DC/DC converter is the board mounted power module used in a wide variety of large electronic systems, such as telecommunications central switching networks, server and router installations, and the like. Typically these applications have 48 V input, frequently with a range of 36 –75 V. Some systems also have requirements in the 24 V supply range. Converters of this type have a greater variety of topologies. Single ended forward converters are quite prevalent, while half bridge and push– pull converters are also very common.
Fig. 19. A simple DC/DC converter with advanced FET MLP and DirectFET components.
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Fig. 20. Efficiency that can be achieved in a 48– 7.5 V isolated converter with advanced FETs.
Fig. 17 shows the primary side of a half bridge topology. In this case, the FETs are likely to be 100 V FETs to cover the high end of the 48 V rail, but may be as low as 80 V. The FET technology is again both planar and trench, with trench devices becoming more common in the application as the performance and cost structure improves. The illustrated IC is a simple self-oscillating gate-driver at 50% duty cycle for the sake of performance evaluation, but could also be a complete PWM controller. It should operate up to 500 kHz at least, and provide adjustable deadband and delay matching between the channels. The packages on the primary side FETs are typically SO8s, but for high power level may use Dpaks or D2paks to get better heat sinking capability. The main problem with the SO8s is the high thermal resistance they have to the board. In many of the BMP modules, the components are mounted on a better thermal conductor than a PCB, such as an insulated metal substrate (IMS). In such cases, a package which has a small footprint but better thermal coupling to the substrate is strongly desired. Fig. 18 shows an IC that is designed to drive synchronous rectifiers in an optimal way by deriving the drive signals from the transformer output waveform. In this way, no gate drive signals have to traverse the isolation boundary, and the problems inherit in self-driven synchronous rectifier schemes are avoided. These include noisy gate waveforms, overvoltage and asymmetric drive, non-optimum timing since the FET switching is delayed after the transformer is already transitioned. This IC has internal phase lock loop capability to synchronize with the transformer signal, and then advance the drive waveform as much as necessary to give the optimum deadband and minimize body diode conduction. This IC is designed to drive low Rdson MOSFETs very rapidly, and must have 1 – 2 A of drive current available to
do so. The FETs are typically 20 –30 V rated, occasionally higher, and other than Rdson the most common parameter of interest is the stored body diode charge Qrr and the gate charge Qg, which determine between the two the amount of energy lost/cycle and hence the optimum operating frequency. These FETs can be designed in a very similar way to the synchronous FETs in the buck converter topology. An example of a simplified DC/DC converter is pictured in Fig. 19. It illustrates the use of Microleadframe Packages (MLP) for the primary side FETs, which have exposed die attach pads on the bottom like the IC packages illustrated earlier to get the heat out while maintaining a very compact and efficient floorplan. On the secondary side, the use of directFET with Rdson as low as 2 mV is shown. The driver is the self-oscillating one described above. The demonstrated efficiency of the DC/DC converter in Fig. 20 is impressive at over 95% over the full range 50 to almost 200 W. The keys to achieving this result: effective gate drive, state of the art MOSFET technology and packaging technology, careful layout and magnetic design. It should be noted that some of the losses of a full converter may not be included, because this circuit is operating open loop to illustrate the capability of the components.
9. Conclusions Meeting the power conversion needs of today’s advanced electronic systems is quite a challenge, and promises to remain so for the foreseeable future. A combination of many electronic and mechanical disciplines is required, not to mention the fabrication challenges we all face as technologists in this field. It is
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not enough just to make power devices better, or to say the controller is the key to success. Analog IC capabilities must continue to improve, even as the technologies for generating new designs migrate from Bipolar to BCDMOS, BiCMOS, and from predominantly analog techniques to an increasingly digital control environment. Cost effective partitioning will also be key, with high performance multiphase architectures that address all the key issues that go along with that, such as phase timing, current sharing, lossless sensing, fault protection and diagnostic, optimized level shifting and gate drive nonoverlap timing. FETs are already pushing the fabs to 0.5 u capability and beyond. With trench devices going toward 1 u pitch, there is no question that the design and process integration engineers will remain challenged to push to reduce the FET losses even further. All the while, the packages have to improve so that they do not become the loss leaders, dissipating the majority of the energy and then bottling it up so that it cannot do anything but drive the FETs or the PCB into over temperature conditions. All the while, some of the truly remarkable advances in system efficiency will come from those who have a deep understanding and awareness of all the system and component issues, and are able to select the right technologies from the many available and combine them to achieve the best of all worlds.
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Acknowledgements I would like to recognize the assistance of my colleagues in the preparation of this material. These include Ritu Sodhi for the FET structures and performance, George Schuellein and Reza Amirani for the regulator and controller IC information, Andrew Sawle for the DirectFET packaging material, Goran Stojcic for the isolated DC/DC converter information, and Steve Brown for the integrated packaged solution data.
Dan Kinzer is currently Vice President of R&D for discrete products at International Rectifier. He has worked in the power semiconductor R&D for 24 years at International Rectifier. Among the devices he has been responsible for developing are HEXFET power MOSFETs, IGBTs, FREDs, high voltage and power ICs, and microelectronic relays. He has authored numerous papers in the field and has been granted approximately 30 patents in the fields of power electronic devices, IC technology, power electronic circuits, and packaging. Many of these form the basis for the manufacturing processes used today in the majority of IR products. He is currently serving on several technical committees related to IEEE conferences, including general chairperson for ISPSD’05, and is on the ADCOM subcommittee on Power Semiconductors. Mr Kinzer graduated from Princeton University with a BSE in Engineering Physics in 1978, before joining International Rectifer.
Advanced power semiconductors and ICs for DC/DC converter applications Dan Kinzer Research and Development, 233 Kansas St, International Rectifier, El Segundo, CA, USA
Abstract This paper describes recent advances in power semiconductor devices, integrated circuits, and packages for DC/DC converter applications. Special emphasis is placed on the latest discrete power MOSFET devices and packages. Features and trends in ICs for control of synchronous buck converters are highlighted as well. The paper will also cover a new class of miniaturized hybrid assembly that sets new efficiency standards for high current low output voltage applications. q 2003 Elsevier Ltd. All rights reserved. Keywords: Power MOSFET; DC/DC converter; Voltage regulator modules; Controller; PWM
1. Introduction One of the most exciting areas of power semiconductors and power electronics in general is the area of DC/DC converters. The rapid advancement in this field is driven by the ever-increasing current requirements of advanced VLSI circuits, especially microprocessors. The demands of this load include currents above 100 A, voltages approaching only 1 V and going lower, full load transient response approaching 100 ns, voltage regulation accuracy of 1% or less, efficiency above 90%, motherboard space consumption less than 20 cm2, and of course, cost that goes down every year even as the requirements get tougher. Achieving these goals requires a concerted effort in topology, control, drive, MOSFET, packaging and thermal design. The purpose of this paper is to illustrate some of those trends, discuss how some of those performance requirements are achieved, and indicate some directions for the future. Some examples will be chosen from embedded point of load, Voltage regulator modules (VRM) and isolated DC/DC converter designs.
2. Controllers and drivers The most pervasive topology for high performance DC/DC converters today is the synchronous buck
E-mail address: [email protected] (D. Kinzer). 0026-2692/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2692(03)00185-X
topology. This typically has a multiphase controller, which may range from 2 to 8 or even as much as 12 phases. Each phase drives two MOSFETs, which are optimised for high side and low side application. The high side switch controls the duty cycle and thus the output voltage, while the low side switch operates as a rectifier to keep inductor current flowing when the control FET is off. There are many ways to partition the phases, including single and dual phase controllers that synchronize themselves with other like ICs, master –slave configurations, and monolithic multiphase controllers. All of these may or may not include on-board gate drivers, depending on the capability of the process technology and the cost of full integration. In some case, at currents less than 10 A/phase, a single phase controller may integrate the gate drive as well as the MOSFETs themselves. An example of a representative three-phase PWM Controller with on-board MOSFET drivers which meets VRM 9.0 specification is shown in Fig. 1. It has a 5-Bit DAC for programming output voltage from 1.075 to 1.85 V in 25 mV steps and 1.0% output voltage accuracy over temperature. It employs a lossless average inductor current sensing technique and matches phase current with an internal transconductance amplifier (Fig. 2). Control is voltage mode, with programmable frequency from 50 to 500 kHz/phase. Other useful features include soft start, power good feedback, current limit using the synchronous FET Rdson to sense, overcurrent and overvoltage protection, and an easily implementable droop compensation circuit. This capability is required by Intel to
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Fig. 1. Schematic of a three-phase DC/DC converter.
keep the voltage in the right range under transient conditions. At full load, the power dissipation is somewhat reduced, while the voltage overshoot upon transition to light load is minimized. At light load, the voltage can be increased to get higher performance without excessive power consumption, and the undershoot going to full load is prevented. The specification and circuit performance are shown in Fig. 3. Some of the features that need to be incorporated into controllers in the future are scalability in the number of phases, a solution to the large amount of capacitance required in the circuit today, and the ability to climb up in frequency without excessive losses. There must be accurate current sharing, lossless sensing, and transient response on the order of one or two cycles. It must be accurate under all conditions, and of course take up a minimum of space. Examples of tiny Micro leadframe packages are given in Fig. 4. There is not a single answer today as to the appropriate process technology to implement these controllers. Many controllers still employ bipolar technology with minimum feature sizes above 1 mm. These technologies are quite suitable for analog and drive functionality, but may be limited in their ability to approach megahertz operation. Other controller areas implemented in full BCDMOS technologies, especially in circuits requiring higher input voltage capability, integrated MOS gate drive or full integration of the power transistor. Some such technologies have the ability to come close to the discrete MOSFET in performance figures of merit. System economics limits the output power of such circuits because the application cannot afford to use the high cost silicon in such complex technology for the power device. It is also difficult to obtain monolithic devices in the 10– 20 mV range and below because of the ohmic metal drops in the top surface drain and source connections, while discrete devices are
achieving resistances as low as 2 mV. Some companies are starting to offer more complete digital functionality in a controller, which allows more of the function to be implemented in standard CMOS technology with BiCMOS needed primarily for the I/Os. These technologies may employ CMOS and LDMOS structures using design rules extending down to 0.25 u.
3. Power MOSFETs The MOSFET is definitely the device of choice for DC/DC converter switch requirements today. It has a unique combination of ultralow conduction losses, low loss drive, high frequency capability, negligible storage time and robust SOA. There has been a tremendous amount of work on optimizing the MOSFET, and the main categories of device today are the planar DMOS vertical MOSFET, the trench vertical MOSFET and the lateral MOSFET. Today, large volumes of all types are performing the function,
Fig. 2. Lossless average inductor current sensing and phase matching.
D. Kinzer / Microelectronics Journal 35 (2004) 225–233
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Fig. 3. Droop compensation compared to Intel specification.
although lateral MOSFETs are primarily offered as part of integrated solutions and not as discrete devices. The trench MOSFET may appear to be a relative newcomer to the scene, but in fact V-groove and U-groove trench structures were fabricated as early as the 1970s. However, it really was not until the development of advanced plasma etch techniques in the early to mid-90s that a suitable quality structure could be attained. Even today, the device brings substantial challenges in the area of process control, cleanliness, geometric tolerancing, trench filling, corner rounding and high quality gate oxidation. For some manufacturers, these issues have been mastered to the extent that high volume production is now common. The challenge that remains is to design the devices in such a way that they perform with maximum efficiency in today’s applications.
Fig. 4. Microleadframe packaging for IC controllers.
Fig. 5. Schematic drawing of state of the art trench FET.
The trench device in Fig. 5 (not to scale) shows some of the attributes of the device. The channel is arranged on the trench sidewall, while the gate electrode consists typically of the polysilicon that is used to fill the trench. High packing density is achieved by the vertical channel orientation, and by the relatively unrestricted current flow path form the channel through the epi layer to the underlying substrate material. As illustrated, it is preferred if the trench bottom oxide is thicker than the sidewall oxide in order to minimize the gate to drain overlap capacitance. By the same token, it is also beneficial to reduce the trench width, provided that the small radius of curvature does not cause current crowding and high electric field stress at the trench bottom. The P-base region defined the channel length, which of course is preferably as short as possible to lower both its resistance and the gate-source overlap capacitance. The source metallization must come in contact with the source and the base in a very low resistance fashion to ensure low resistance as well as keep the parasitic NPN bipolar inherent in the structure from turning on. A state of the art device may have a pitch as shown in the range of 2.4 u as has also been reported. The selection of the pitch is driven by application, depending on whether the device is to be optimized for highest packing density and therefore lowest conduction loss, or for low gate charge to achieve high speed and low switching loss. For low conduction loss, the normal figure of merit for the transistor is the Rdson X Area product, which determines the current density capability of the device. For high frequency
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Fig. 6. Forecasted trend in 30 V silicon FET Rdson.
operation, the switching charge Qswitch is defined which adds the amount of charge Cgs must receive to switch the current to the amount of charge Cgd must receive to slew the voltage. This charge is approximately proportional to chip area and inversely proportional to Rdson, which leads to the technology independent figure of merit Rdson X Qswitch. The expected trends in these figures of merit for 30 V rated silicon MOSFETs are shown in Figs. 6 and 7. It is worth noting on these charts that the planar DMOS performance shown in 2001, while the trench MOSFET of today is leading the roadmap to achieve this years levels. Recently, some data presented at ISPSD has indicated that lateral devices can come close to achieving the levels indicated for 2003 in the charge for Rdson X area, although those devices had breakdown voltage of only 15 V and were limited to small active area test structures where metal series resistance is only a small factor. The switching figure of merit Rdson X Qswitch is the characteristic where lateral devices are expected to perform competitively at low enough voltage and current. Another point to consider is the apparent saturation of the silicon roadmap in Rdson X Area, with a slowing rate of improvement. This means that all the relatively easy to tackle source of parasitic resistance such as substrate, contact, and top metal resistance have been substantially eliminated. The limitation appears to be due in part to
Fig. 7. Forecasted trend in 30 V silicon FET switching figure of merit.
the required channel length to withstand the rated 30 V without punchthrough, and the feasible packing density of the trenches. The second limitation is the ‘theoretical silicon limit’, which is determined from the minimum resistivity and thickness of the drain drift region required to withstand the voltage, assuming a uniform vertical current conduction within that region. The smaller the pitch and the spacing between trenches, the closer the device may approach that ideal limit. In order to break those limits, a new technology will need to be introduced. One must consider either the use of field contouring or charge balancing techniques to be able to enhance blocking voltage beyond the theoretical 1D planar junction limit, or one must consider the use of alternate high mobility or high critical field materials such as GaAs and GaN.
4. Discrete packaging Packaging for power MOSFETs must meet some important criteria. The package should add minimum electrical resistance to the device, considering that some MOSFET chips are now measured in microohms instead of milliohms. It should also have a very low thermal resistance to get the heat out, and an ability to channel that heat to the place where it is most effectively removed from the system. It should also be very low inductance, and of course low cost, robust, and friendly to the environment. Pictured in Fig. 8 are some widely used packages and a new package concept called the DirectFET. The SO8 is most common. It is 1.7 mm tall, and current must flow through a large number of typically 50 u gold wire bonds in parallel. The bonds are usually constrained to remain near the die edge, which results in a fairly large resistance in the wires as well as the die top metallization. Most of the heat must exit the package through the drain leads into the board the device is mounted on and from there to the ambient. The copper strap SO8 helps the situation by replacing the gold wires with the strap, which effectively shunts the top metal and wire resistance. This also creates a thermal path to
Fig. 8. Comparison of surface mount FET packages.
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and the losses in the package resistance are mostly eliminated. When a heat sink and forced air are applied, the current out of the same footprint is nearly doubled. This is only possible with a package that allows top side heat sink attachment. Fig. 11 shows the important point that even with nearzero thermal impedance to the printed circuit board, most applications use relatively small footprint trace and thus cannot remove much heat. That is why a low thermal resistance path away form the board is such a big advantage. In motherboards, it is preferred to keep heat away form the board, as there is already a heat overload from the microprocessor.
5. Integrated package solutions
Fig. 9. Package resistance of various common packages.
the source leads, allowing heat to exit both sides and lowering the thermal resistance into and through the board. The new DirectFET lowers the package profile to less than half, and places the junction directly in contact to the board through the same solder process used to mount other surface mount components. This effectively eliminates almost all the die free package resistance, and opens up a new cooling path through the top of the package that was not there before. A comparison to other package is shown in Fig. 9. The graph in Fig. 10 shows the improvement in efficiency and power handling capability gained through the new packaging. The efficiency is improved by 3% at 19 A, largely because the junction temperature is cooler
Excellent gains are possible in system efficiency and ease of use through a combination of the kinds of control, power semiconductor and packaging technologies discussed so far, as shown in Fig. 12. One of the advantages of integration is close coupling of controller and MOSFET to eliminate layout parasitics. Another is the close coupling of the Schottky diode and synchronous FET that are paralleled to make sure the body diode of the FET conducts as little as possible during the deadband period when both FETs are off. Yet another is due to the inclusion of debiasing capacitance on the input to eliminate ground noise and allow for clean signals to come from the controller or driver to the MOSFET gates. Other improvements come from the package thermal design. This is driven by the die to substrate thermal impedance, connection to the underlying board, and the ability to extract heat from both sides of the package. Important factors in the design include distributing the heat
Fig. 10. Efficiency and power handling improvement of DirectFET in a typical application with and without heatsink.
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Fig. 11. Thermal resistance of DirectFET topside and bottomside.
generation points across the package, making a low thermal impedance connection to the top of the die, and reducing the thermal resistance through the substrate itself.
6. Embedded motherboard applications These modules provide a flexible platform for single or multiphase power. They may include the full functionality of an integrated phase controller, or just be limited to the gate drive and power. Single, two-phase dual, or two-phase single output can easily be accommodated. A scalable architecture with a phase controller in each module and
Fig. 13. Comparison of discrete and integrated package.
a multiphase controller externally is also an attractive option for 100 A and higher. This technology is quite capable supporting the transient load conditions that are pushing the frequencies into the 1 – 2 MHz range per phase. The schematic drawings in Fig. 13 shows the concept of the simplification of layout and board design possible with the integrated package solution. Shown are the four-phase controller IC, the modules themselves, the inductors and the capacitors. The most striking thing about the solution is the performance of the total solution, as shown in Fig. 14.
7. Voltage regulator modules Many desktop computers manufacturers still prefer to supply the power to the processor through a plug in card called a VRM. This saves real estate on the motherboard, but has the disadvantage of adding height to the board and adding the interconnect resistance in the power path. This
Fig. 12. Integrated package (iPowIR) conceptual diagram.
Fig. 14. Efficiency of integrated and discrete package solutions.
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Fig. 15. Two sides of a VRM demonstration board for 100 A using DirectFET.
Fig. 18. IR1176 synchronous rectifier controller/driver in a secondary side application circuit within a forward converter.
Fig. 16. VRM efficiency and current capability with advanced FET components.
can degrade the transient response and overall regulation accuracy. The design in Fig. 15 is capable to deliver 100 A in less than 25 cm2 of board space. The top photo shows the eight power FETs in four phases on one side of the board, and the bottom photo shows the inductors, driver ICs and four-phase controller similar to the integrated package approach (Fig. 16). This level of output current is possible because of the DirectFET, and was accomplished by adding a heat sink to remove heat from the top of the packages. This is the only 25 A/phase solution that operates without paralleling FETs today. The heat sink for doing this is available in many configurations today and is becoming a more common element of the PC system designer’s solution set. The result
Fig. 17. Self-oscillating primary side circuit for isolated DC/DC converter.
in Fig. 18 shows an efficiency of greater than 86% at 100 A at 1.7 V output, and nearly 84% at 1.3 V out.
8. The isolated DC/DC converter Another class of DC/DC converter is the board mounted power module used in a wide variety of large electronic systems, such as telecommunications central switching networks, server and router installations, and the like. Typically these applications have 48 V input, frequently with a range of 36 –75 V. Some systems also have requirements in the 24 V supply range. Converters of this type have a greater variety of topologies. Single ended forward converters are quite prevalent, while half bridge and push– pull converters are also very common.
Fig. 19. A simple DC/DC converter with advanced FET MLP and DirectFET components.
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Fig. 20. Efficiency that can be achieved in a 48– 7.5 V isolated converter with advanced FETs.
Fig. 17 shows the primary side of a half bridge topology. In this case, the FETs are likely to be 100 V FETs to cover the high end of the 48 V rail, but may be as low as 80 V. The FET technology is again both planar and trench, with trench devices becoming more common in the application as the performance and cost structure improves. The illustrated IC is a simple self-oscillating gate-driver at 50% duty cycle for the sake of performance evaluation, but could also be a complete PWM controller. It should operate up to 500 kHz at least, and provide adjustable deadband and delay matching between the channels. The packages on the primary side FETs are typically SO8s, but for high power level may use Dpaks or D2paks to get better heat sinking capability. The main problem with the SO8s is the high thermal resistance they have to the board. In many of the BMP modules, the components are mounted on a better thermal conductor than a PCB, such as an insulated metal substrate (IMS). In such cases, a package which has a small footprint but better thermal coupling to the substrate is strongly desired. Fig. 18 shows an IC that is designed to drive synchronous rectifiers in an optimal way by deriving the drive signals from the transformer output waveform. In this way, no gate drive signals have to traverse the isolation boundary, and the problems inherit in self-driven synchronous rectifier schemes are avoided. These include noisy gate waveforms, overvoltage and asymmetric drive, non-optimum timing since the FET switching is delayed after the transformer is already transitioned. This IC has internal phase lock loop capability to synchronize with the transformer signal, and then advance the drive waveform as much as necessary to give the optimum deadband and minimize body diode conduction. This IC is designed to drive low Rdson MOSFETs very rapidly, and must have 1 – 2 A of drive current available to
do so. The FETs are typically 20 –30 V rated, occasionally higher, and other than Rdson the most common parameter of interest is the stored body diode charge Qrr and the gate charge Qg, which determine between the two the amount of energy lost/cycle and hence the optimum operating frequency. These FETs can be designed in a very similar way to the synchronous FETs in the buck converter topology. An example of a simplified DC/DC converter is pictured in Fig. 19. It illustrates the use of Microleadframe Packages (MLP) for the primary side FETs, which have exposed die attach pads on the bottom like the IC packages illustrated earlier to get the heat out while maintaining a very compact and efficient floorplan. On the secondary side, the use of directFET with Rdson as low as 2 mV is shown. The driver is the self-oscillating one described above. The demonstrated efficiency of the DC/DC converter in Fig. 20 is impressive at over 95% over the full range 50 to almost 200 W. The keys to achieving this result: effective gate drive, state of the art MOSFET technology and packaging technology, careful layout and magnetic design. It should be noted that some of the losses of a full converter may not be included, because this circuit is operating open loop to illustrate the capability of the components.
9. Conclusions Meeting the power conversion needs of today’s advanced electronic systems is quite a challenge, and promises to remain so for the foreseeable future. A combination of many electronic and mechanical disciplines is required, not to mention the fabrication challenges we all face as technologists in this field. It is
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not enough just to make power devices better, or to say the controller is the key to success. Analog IC capabilities must continue to improve, even as the technologies for generating new designs migrate from Bipolar to BCDMOS, BiCMOS, and from predominantly analog techniques to an increasingly digital control environment. Cost effective partitioning will also be key, with high performance multiphase architectures that address all the key issues that go along with that, such as phase timing, current sharing, lossless sensing, fault protection and diagnostic, optimized level shifting and gate drive nonoverlap timing. FETs are already pushing the fabs to 0.5 u capability and beyond. With trench devices going toward 1 u pitch, there is no question that the design and process integration engineers will remain challenged to push to reduce the FET losses even further. All the while, the packages have to improve so that they do not become the loss leaders, dissipating the majority of the energy and then bottling it up so that it cannot do anything but drive the FETs or the PCB into over temperature conditions. All the while, some of the truly remarkable advances in system efficiency will come from those who have a deep understanding and awareness of all the system and component issues, and are able to select the right technologies from the many available and combine them to achieve the best of all worlds.
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Acknowledgements I would like to recognize the assistance of my colleagues in the preparation of this material. These include Ritu Sodhi for the FET structures and performance, George Schuellein and Reza Amirani for the regulator and controller IC information, Andrew Sawle for the DirectFET packaging material, Goran Stojcic for the isolated DC/DC converter information, and Steve Brown for the integrated packaged solution data.
Dan Kinzer is currently Vice President of R&D for discrete products at International Rectifier. He has worked in the power semiconductor R&D for 24 years at International Rectifier. Among the devices he has been responsible for developing are HEXFET power MOSFETs, IGBTs, FREDs, high voltage and power ICs, and microelectronic relays. He has authored numerous papers in the field and has been granted approximately 30 patents in the fields of power electronic devices, IC technology, power electronic circuits, and packaging. Many of these form the basis for the manufacturing processes used today in the majority of IR products. He is currently serving on several technical committees related to IEEE conferences, including general chairperson for ISPSD’05, and is on the ADCOM subcommittee on Power Semiconductors. Mr Kinzer graduated from Princeton University with a BSE in Engineering Physics in 1978, before joining International Rectifer.