Advanced time-stamped total data acquisition control front-end for MeV ion beam microscopy and proton beam writing

Microelectronic Engineering 102 (2013) 9–11

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Advanced time-stamped total data acquisition control front-end for MeV ion beam microscopy and proton beam writing Henri Kivistö a,⇑, Mikko Rossi a, Pete Jones a, Rattanaporn Norarat a, Nitipon Puttaraksa a, Timo Sajavaara a, Mikko Laitinen a, Väinö Hänninen a, Kimmo Ranttila a, Pauli Heikkinen a, Leona Gilbert b, Varpu Marjomäki b, Harry J. Whitlow a,1 a b

Department of Physics, University of Jyväskylä, P.O. Box 35 (YFL), FIN-40014 Jyväskylä, Finland Department of Environmental and Biological Sciences, University of Jyväskylä, P.O. Box 35 (YA), FIN-40014 Jyväskylä, Finland

a r t i c l e

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Article history: Available online 29 March 2012 Keywords: Front-end Microbeam FPGA Data acquisition Time-stamping

a b s t r a c t Many ion–matter interactions exhibit sub-ls time dependences such as, fluorophore emission quenching and ion beam induced charge (IBIC). Conventional event-mode MeV ion microbeam data acquisition systems discard the time information. Here we describe a fast time-stamping data acquisition front-end based on the concurrent processing capabilities of a Field Programmable Gate Array (FPGA). The system is intended for MeV ion microscopy and MeV ion beam lithography. The speed of the system (>240,000 events s 1 for four analogue to digital converters (ADC)) is limited by the ADC throughput and data handling speed of the host computer. Ó 2012 Elsevier B.V. All rights reserved.

1. Introduction The evolution in computer, data acquisition and control technology continuously offers new and enhanced possibilities for new types of measurements and approaches. MeV ion microbeams are attracting increasing interest for advanced microscopy and materials modification, such as MeV ion beam lithography which can benefit from these advances. In conventional MeV ion microbeam data acquisition (DAQ) systems, a control system or computer generates signals that control the x, y beam position and beam blanker. The pulse amplitude and time information are digitised and synchronously assembled into multiplets for each single event. The multiplet event records are then stored and/or histogrammed by the computer. This process is slow because it requires many steps to be carried out sequentially and synchronously [1]. The most serious objection is that time information, which can be physically relevant is discarded. In contrast, high-speed asynchronous time-stamped data collection can be realised using concurrent processing. In this mode each free-running input and output signal is time-stamped and the conversion value is stored asynchronously with its time-stamp in a data queue. This is inherently faster than using time-tagged multiplets [2]. FPGAs are well suited to this task because they ⇑ Corresponding author. E-mail address: [email protected].fi (H. Kivistö). Present Address: Institut des Microtechnologies Appliqées Arc, Haute Ècole Arc Ingénierie, Eplatures-Grise 17, CH-2300 la Chaux-de-Fonds, Switzerland. 1

0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2012.02.011

inherently process data concurrently and may run autonomously of the host processor [1]. In this case the clock frequency of the FPGA governs the time resolution, which can be on a scale of 10 ns. Autonomous operation using Direct Memory Access (DMA) or buffers [3] to handle host-side data queues overcomes operating-system associated latencies. The asynchronous time-stamping approach has been used successfully in Jyväskylä for collecting data from fundamental nuclear physics experiments and Time of Flight Elastic Recoil Detection Analysis (ToF-ERDA) [4]. Time-stamped DAQ opens up many microscopic time domain processes for study using MeV ion microbeams. This is because unlike conventional fast-DAQ the time information is inherently stored with each channel. The off-line triggering thereby allows complex time, position and amplitude relationships to be measured. Examples are; spatially and temporally resolved IBIC studies of charged particle induced breakdown in semiconductors and bleaching of fluorophores and degradation of materials. For study at the single ion detection level (e.g. Direct STIM) at a typical beam current of 1 pfA, the single channel count rate is 6300 s 1. A modest pile-up factor of <0.5% requires a time resolution of 50 ns, or better. Here we report on development of a truly-asynchronous time stamping FPGA DAQ front-end (DAQ-FE) for the DREAM MeV ion microbeam project for MeV ion beam lithography and microscopic imaging. The DAQ-FE system is based around a single commercial PXI FPGA interface card that handles standard nuclear instrumentation module (NIM) pulse height ADCs and generates the scan and beam blanking signals. The interface is programmed using LabVIEW to ensure compatibility and upgradeability.

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H. Kivistö et al. / Microelectronic Engineering 102 (2013) 9–11

2. Experimental configuration The reported data acquisition system is being developed for the DREAM microbeam project in Jyväskylä. This new microbeam system will be initially based on a quadrupole doublet for focussing with electrostatic beam-blanking and post-lens electrostatic deflection. Requirements for such a system include one fast TTL digital output (beam-blank) and two analogue outputs (scanning deflection) from the DAQ-FE for operation of the system. The data from the detectors is digitised by 12-bit Daresbury laboratory’s EC643 4K pulse height spectroscopy ADCs. ADCs each take up to 17 digital input/output lines (DIO) for communication and data transfer. Four such ADCs are interfaced directly to the TTL DIO lines via purpose-built interface boxes. As in the case of the IonDAQ system [1] the use of a single FPGA card makes the system compact as seen in Fig. 1. In addition provision is made to control the lens current power supplies from the spare digital to analogue converters (DACs) to allow auto-focussing of the beam [5,6].

3. FPGA based DAQ front-end For realising the DAQ-FE, a National Instruments (NI) PXI-7841R FPGA module was selected. This is closely similar to the PXI-7811R module which was previously used in Jyväskylä for time-stamped DAQ in ToF-ERDA with good results. The NI PXI-7841R module is based on a Virtex-5 LX30 FPGA which holds 19,200 macro cells, which is sufficient to hold the whole DAQ-FE system on one FPGA with a broad margin. There are also 32 48-bit digital signal processing slices (DSP48E) that can be configured as fast cumulative counters with pre-set stop and reset signals that can be used to control scanning using pre-set charge or time values. The software for the FPGA-based DAQ-FE was developed using NI LabVIEW. This was chosen as a development environment because it facilitates fast development and maintenance without the overhead associated with using a conventional programming language. The Ni PXI-7841R FPGA module has eight 16-bit DACs with ±10 V output swing, two of which will be used to control the deflection of the beam. 96 bidirectional TTL digital input/output lines are used for interfacing four ADCs (extendable to five), inputs of optional fast timing triggers and TTL compatible DIO for four counter inputs and control of the beam blanker. The FPGA module has a 40 MHz internal clock that synchronises the processing steps in the FPGA and is used to update the master time clock used for time-stamping in 25 ns steps. (This can be reduced to 12.5 ns with

Fig. 1. DAQ-system for the DREAM MeV ion microbeam project. The four ADC’s are in the NIM crate with the interface boxes are on top. The DAQ-FE is implemented on a module in the PXI crate. Analogue interfaces are in the shielded module on top of the PXI crate. The PC is not shown in this view.

overclocking.) The module sits in a NI PXI-1033 chassis, (Fig. 1) with 10 MHz system reference clock and 110 MB s 1 data transfer rate to a host computer. The system reference clock does not influence the FPGA clock during data transfer to the host. The data transfer is carried out using first-in first-out (FIFO) DMA communication lines. In time-stamped DAQ every event is gathered, labelled and stored with a time-stamp into a event-list file. For simplicity all events in our DAQ-FE are treated identically. An event can be a signal in an ADC or a change in blanker status, change in deflection voltage, counter pre-set reached or other fast trigger signal. The FPGA is not confined by von Neumann architecture which gives the FPGA the ability to handle each process concurrently and enables each process to be performed completely asynchronously. Non-deterministic dataflow in FPGA gives the DAQ more processing power compared to microcontroller based systems. Each event is stored on an as it happened basis and the only thing linking events is their time-stamp. The major advantage with time-stamping DAQ is that there is no need for complex hardware triggering and that no slow assembly of event data is needed [1]. These functions are performed on-line by a host processor, or by off-line post processing, of the time-stamped data. Other advantage of this approach is that time information is registered with high resolution (25, or 12.5 ns) and that one can optimise different timing and amplitude gate conditions off-line without the need to re-measure the data. The dataflow in the DAQ-FE is shown in Fig. 2(a). All the blocks in this figure work asynchronously. The ADCs can be read at the same time as the previous data is being transferred and new scanning pattern data can be loaded and executed without delays. The only part where some synchronisation is needed is access through the shared FIFO resources (Fig. 2(a)). A ‘‘fair round robin’’ procedure is used for queueing to allow different function blocks to transfer data to the host computer by DMA where they are transferred to a hard disc. Every event is transferred to the host as two 64-bit elements where the first one holds the 64 bit time stamp and the second one consists of data related to the event. The first 8 bits of data are reserved for event identification such as ADC number, blanker on/off status or X-, Y-deflection change. The next 8 bits are reserved for later needs. The next 16 bits carry ADC conversion values, deflection values or beam blanker status. The last 32 bits are used to transfer counter values. The ADC readout function block, (Fig. 2(a)) at the start of the readout cycle checks to see if the data ready line is already low (data waiting), if so the data from that channel is discarded as bad-time-stamp. This corresponds to a rare pile-up event when the DAQ-FE is overloaded and the event time cannot be resolved. Otherwise, it waits for falling edge on the data ready line, timestamps the event and then requests the ADC data which is loaded to a register to be transferred through the FIFO link. A new cycle can start as soon as the data is put into the register. However, if the registered has not been cleared, the readout process will wait for a signal from the FIFO indicating that the data has been read, before writing new data to the register. A separate 64 bit FIFO channel is used to transmit scanning and beam-blanking data to the FPGA in a similar manner to the Ionscan program [7]. The scanning procedure will start once the first element is received by the FPGA while the rest of the scanning data is loaded dynamically to fill up the RAM. The beam blanker is switched for every pixel after an initial variable delay. The delay can correspond to pre-set times, charge accumulation or a counter value. The 32-bit counter data and x, y 16-bit scan amplitudes represent one record in the scanning file (or RAM address). These are sent through the 64-bit FIFO channel from the host processor to the FPGA. (Fig. 2(a)).

H. Kivistö et al. / Microelectronic Engineering 102 (2013) 9–11

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Fig. 2. Schematic showing dataflow on the FPGA (a) and host (b) side on the DAQ system. Table 1 Summary of the DAQ system performance and features. NIM ADCs Number of ADCs ADC resolution

4 (max 5) 13 bit (max by DIO)

Scanning DAC resolution Scanning voltage Stopping preset

16 bit ±10 V Charge or time (1 ls interval)

Data Data Data Data

2 64 bit data elements (64:8:8:16:32) FIFO DMA 110 MB s 1 >240 kHz for whole system

processing and transfer type transfer throughput

Other features TTL counters Time resolution

run concurrently on separate processor cores perform writing of data to the hard disk and data queue, sorting and histogramming, scanning and positioning. These are controlled by a GUI thread which also performs histogram rendering in 1D and 2D. Motorised positioners for the sample stage and programmable proximity aperture lithography [8,9] are controlled by USB-RS-232 interfaces (Fig. 2(b)). 5. Conclusions

Fast DSP48E counters (3 channels) 25 ns (12.5 ns over-clocked)

Some FPGA parameters as ADC on/off status, handshake communication delay and counter reset are also controlled by the host processor. These parameters are directly modified on the FPGA through a bus interface by determining a bit address, process and data bits. The data handling is fast because neither sorting nor histogramming is carried out on the FPGA. The theoretical maximum data transfer rate to the host is over 6  106 events s 1 for a 110 MB s 1 transfer rate link to the host PC. The FPGA implementation could in theory handle almost 1 M events s 1. In practice one ADC has a dead time of 6.8 ls limiting the collection speed to 147 kHz per channel. Minimum program clock cycle for the host computer used in testing was 15 ls. If the minimum of two elements are gathered during one cycle the speed limit is 67 kHz. Using an algorithm that modulates the number of elements to write on hard disk according to elements waiting in the DMA memory section, the data throughput was observed to be more than 240 kHz without any data drops using two ADCs. A summary of the DAQ system specifications can be found in Table 1.

A FPGA-based time-stamping DAQ-FE for MeV ion microscopy and MeV ion beam lithography has been developed. The highspeed afforded by the concurrent processing achievable by FPGA allows data to be collected so that time and dose effects at the individual ion level can be measured. The time-stamping DAQ-FE is truly asynchronous with a time resolution corresponding to the FPGA clock of 25 ns. The throughput is limited by the ADC dead time and data transfer in the host processor. Acknowledgement This work was supported the Academy of Finland, Centre of Excellence in Nuclear and Accelerator Based Physics, Ref. 213503 and Grant No. 129999. References [1] [2] [3] [4]

[5] [6] [7] [8]

4. Host-side processing The DAQ-FE works with a host computer. Fig. 2(b) illustrates the data-flow in the DAQ system. Different program threads, that

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