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All-digital thermal distribution measurement on field programmable gate array using ring oscillators
Microelectronics Reliability xxx (2014) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
All-digital thermal distribution measurement on field programmable gate array using ring oscillators Yuan Yue a, Feng Shi-Wei a,⇑, Guo Chun-Sheng a, Yan Xin a, Feng Rui-Rui b a b
School of Electronic Information & Control Engineering, Beijing University of Technology, Beijing 100124, China College of Physical Science and Technology, Sichuan University, Sichuan 610207, China
a r t i c l e
i n f o
Article history: Received 17 March 2014 Received in revised form 29 September 2014 Accepted 12 October 2014 Available online xxxx Keywords: Field programmable gate array (FPGA) Thermal sensor Temperature distribution Transient Oscillator
a b s t r a c t In this paper, a digital method for transient temperature distribution measurement of field programmable gate array (FPGA)-based systems is proposed. The smart thermal sensors used rely on correspondence between the delay and temperature in a ring oscillator. The tested temperature was converted into a time signal with a thermally-sensitive width. The output frequency is read out by a counter with a scan path, and then, transited to PC by a Universal Serial Bus (USB) interface. We capture the infrared images of the FPGA chip by infrared camera. The images were compared with the thermal map of the die constructed using an array of sensors. The tested temperature error varies by less than 1.6 °C in the range from 20 °C to 90 °C, and the maximum sampling rate is 330 Hz. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Field programmable gate array (FPGA)-based system device structures are shrinking while their device densities are increasing, meaning that thermal management is gaining increasing importance in these structures [1]. High temperature affects the performance of circuits, which can lead to timing errors and reduced reliability [2]. While methods are available to gather the thermal information, like embedded diodes available in FPGAs or use of infrared imagers [3,4], these methods are not suitable for use in that embedded diodes can get the temperature at points in the die, and infrared imagers are rarely used for their expensive and destructive causes. Therefore, the smart thermal sensor has been proposed, which can enable measurement of the junction temperature distribution rather than single position temperature of the package. Numerous ring oscillator-based thermal sensors have been described in the literature previously [5–8], but the detailed studies have been rarely performed to date. Datta and Burleson [13] proposed use of differential ring oscillators (DRO) for thermal sensing, but its sensing design depended on full-custom which made it hard to adapt to process variation. The differential ring oscillators are fixed in a certain position of the die. In [5] the authors proposed temperature sensors based on ROs. The system
⇑ Corresponding author. E-mail address: [email protected] (S.-W. Feng).
calibrated them using an internal precalibrated thermal diode on a Virtex-6 FPGA. In this paper, an array of sensors is used to construct a thermal map of the die to measure its temperature distribution and to predict the transient thermal behavior of the FPGA-based system. The sensors are fully digital and constructed by pure standard cell-based design that can be dynamically inserted and eliminated at any position of the die. The proposed all-digital thermal sensor can be used to get transient thermal distribution of the die. We also captured the infrared images of the package for comparison with the measured results of the sensors in order to calibrate the thermal sensor and to improve the accuracy by evaluating the influence of the number of inverters. 2. Smart thermal sensor The smart thermal sensor consists of a thermally sensitive ring oscillator, which is a circular chain with an odd number of inverters, as shown in Fig. 1. The oscillation period is twice the sum of the delays, and is given as [9]:
f out ¼
1 2N T d
ð1Þ
where N is the number of inverters resident in the ring oscillator, and Td is the average propagation delay. By neglecting the effects of velocity saturation, channel length modulation and other nonidealities for simplicity, the propagation delay under the first-order approximation can then be given as [10]:
http://dx.doi.org/10.1016/j.microrel.2014.10.010 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
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Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
fout
enable
Fig. 1. Schematic of the ring oscillator.
Td ¼
ðL=WÞC L 1:5V DD 2V T ln lC ox ðV DD V T Þ 0:5V DD
ð2Þ
The length/width ratio L/W, the gate oxide capacitance Cox and the effective load capacitance CL are independent of the temperature, while the thermal characteristics of the mobility l and the threshold voltage VT change with temperature, and can be derived as follows [11]:
l ¼ l0
T T0
km
Fig. 3. Sensor output frequency dependence on temperature.
ð3Þ
V T ðTÞ ¼ V T ðT 0 Þ þ aðT T 0 Þ
ð4Þ
In the majority of designs, the supply voltage is chosen to be high enough that VDD VT. Under these conditions, the delay becomes virtually independent of the supply voltage, and the electron mobility plays the main role in thermal effects of the propagation delay. The threshold voltages of transistors for Altera FPGA are 100 mV, the supply voltage is 3.3 V which is much greater than the threshold voltage. Because of the negative temperature coefficient of the surface carrier mobility for electrons, the propagation delay Td has a positive temperature coefficient. This means that as the temperature increases, then the output frequency of the ring oscillator decreases. The block diagram of the smart thermal sensor is depicted in Fig. 2. The thermal sensor converts temperature into time information being fed into a time-to-digital converter according to a reference clock for digital coding. The ring oscillator translates the tested temperature into a pulse with a temperature-proportional width. A counter with a scan path captures the frequency over a fixed pulse to produce the digital output which is transmitted to the computer through the Universal Serial Bus (USB) interface. The fixed period is provided by the system clock, and it is useful to increase the wiring delays and thus reduce the operating frequency of the ring oscillator; in this case, the goal is to make the operating frequency lower than that of the system clock to minimize self-heating [11].
Fig. 4. Sensor output frequency dependence on power supply voltage.
3. FPGA implementation An Altera Cyclone III series FPGA chip is used for circuit realization to verify the proposed thermal sensor. A ring oscillator is constructed using inverters, which can be mapped on the FPGA using the look-up tables (LUT); the logic utilization for such a sensor is as low as 21 logic elements (LE). A delay line can be built among the
Counter Digital output
PRE D Add0 A[25..0] 00001 --
B[25..0]
counter~[25..0]
26' h0000000 --
LessThan0 CIN
SEL DATAA
+
UART
Q
DATAB
counter[25..0]
1
A[25..0] 26' h2FAF080 --
PRE OUT0
D
B[25..0]
<
Q
ENA
Fixed pulse
CLR
LESSTHAN
ADDER
ENA MUX21
CLR
PC
CLK
Fig. 2. Block diagram of the thermal sensor.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
3
(a) The floorplan of the Nios II/e processor.
36.3
(b) The thermal map of the Nios II/e processor.
(c) The infrared image of the Nios II/e processor. Fig. 5. The experimental results for the Nios II/e processor.
inverters to reduce the operating frequency of the ring oscillator. Synthesis optimization should be prohibited during logic complication to prevent the synthesis of the delay line [12]. The power consumption of the thermal sensor is measured to be 750 nW. An array of 4 6 sensors was placed in the FPGA to measure the die temperature distribution. It is important to use the logic lock technology to fix the positions of the 24 sensors on the FPGA and to ensure their positions unchanged when embedded in different programs; the yellow boxes showing the locations of
the thermal sensors are depicted in Fig. 3. The FPGA was configured with all of the thermal sensors, but takes turns in opening these sensors for frequency measurements to reduce the effects of self-heating [11]. Each thermal sensor need to be calibrated before use. We put the configured FPGA board in a temperature-controlled oven, and used a long ribbon cable to transmit out the signals to the computer outside [12]. The measured calibration curves between temperatures and output frequency of the 24 sensors are shown
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
4
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
(a) The floorplan of the Nios II/f processor.
Fig. 7. Sensor output frequency of different chips.
39.2
(b) The thermal map of the Nios II/f processor.
Fig. 8. The measurement error map between the sensor and thermal imager.
(c) The infrared image of the Nios II/f processor. Fig. 6. The experimental results for the Nios II/f processor.
in Fig. 3. They exhibited a perfect linear dependence on temperature, with a coefficient of 95 kHz/°C. Fig. 4 shows the output frequency depends on power supply variations. They exhibited a perfect linear dependence with a coefficient of 1.03 kHz/mV. Figs. 3 and 4 show that the variation of frequency with temperature is much larger than that with the power supply voltage. It could be inferred that large increments of the temperature can’t be covered by tiny power supply variations. The supply voltage is 3.3 V all the time. So the tiny variation of power supply influence is negligible.
Fig. 9. Output frequency dependence on temperature for different numbers of inverters.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
5
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx Table 1 Measurement errors, resolution and power consumption vary with the number of inverters. The number of inverters Frequency (MHz) Resolution (°C) Error (°C) Power (lW)
9 175.87 0.0435 0.6–0.7 1.358
15 137.87 0.0695 0.5–0.6 1.0651
17 120.89 0.0828 0.8–1.1 0.933
The FPGA is a programmable logic device. Running different programs maybe cause different hot spots or temperature gradients. We evaluated the smart thermal sensors by embedding two different configurations of the Nios II processor within the FPGA: the Nios II/e with 600–700 logic elements and the Nios II/f with 1400–1800 logic elements. The overall power consumption of the program is about 240 mW, the additional power consumption caused by the thermal sensor is much less than the overall power consumption. We used logic lock to constrain the logic blocks of the Nios II/e processor to fit into a 17 12 array of the layout, as depicted in Fig. 5a, and used a 19 17 array of logic blocks for the Nios II/f processor, as shown in Fig. 6a. For comparison, we implement the same program on a Xilinx Spartan-3E FPGA, a Altera Cyclone II FPGA and a Altera Cyclone III FPGA respectively. Fig. 7 illustrates the output frequencies versus die temperature on the three FPGA chips. Ring-oscillators in the chips exhibit a linear response in operation temperature range. The resolutions of the temperature sensors implemented on ‘‘Xilinx Spartan-3E’’, ‘‘Altera Cyclone II’’ and ‘‘Alter Cyclone III’’ are different. They are 0.103, 0.303 and 0.0961, as shown in Fig. 7. 4. Experimental results We use infrared imager as reference temperature distribution. A FLIR SC5000 which has a spatial resolution of 3 lm, was used to capture the infrared imager of the FPGA chips. For more accurate temperature measurement, the package of FPGA chip was thinned using a laser. The bonding diagram of the FPGA chip is shown in Fig. 5c. The thermal sensors in the configured FPGA with two Nios II processor programs were set up to measure temperatures in turns. The thermal map of the die constructed by the thermal sensors of the Nios II/e processor is shown in Fig. 5b, while that of the Nios II/f processor is shown in Fig. 6b. Hot spots arise from die-level power dissipation non-uniformity which is due to the location of the functional blocks with high computation. The corresponding infrared images of the FPGA chip are shown in Figs. 5c and 6c. The figures show that the location of hot spot in the thermal map is the same as that in the infrared image, which agrees with the floorplans of the logic blocks shown in Figs. 5a and 6a. Their temperature gradients of the die measured by both methods are similar. Because the number of LEs for the Nios II/f is larger than that of the Nios II/e processor, its temperature in the thermal map is 2 °C higher. The temperature tested by smart thermal sensors is 1.5 °C higher than that by infrared imager in Figs. 5 and 6 in that the sensors measure inner temperature of die rather than that of surface of package. The results showed that the thermal map generated by the proposed sensor was matched with the one captured by thermal imager with a small offset. The error map between by the sensors and by thermal imager is shown as Fig. 8. In order to study the influence of number of inverters on accuracy, we carry out an experiment with changing the number of inverters. The output frequency decreases with the increase of the inverters’ number, as shown in the right side of Fig. 9, but its power consumption goes up [14]. The higher the frequency is,
21 97.08 0.0961 0.9–1.56 0.75
25 81.27 0.117 0.5–1.11 0.627
27 75.9 0.126 0.7–0.8 0.586
31 65.22 0.146 0.6–0.9 0.503
Fig. 10. The thermal transients of the FPGA chip.
the more circulation times to keep the resolution large enough. Shown in Table 1, with the increase of number of inverters, the slop of line of the frequency with temperature becomes small, that means lower resolution in the sense of measurement. So, there is a trade-off relation among the resolution, power consumption and the number of sensors. The results were listed in Table 1. For thermal transient measurements, we configured the FPGA with a transient pulse after a time of 6 s, which the power of 6 mW was evaluated by Altera PowerPlay. The thermal transient behavior is as shown in Fig. 10. The y-axis on the right in Fig. 9 is the power consumption of the transient pulse configured on FPGA. By the common definition that thermal time constant is the time for temperature to reach 63.2% of its maximum, the temperature rise time is 3 ms, and it increases exponentially to a steady state after a few seconds. The red line on the lower right of the figure is the first-order exponential fitting curve. From the fitting curve, we obtained the formula:
ðtt 0 Þ T ¼ DT 1 e s þ T 0
T 0 ¼ 32:5 C; DT ¼ 2:5 C; t0 ¼ 6013 ms;
s ¼ 3:384 ms
ð5Þ
The variable s in the formula expresses the thermal time constant; therefore, the time constant is approximately 3 ms, and the maximum sampling rate is 330 Hz. The experimental results show that fast and accurate temperature measurements can be realized. This method can be used to measure transient thermal characteristics. 5. Conclusion In summary, a digital method of temperature distribution measurement using smart thermal sensors on an FPGA-based system has been presented. The sensors are based on thermally-sensitive ring oscillators without any analog parts. We propose two different Nios processor designs to estimate the sensor temperatures and construct the thermal map of the die using an array of sensors. Using the infrared imager, we capture the thermal emissions of the FPGA chip for comparison with that measured using the
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
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Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
sensors. The proposed sensors can easily measure the die’s thermal gradients and hot spots during operation, with a measurement error of less than 1.6 °C and a maximum sampling rate of 330 Hz. Acknowledgements This work was supported in part by National Natural Science Foundation of China under Grants 61376077, 61201046, and 61204081; in part by the Beijing Natural Science Foundation under Grants 4132022 and 4122005; in part by Strategic Emerging Industry Project of Guangdong under Grant 2012A080304003. References [1] Ruething C, Agne A, Happe M, et al. Exploration of ring oscillator design space for temperature measurements on FPGAs. In: 22nd International conference on field programmable logic and applications (FPL), IEEE; 2012. p. 559–62. [2] Gag M, Wegner T, Waschki A, et al. Temperature and on-chip crosstalk measurement using ring oscillators in FPGA. In: 15th International symposium on design and diagnostics of electronic circuits & systems (DDECS), IEEE; 2012. p. 201–4. [3] Lopez-Buedo S, Boemo E. Making visible the thermal behavior of embedded microprocessors on FPGAs: a progress report. In: Proceedings of the 2004 ACM/SIGDA 12th international symposium on field programmable gate arrays, ACM; 2004. p. 79–86.
[4] Nowroz AN, Reda S. Thermal and power characterization of fieldprogrammable gate arrays. In: Proceedings of the 19th ACM/SIGDA international symposium on field programmable gate arrays, ACM; 2011. p. 111–4. [5] Happe M, Agne A, Plessl C. Measuring and predicting temperature distributions on FPGAs at run-time. In: International conference on reconfigurable computing and FPGAs (ReConFig), IEEE; 2011. p. 55–60. [6] Zick KM, Hayes JP. Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems. ACM Trans Reconf Technol Syst 2012;5(1):1:1–1:26. [7] Chen P, Chen SC, Shen YS, et al. All-digital time-domain smart temperature sensor with an inter-batch inaccuracy of 07–0.6 after one point calibration. IEEE Trans Circ Syst I: Reg Pap 2011;58(5):913–20. [8] Xie S, Ng WT. A low power all-digital self-calibrated temperature sensor using 65 nm FPGAs. In: International symposium on circuits and systems (ISCAS), IEEE; 2013. p. 2617–20. [9] Chen P, Shie MC, Zheng ZY, et al. A fully digital time-domain smart temperature sensor realized with 140 FPGA logic elements. IEEE Trans Circ Syst I: Reg Pap 2007;54(12):2661–8. [10] Demassa TA, Ciccone Z. Digital integrated circuits. New York: Wiley; 1996. [11] Filanovsky IM, Allam A. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Trans Circ Syst I, Fundam Theory Appl 2001;48(7):876–84. [12] Boemo E, López-Buedo S. Thermal verification on FPGAs. In: 23rd NORCHIP conference, IEEE; 2005. p. 48–53. [13] Datta B, Burleson W. Low-power and robust on-chip thermal sensing using differential ring oscillators. In: Proceedings of 50th midwest symposium on circuits and systems (MWSCAS); 2007. p. 29–32. [14] Sedra AS, Smith KC. Microelectronic circuits. 5th ed. New York: Oxford Univ. Press; 2004.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
All-digital thermal distribution measurement on field programmable gate array using ring oscillators Yuan Yue a, Feng Shi-Wei a,⇑, Guo Chun-Sheng a, Yan Xin a, Feng Rui-Rui b a b
School of Electronic Information & Control Engineering, Beijing University of Technology, Beijing 100124, China College of Physical Science and Technology, Sichuan University, Sichuan 610207, China
a r t i c l e
i n f o
Article history: Received 17 March 2014 Received in revised form 29 September 2014 Accepted 12 October 2014 Available online xxxx Keywords: Field programmable gate array (FPGA) Thermal sensor Temperature distribution Transient Oscillator
a b s t r a c t In this paper, a digital method for transient temperature distribution measurement of field programmable gate array (FPGA)-based systems is proposed. The smart thermal sensors used rely on correspondence between the delay and temperature in a ring oscillator. The tested temperature was converted into a time signal with a thermally-sensitive width. The output frequency is read out by a counter with a scan path, and then, transited to PC by a Universal Serial Bus (USB) interface. We capture the infrared images of the FPGA chip by infrared camera. The images were compared with the thermal map of the die constructed using an array of sensors. The tested temperature error varies by less than 1.6 °C in the range from 20 °C to 90 °C, and the maximum sampling rate is 330 Hz. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Field programmable gate array (FPGA)-based system device structures are shrinking while their device densities are increasing, meaning that thermal management is gaining increasing importance in these structures [1]. High temperature affects the performance of circuits, which can lead to timing errors and reduced reliability [2]. While methods are available to gather the thermal information, like embedded diodes available in FPGAs or use of infrared imagers [3,4], these methods are not suitable for use in that embedded diodes can get the temperature at points in the die, and infrared imagers are rarely used for their expensive and destructive causes. Therefore, the smart thermal sensor has been proposed, which can enable measurement of the junction temperature distribution rather than single position temperature of the package. Numerous ring oscillator-based thermal sensors have been described in the literature previously [5–8], but the detailed studies have been rarely performed to date. Datta and Burleson [13] proposed use of differential ring oscillators (DRO) for thermal sensing, but its sensing design depended on full-custom which made it hard to adapt to process variation. The differential ring oscillators are fixed in a certain position of the die. In [5] the authors proposed temperature sensors based on ROs. The system
⇑ Corresponding author. E-mail address: [email protected] (S.-W. Feng).
calibrated them using an internal precalibrated thermal diode on a Virtex-6 FPGA. In this paper, an array of sensors is used to construct a thermal map of the die to measure its temperature distribution and to predict the transient thermal behavior of the FPGA-based system. The sensors are fully digital and constructed by pure standard cell-based design that can be dynamically inserted and eliminated at any position of the die. The proposed all-digital thermal sensor can be used to get transient thermal distribution of the die. We also captured the infrared images of the package for comparison with the measured results of the sensors in order to calibrate the thermal sensor and to improve the accuracy by evaluating the influence of the number of inverters. 2. Smart thermal sensor The smart thermal sensor consists of a thermally sensitive ring oscillator, which is a circular chain with an odd number of inverters, as shown in Fig. 1. The oscillation period is twice the sum of the delays, and is given as [9]:
f out ¼
1 2N T d
ð1Þ
where N is the number of inverters resident in the ring oscillator, and Td is the average propagation delay. By neglecting the effects of velocity saturation, channel length modulation and other nonidealities for simplicity, the propagation delay under the first-order approximation can then be given as [10]:
http://dx.doi.org/10.1016/j.microrel.2014.10.010 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
2
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
fout
enable
Fig. 1. Schematic of the ring oscillator.
Td ¼
ðL=WÞC L 1:5V DD 2V T ln lC ox ðV DD V T Þ 0:5V DD
ð2Þ
The length/width ratio L/W, the gate oxide capacitance Cox and the effective load capacitance CL are independent of the temperature, while the thermal characteristics of the mobility l and the threshold voltage VT change with temperature, and can be derived as follows [11]:
l ¼ l0
T T0
km
Fig. 3. Sensor output frequency dependence on temperature.
ð3Þ
V T ðTÞ ¼ V T ðT 0 Þ þ aðT T 0 Þ
ð4Þ
In the majority of designs, the supply voltage is chosen to be high enough that VDD VT. Under these conditions, the delay becomes virtually independent of the supply voltage, and the electron mobility plays the main role in thermal effects of the propagation delay. The threshold voltages of transistors for Altera FPGA are 100 mV, the supply voltage is 3.3 V which is much greater than the threshold voltage. Because of the negative temperature coefficient of the surface carrier mobility for electrons, the propagation delay Td has a positive temperature coefficient. This means that as the temperature increases, then the output frequency of the ring oscillator decreases. The block diagram of the smart thermal sensor is depicted in Fig. 2. The thermal sensor converts temperature into time information being fed into a time-to-digital converter according to a reference clock for digital coding. The ring oscillator translates the tested temperature into a pulse with a temperature-proportional width. A counter with a scan path captures the frequency over a fixed pulse to produce the digital output which is transmitted to the computer through the Universal Serial Bus (USB) interface. The fixed period is provided by the system clock, and it is useful to increase the wiring delays and thus reduce the operating frequency of the ring oscillator; in this case, the goal is to make the operating frequency lower than that of the system clock to minimize self-heating [11].
Fig. 4. Sensor output frequency dependence on power supply voltage.
3. FPGA implementation An Altera Cyclone III series FPGA chip is used for circuit realization to verify the proposed thermal sensor. A ring oscillator is constructed using inverters, which can be mapped on the FPGA using the look-up tables (LUT); the logic utilization for such a sensor is as low as 21 logic elements (LE). A delay line can be built among the
Counter Digital output
PRE D Add0 A[25..0] 00001 --
B[25..0]
counter~[25..0]
26' h0000000 --
LessThan0 CIN
SEL DATAA
+
UART
Q
DATAB
counter[25..0]
1
A[25..0] 26' h2FAF080 --
PRE OUT0
D
B[25..0]
<
Q
ENA
Fixed pulse
CLR
LESSTHAN
ADDER
ENA MUX21
CLR
PC
CLK
Fig. 2. Block diagram of the thermal sensor.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
3
(a) The floorplan of the Nios II/e processor.
36.3
(b) The thermal map of the Nios II/e processor.
(c) The infrared image of the Nios II/e processor. Fig. 5. The experimental results for the Nios II/e processor.
inverters to reduce the operating frequency of the ring oscillator. Synthesis optimization should be prohibited during logic complication to prevent the synthesis of the delay line [12]. The power consumption of the thermal sensor is measured to be 750 nW. An array of 4 6 sensors was placed in the FPGA to measure the die temperature distribution. It is important to use the logic lock technology to fix the positions of the 24 sensors on the FPGA and to ensure their positions unchanged when embedded in different programs; the yellow boxes showing the locations of
the thermal sensors are depicted in Fig. 3. The FPGA was configured with all of the thermal sensors, but takes turns in opening these sensors for frequency measurements to reduce the effects of self-heating [11]. Each thermal sensor need to be calibrated before use. We put the configured FPGA board in a temperature-controlled oven, and used a long ribbon cable to transmit out the signals to the computer outside [12]. The measured calibration curves between temperatures and output frequency of the 24 sensors are shown
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
4
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx
(a) The floorplan of the Nios II/f processor.
Fig. 7. Sensor output frequency of different chips.
39.2
(b) The thermal map of the Nios II/f processor.
Fig. 8. The measurement error map between the sensor and thermal imager.
(c) The infrared image of the Nios II/f processor. Fig. 6. The experimental results for the Nios II/f processor.
in Fig. 3. They exhibited a perfect linear dependence on temperature, with a coefficient of 95 kHz/°C. Fig. 4 shows the output frequency depends on power supply variations. They exhibited a perfect linear dependence with a coefficient of 1.03 kHz/mV. Figs. 3 and 4 show that the variation of frequency with temperature is much larger than that with the power supply voltage. It could be inferred that large increments of the temperature can’t be covered by tiny power supply variations. The supply voltage is 3.3 V all the time. So the tiny variation of power supply influence is negligible.
Fig. 9. Output frequency dependence on temperature for different numbers of inverters.
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
5
Y. Yue et al. / Microelectronics Reliability xxx (2014) xxx–xxx Table 1 Measurement errors, resolution and power consumption vary with the number of inverters. The number of inverters Frequency (MHz) Resolution (°C) Error (°C) Power (lW)
9 175.87 0.0435 0.6–0.7 1.358
15 137.87 0.0695 0.5–0.6 1.0651
17 120.89 0.0828 0.8–1.1 0.933
The FPGA is a programmable logic device. Running different programs maybe cause different hot spots or temperature gradients. We evaluated the smart thermal sensors by embedding two different configurations of the Nios II processor within the FPGA: the Nios II/e with 600–700 logic elements and the Nios II/f with 1400–1800 logic elements. The overall power consumption of the program is about 240 mW, the additional power consumption caused by the thermal sensor is much less than the overall power consumption. We used logic lock to constrain the logic blocks of the Nios II/e processor to fit into a 17 12 array of the layout, as depicted in Fig. 5a, and used a 19 17 array of logic blocks for the Nios II/f processor, as shown in Fig. 6a. For comparison, we implement the same program on a Xilinx Spartan-3E FPGA, a Altera Cyclone II FPGA and a Altera Cyclone III FPGA respectively. Fig. 7 illustrates the output frequencies versus die temperature on the three FPGA chips. Ring-oscillators in the chips exhibit a linear response in operation temperature range. The resolutions of the temperature sensors implemented on ‘‘Xilinx Spartan-3E’’, ‘‘Altera Cyclone II’’ and ‘‘Alter Cyclone III’’ are different. They are 0.103, 0.303 and 0.0961, as shown in Fig. 7. 4. Experimental results We use infrared imager as reference temperature distribution. A FLIR SC5000 which has a spatial resolution of 3 lm, was used to capture the infrared imager of the FPGA chips. For more accurate temperature measurement, the package of FPGA chip was thinned using a laser. The bonding diagram of the FPGA chip is shown in Fig. 5c. The thermal sensors in the configured FPGA with two Nios II processor programs were set up to measure temperatures in turns. The thermal map of the die constructed by the thermal sensors of the Nios II/e processor is shown in Fig. 5b, while that of the Nios II/f processor is shown in Fig. 6b. Hot spots arise from die-level power dissipation non-uniformity which is due to the location of the functional blocks with high computation. The corresponding infrared images of the FPGA chip are shown in Figs. 5c and 6c. The figures show that the location of hot spot in the thermal map is the same as that in the infrared image, which agrees with the floorplans of the logic blocks shown in Figs. 5a and 6a. Their temperature gradients of the die measured by both methods are similar. Because the number of LEs for the Nios II/f is larger than that of the Nios II/e processor, its temperature in the thermal map is 2 °C higher. The temperature tested by smart thermal sensors is 1.5 °C higher than that by infrared imager in Figs. 5 and 6 in that the sensors measure inner temperature of die rather than that of surface of package. The results showed that the thermal map generated by the proposed sensor was matched with the one captured by thermal imager with a small offset. The error map between by the sensors and by thermal imager is shown as Fig. 8. In order to study the influence of number of inverters on accuracy, we carry out an experiment with changing the number of inverters. The output frequency decreases with the increase of the inverters’ number, as shown in the right side of Fig. 9, but its power consumption goes up [14]. The higher the frequency is,
21 97.08 0.0961 0.9–1.56 0.75
25 81.27 0.117 0.5–1.11 0.627
27 75.9 0.126 0.7–0.8 0.586
31 65.22 0.146 0.6–0.9 0.503
Fig. 10. The thermal transients of the FPGA chip.
the more circulation times to keep the resolution large enough. Shown in Table 1, with the increase of number of inverters, the slop of line of the frequency with temperature becomes small, that means lower resolution in the sense of measurement. So, there is a trade-off relation among the resolution, power consumption and the number of sensors. The results were listed in Table 1. For thermal transient measurements, we configured the FPGA with a transient pulse after a time of 6 s, which the power of 6 mW was evaluated by Altera PowerPlay. The thermal transient behavior is as shown in Fig. 10. The y-axis on the right in Fig. 9 is the power consumption of the transient pulse configured on FPGA. By the common definition that thermal time constant is the time for temperature to reach 63.2% of its maximum, the temperature rise time is 3 ms, and it increases exponentially to a steady state after a few seconds. The red line on the lower right of the figure is the first-order exponential fitting curve. From the fitting curve, we obtained the formula:
ðtt 0 Þ T ¼ DT 1 e s þ T 0
T 0 ¼ 32:5 C; DT ¼ 2:5 C; t0 ¼ 6013 ms;
s ¼ 3:384 ms
ð5Þ
The variable s in the formula expresses the thermal time constant; therefore, the time constant is approximately 3 ms, and the maximum sampling rate is 330 Hz. The experimental results show that fast and accurate temperature measurements can be realized. This method can be used to measure transient thermal characteristics. 5. Conclusion In summary, a digital method of temperature distribution measurement using smart thermal sensors on an FPGA-based system has been presented. The sensors are based on thermally-sensitive ring oscillators without any analog parts. We propose two different Nios processor designs to estimate the sensor temperatures and construct the thermal map of the die using an array of sensors. Using the infrared imager, we capture the thermal emissions of the FPGA chip for comparison with that measured using the
Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010
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sensors. The proposed sensors can easily measure the die’s thermal gradients and hot spots during operation, with a measurement error of less than 1.6 °C and a maximum sampling rate of 330 Hz. Acknowledgements This work was supported in part by National Natural Science Foundation of China under Grants 61376077, 61201046, and 61204081; in part by the Beijing Natural Science Foundation under Grants 4132022 and 4122005; in part by Strategic Emerging Industry Project of Guangdong under Grant 2012A080304003. References [1] Ruething C, Agne A, Happe M, et al. Exploration of ring oscillator design space for temperature measurements on FPGAs. In: 22nd International conference on field programmable logic and applications (FPL), IEEE; 2012. p. 559–62. [2] Gag M, Wegner T, Waschki A, et al. Temperature and on-chip crosstalk measurement using ring oscillators in FPGA. In: 15th International symposium on design and diagnostics of electronic circuits & systems (DDECS), IEEE; 2012. p. 201–4. [3] Lopez-Buedo S, Boemo E. Making visible the thermal behavior of embedded microprocessors on FPGAs: a progress report. In: Proceedings of the 2004 ACM/SIGDA 12th international symposium on field programmable gate arrays, ACM; 2004. p. 79–86.
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Please cite this article in press as: Yue Y et al. All-digital thermal distribution measurement on field programmable gate array using ring oscillators. Microelectron Reliab (2014), http://dx.doi.org/10.1016/j.microrel.2014.10.010