Alternative fabrication process for edgeless detectors on 6 in. wafers

Nuclear Instruments and Methods in Physics Research A 633 (2011) S50–S54

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Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima

Alternative fabrication process for edgeless detectors on 6 in. wafers ¨ Juha Kalliopuska n, Simo Eranen, Tuula Virolainen VTT Micro and Nanoelectronics, Tietotie 3, Espoo, P.O. Box 1000, FI-02044 VTT, Finland

a r t i c l e in f o

a b s t r a c t

Available online 9 July 2010

VTT has developed a straightforward and fast process to fabricate edgeless (active edge) microstrip and pixel detectors on 6 in. (150 mm) wafers. The process avoids all slow process steps, such as polysilicon growth, planarization and additional ICP-etching. We have successfully fabricated 150 mm thick p-on-n and n-on-n prototypes of edgeless detectors having dead layers at the edge with a thickness below a micron. Fabrication was done on high resistivity n-type FZ-silicon wafers. The prototypes include 5  5 and 1  1 cm2 edgeless microstrip detectors with DC-, FOXFET- and PT-couplings. In addition 1.4  1.4 cm2 Medipix2 edgeless pixel detectors were also fabricated. This paper presents leakage current, capacitance and breakdown voltage measurements of different DC-coupled microstrip designs and compares them with respect to the active edge distance and polarity of the detector. The active edge distances were 20, 50 and 100 mm from the strips. Electrical characterization of these detectors on the wafer level gave promising results. A good uniformity in the measured parameters was observed for the inner strips. The parameters of the adjacent strip to the edge showed a dramatic dependence on the active edge distance. Leakage current and capacitance of the inner microstrips were 50–70 nA/cm2 and 580–660 pF/cm2 at, respectively, 40 V reverse bias for the p-on-n. For the n-on-n design these parameters were 116–118 nA/cm2 and 930–960 pF/cm2. The breakdown voltages were above 150 V for p-on-n prototypes and increased as a function of active edge distance. To fully deplete the p-on-n detectors required twice as much reverse bias as was needed for the n-on-n detectors, i.e. 13–28 V. & 2010 Elsevier B.V. All rights reserved.

Keywords: Solid-state detector Silicon detector Edgeless detector Active edge detector Ion implantation

1. Introduction The edgeless (active edge) detector design permits tiling of the chips to long ladders or matrixes in order to realize large imaging detectors with negligible insensitive area between the mosaic elements. For charged particle detection and molecular biology, the design permits a large active-to-inactive area ratio [1]. The conventional fabrication process for the edgeless and 3D detectors uses doped polysilicon filling or a doped source diffusion to activate the edges or columns in these designs, respectively [1–6]. Different 3D detector designs have been fabricated by a few European organizations on 100 mm wafers. Single type column detectors were presented by VTT and FBK IRST [2,3]. Double-side double-type column 3D detectors have been fabricated by FBK IRST and CNM [4,5]. The process of the detectors has been done on a single wafer with a double sided process (DSP) and the detectors do not have active edges. In this case, the detector thickness is bound by the wafer thickness, which can handle the DSP without use of a support. Full 3D active edge detectors have been fabricated by Hansen et al. [6]. Fabrication of the active edge requires the use of a support wafer, which also gives a freedom to further decrease the

n

Corresponding author. Tel.: +358 414 313 212; fax: + 358 20 722 7012. E-mail address: juha.kalliopuska@vtt.fi (J. Kalliopuska).

0168-9002/$ - see front matter & 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2010.06.119

detector thickness without a fear of breaking the wafer during the complicated process. VTT has done process development to be able to fabricate edgeless detectors on 150 mm wafer. The first prototypes of the edgeless detectors were fabricated using polysilicon filling of the trenches. Electrical characterization of these detectors showed low leakage currents but very early breakdown voltage [7]. After the submission of Ref. [7], wafer level leakage current measurements were done for the first prototypes and the results are presented here. Early breakdown was still present and thus edge cracking could not be the single cause of breakdown. It was concluded that the polysilicon filling causes yield problems in the process and might be the reason for the early breakdown voltages. In addition, a straightforward and fast process to fabricate the edgeless detectors was proposed in Ref. [7]. The alternative process relies on side wall ion implantation and avoids all slow process steps, such as polysilicon growth, planarization and additional ICP etching.

2. Edgeless detector designs Even though edgeless 1.4  1.4 cm2 pixel detectors and large area 5  5 cm2 microstrip detectors were fabricated and successfully removed from the support wafer, their characterizations will

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Fig. 1. Wafer level photographs, (a)–(c), show the active edge distances of 100, 50 and 20 mm from the strips, respectively. Schematic (d) shows the bias corner of the n-onn detector design, where a common p-stop has been implemented.

be reported as separate articles. This paper concentrates on characterization of DC-coupled 1  1 cm2 edgeless microstrip prototype detectors with varied active edge distances and polarities. High resistivity n-type FZ-silicon wafers were used in the fabrication of the prototypes. The pitch of the strips is 50 mm. The active edge distances were 100, 50 and 20 mm from the strips, as shown in Fig. 1(a)–(c), respectively. The detectors that were characterized for this paper had bias contact on the front surface at one corner as presented in Fig. 1(d). 2.1. p-on-n and n-on-n design For the p-on-n design, the active edge and the backplane have n-type doping, holes are collected and depletion of the detector starts from the strips as the reverse bias is applied. For the n-on-n design, the active edge and the backplane have p-type doping, electrons are collected and depletion of the detector starts from the active edge and backplane as the reverse bias is applied. The n-on-n design requires an additional p-stop implementation, as presented in Fig. 1(d). Advantages of the n-on-n design are: 1. better edge depletion (signal collection) at low voltages and 2. possibility to collect electrons that have higher mobility than holes. Electron collection is favorable in hard radiation environments at colliders, where silicon bulk damage causes type inversion of the n-type bulk to p-type, introduces defect traps and reduces charge carrier lifetimes. Charge collection efficiency after high radiation doses is considerably better for the electrons. It has been shown in Ref. [8] that the n-on-n FZ silicon diodes give the highest charge collection after high radiation doses of protons and neutrons.

2.2. Active edge Fig. 2 shows a macro photograph of individual edgeless detectors after the handle wafer removal process. Back side oxide has been removed for the detectors that did not have a bias contact on the front surface. Also the Punch-Through and FOXFET biased edgeless detectors are illustrated. It should be emphasized that the protecting oxide layer on the active edge shows a beautiful reflection of light. Tweezers can be used to handle the detectors without cracking the edge and destroying the detector. This is big advantage compared with the detectors where polysilicon had been used to activate the edges. Fig. 3(a) and (b) shows SEM images of the edge of the detector fabricated with polysilicon filling and ion implantation, respectively. The detectors fabricated using ion implantation have about only 500 nm layer inactive silicon oxide protecting the edge against damage and contamination. Fig. 3(a) shows an inactive polysilicon layer of about 6 mm thick. Fairly small pressure to this edge causes the polysilicon layer to completely detach from the silicon–polysilicon interface.

3. Electrical characterization Electrical characterization of the microstrip detectors has been done on a wafer level in a dark probe station in a clean room. Four probes were used except for the n-on-n detector leakage current measurements—one for biasing the detector, two for grounding the perimeter of the strip at the center and one to read out the current (l´–V) or capacitance (C–V) from the center strip. The measurements were done on strips near the biasing corner, as shown in Fig. 2. The lengths of the two strips closest to the edge are about 50 mm (0.5%) shorter than the length of the other strips. The first I–V and C–V measurements showed that this length

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1E-9

Current (A /cm)

1E-9

1E-10

1E-10 20 um, implantation 50 um, implantation 100 um, implantation 50 um, poly fill 100 um, poly fill

1E-11 0 Fig. 2. Macro-photograph of edgeless detector designs. At top right are shown biasing corners of DC-coupled edgeless detectors with active edge distances of 20, 50 and 100 um (order from bottom to top). At bottom are shown the PunchThrough (top) and FOXFET (bottom) biased detector designs with the active edge distance of 50 mm. At left are shown back sides of the detectors with removed oxide for biasing (top) and intact oxide (bottom).

10

20

30

40

50

60

70

80

1E-11 90 100

Bias Voltage (V) Fig. 4. Leakage current of a strip with varied active edge distances and fabrication method.

20 um, p-on-n 50 um, p-on-n

1E-6

100 um, p-on-n

1E-6

20 um, n-on-n 50 um, n-on-n

2

Current I (A/cm )

100 um, n-on-n

1E-7

1E-7

-90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Bias Voltage (V)

Fig. 3. SEM images of (a) polysilicon and (b) ion implantation activated edgeless detectors. In (a), the polysilicon leaves an inactive region of several microns to the edge and also causes edge cracking fairly easily.

difference and the adjacent bias contact did not have a considerable effect on the characteristics.1

3.1. Leakage current and breakdown voltage Fig. 4 shows a comparison between the polysilicon and ion implantation prototypes for the p-on-n design. Thicknesses of the detectors were 300 and 150 mm, respectively. The leakage current was measured on the 10th strip from the active edge.2 The early breakdown of the polysilicon detectors on the wafer level indicates that the polysilicon filling itself causes the early breakdown. This can be due to stresses and strains in the polysilicon–silicon interface, which may create generation centers for leakage current. The ion-implanted detectors did not show any sign of breakdown below 100 V and the single strip leakage current increased as a function of active edge distance. 1 Measurement results of the second strip from the active edge are similar to the presented ones and are not shown in figures for the sake of clarity. 2 Distance from the active edge for the 10th strip is about 0.5 mm. Most of the 200 strips in the detector have similar environment geometry and should thus have uniform electrical characteristics.

Fig. 5. Breakdown voltage measurement of the p-on-n and n-on-n detector designs with different active edge distances.

Fig. 5 shows the measured breakdown voltages for the p-on-n and n-on-n designs. To compare the leakage currents of the two polarities, the current level in Fig. 5 is scaled to units of A/cm2. The leakage current level is higher than in Fig. 4 due to the measurement setup.3 The breakdown voltage increases as a function of active edge distance. The earliest breakdown was observed at 150 and 75 V for the p-on-n and n-on-n detectors with the active edge distance of 20 mm, respectively. The breakdown in both designs occurs at the end of the strips, where the electric field reaches its highest values. The breakdown could possibly be improved with hanging metal field plates that extend beyond the implantation of the strip. Also additional floating guard ring structures could be implemented between the strips and the active edge.

3.2. Capacitance. Capacitance was measured as a function of bias voltage using four probes and small signal AC analysis with a signal of 500 mV 3 Measurement has been carried out by using only two probes—one connected to the bias and other to the strip closest to the active edge. The bias voltage was scanned from 100 to 100 V, while keeping the strip voltage at 100 V.

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6E-12

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6E-12

20 um, edge

5.5E-12

5.5E-12

20 um, center

Capacitance (F)

5E-12

5E-12

50 um, edge 50 um, center

4.5E-12

4.5E-12

100 um, edge 100 um, center

4E-12

4E-12

3.5E-12

3.5E-12

3E-12

3E-12

0

5

10

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20

25

30

35

40

Bias Voltage (V)

7E-12

7E-12

20 um, edge 6.5E-12

50 um, edge

6E-12

Capacitance (F)

6.5E-12

20 um, center

6E-12

50 um, center 100 um, edge

5.5E-12

5.5E-12

100 um, center 5E-12

5E-12

4.5E-12

4.5E-12

4E-12

4E-12 0

-5

-10

-15

-20

-25

-30

-35

-40

Bias Voltage (V) Fig. 6. Capacitance of (a) p-on-n and (b) n-on-n detectors with various active edge distances. The 10th strip from the edge is labeled as ‘‘center’’ and the strip closest to the edge as ‘‘edge’’.

Table 1 Edgeless detector properties for different polarities and active edge distances. Edge distance and polarity

Full depletion (V)

Center depletion (V)

Junction breakdown (V)

20 mm p-on-n n-on-n

22 13

20 8

 145  75

50 mm p-on-n n-on-n

34 24

24 10

 180  90

100 mm p-on-n n-on-n

440 28

32 10

4200  95

The depletion voltages at the edge and center of the detector were extracted from the 1/C2 curves calculated from Fig. 6. Front-to-back plane depletion for both polarities was observed at 8 V. Full depletion and center depletion voltages of the detectors as a function of active edge distance are shown in Table 1. It also summarizes the junction breakdown voltages for each detector type. As a rule of thumb, to achieve full depletion in the p-on-n detectors requires double the voltage as compared with the n-on-n detectors. In addition, the breakdown voltage of p-on-n detectors is twice as high.

4. Discussion

and 10 kHz frequency. In general, the capacitance at the inner strips is only slightly dependent on the active edge distance. The capacitance of the strip closest to the active edge decreases as a function of edge distance.

VTT has successfully fabricated several prototypes of 150 mm thick p-on-n and n-on-n edgeless detectors on 6 in. wafers with various active edge distances. The inactive physical region at the edge is only 500 nm for these detectors. The handle wafer removal and under bump metallization (UBM) have been done for few wafers without damaging the detectors.

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VTT is able to offer thin active edge detectors and their packaging with 2–3 months delivery time. Further work on edgeless strip detector characterization includes determination of the edge activity, beam tests and irradiation tests at different facilities.

References [1] S. Parker, et al., Nuclear Instruments and Methods in Physics Research A 565 (2006) 272.

[2] J. Kalliopuska, et al., Nuclear Instruments and Methods in Physics Research A 568 (2006) 22. [3] C. Piemonte, et al., Nuclear Instruments and Methods in Physics Research A 541 (2005) 441. [4] A. Zoboli, et al., Nuclear Instruments and Methods in Physics Research A 612 (2010) 521. [5] D. Pennicard, et al., Nuclear Instruments and Methods in Physics Research A 598 (2009) 67. [6] T. E. Hansen, et al., First fabrication of full 3D-detectors at SINTEF, 2009 JINST 4 P03010. [7] J. Kalliopuska, et al., Nuclear Instruments and Methods in Physics Research A 607 (2009) 85. [8] A. Affolder, et al., Nuclear Instruments and Methods in Physics Research A 604 (2009) 250.