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Ammonia-free chemically deposited CdS films as active layers in thin film transistors
Thin Solid Films 519 (2010) 517–520
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Thin Solid Films j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f
Ammonia-free chemically deposited CdS films as active layers in thin film transistors G. Arreola-Jardón a, L.A. González b, L.A. García-Cerda c, B. Gnade d, M.A. Quevedo-López d,e, R. Ramírez-Bon a,⁎ a
Centro de Investigación y Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro., 76001, México Centro de Investigación en Física, Universidad de Sonora, Apdo. Postal 5-088, CP 83000, Hermosillo, Son., México Centro de Investigación en Química Aplicada, Blvd. Enrique Reyna Hermosillo No. 140, Saltillo, Coah. 25253, México d Material Science and Engineering, The University of Texas at Dallas. Richardson 75083, TX, USA e Departamento de Polímeros y Materiales, Universidad de Sonora, Apdo. Postal 130, CP 83000, Hermosillo, Sonora, México b c
a r t i c l e
i n f o
Article history: Received 8 January 2010 Received in revised form 11 August 2010 Accepted 16 August 2010 Available online 20 August 2010 Keywords: Cadmium sulfide Chemical bath deposition Field effect transistors Electrical properties and measurements
a b s t r a c t In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12–0.16 cm2V−1 s−1 and 8.8–25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8–8.8 cm2V−1 s−1 and the threshold voltage decreased to 8.4–12 V. Ion/Ioff for the annealed devices was approximately 105–106. © 2010 Elsevier B.V. All rights reserved.
1. Introduction The widespread application of flat panel displays has made thin film transistor (TFT) one of the most common devices employed in the electronics industry. In a flat panel display the role of the TFT is to individually control each pixel, for which amorphous silicon is the semiconductor active layer in the current active matrix displays. While amorphous silicon provides adequate performance and reliability for a voltage controlled device like a liquid crystal display, the performance is not adequate for current controlled devices such as an organic light emitting diode, therefore the search for alternative semiconductor materials as active layers in TFTs is still very relevant [1]. Metal chalcogenides such as CdS and CdSe have been studied as semiconductor active layers in TFTs since the early developments of TFTs [2]. More recently, interest in CdS films has been focused on their applications in CdS/CdTe and CdS/CuInxGa1 − xSe2 (CIGS) thin film solar cells. CdS has also been studied in TFT applications for many years [3–7]. Evaporated CdS active layers were used in early work, while chemical bath deposited CdS layers have been used in more recent work. Chemical bath deposition (CBD) provides a costeffective, low-temperature and large-area compatible processing technique for the growth of high quality semiconductor layers. In particular, chemically deposited CdS active layers have shown good performance in TFTs with values of field effect mobility in the range of 0.5–1.5 cm2V−1 s−1 [3–7], comparable to those of amorphous silicon. ⁎ Corresponding author. Tel.: +52 442 2119906; fax: +52 442 2119939. E-mail address: [email protected] (R. Ramírez-Bon). 0040-6090/$ – see front matter © 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2010.08.097
In these previous reports, the recipes generally include ammonia as the complexing agent. Subsequent thermal annealing is performed to improve the electrical properties. In previous papers we have reported the properties of chemically deposited CdS films from an ammonia-free cadmium chloride– sodium citrate–thiourea system [8–11]. We found that this system is very convenient for the growth of CdS films by CBD because it avoids the utilization of ammonia as the complexing agent, allowing a reduction in the amount of cadmium in the reaction solution. The properties of these CdS films are equivalent, or even better, than those of films obtained using conventional CBD recipes based on ammonia as the complexing agent for the cadmium ions. In recent papers our group, as well as others have shown the feasibility of using the ammonia-free chemically deposited CdS films as window layers in CdS–CdTe, CdS–CIGS and CdS sensitized thin film solar cells [12–14]. In this paper we used the cadmium chloride–sodium citrate–thiourea system to grow CdS active layers by CBD for field effect TFT. A p-Si/ SiO2/CdS device with a common bottom gate and Au source/drain contacts, with different channel lengths, was fabricated using lift-off processes. We determined the output responses of the CdS-based TFTs as a function of channel length and thermal annealing conditions. 2. Experimental details The TFTs were fabricated on a RCA cleaned p-Si wafer with a 100 nm thermal SiO2 layer as the dielectric layer of the device. The chemical deposition of the CdS layers on the p-Si/SiO2 substrates was done in a reactive solution prepared in a 100 ml beaker by the
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sequential addition of 15 ml of 0.05 M cadmium chloride (CdCl2, Baker, 99.3%), 15 ml of 0.5 M sodium citrate (C6H5O7Na3, Baker, 99.1%), 5 ml of 0.5 M potassium hydroxide (KOH, Baker, 89.13%), 5 ml of pH 10 buffer solution (Baker) and 7.5 ml of 0.5 M thiourea (CS (NH2)2, Baker, 99.6%). The solution was diluted with deionized water to complete a total volume of 100 ml. The beaker with the reaction solution was immersed in a water bath at 70 °C. The amount of cadmium in this reaction solution is 0.84 mg/ml, which is the optimum concentration for this ammonia-free system to obtain CdS layers with optimum crystalline properties, as shown in recent papers [15]. For the deposition of source and drain contacts, a photoresist layer was deposited on the CdS layer, cured, UV exposed through a shadow mask and developed. The shadow mask consists of pairs of rectangular patterns that represent sets of parallel electrodes (source and drain) whose separation (channel length) decreases from 80 to 20 μm. A 100 nm gold layer was deposited on each sample by e-beam evaporation. The gold source/drain contacts were formed using lift-off process. Chromium (10 nm) and gold (100 nm) were evaporated on the back side of the p-Si wafer to form the back side contact. In order to improve the electrical response of the semiconductor layer some devices were thermal annealed at 250 °C in forming gas for 1 h. The morphology of the semiconductor layer was studied using scanning electron microscopy (SEM). The thicknesses of the dielectric and semiconductor layers were determined using cross sectional SEM. The electrical response of the as-deposited and thermally annealed CdSbased TFTs was determined using current versus voltage measurements at room temperature in a probe station with a 4200 Keithley semiconductor parameter analyzer. 3. Results and discussion A schematic diagram of the final layer structure of the CdS-based TFT is shown in Fig. 1a). Source and drain Au contacts with two
different channel lengths (L), 80 and 40 μm, on top of the CdS layer are shown in Fig. 1b). The width (W) of the Au contacts is 450 μm. The SEM image in Fig. 2a) shows the surface morphology of the CdS layer. The surface of the films is smooth with nanocrystalline grains in a compact granular structure with very well-defined grain boundaries. These are characteristics of the ion-by-ion growth mechanism taking place during the chemical deposition process of the CdS layer [9,16]. An image of the cross section of the device is shown in Fig. 2b), where it is observed from top to bottom the semiconductor CdS layer, the SiO2 dielectric layer and the p-Si substrate. The thickness values were determined to be 110 and 100 nm for the CdS and SiO2 layers, respectively. The output characteristics of the CdS-based TFTs are shown in Fig. 3. The drain current (IDS) versus source–drain voltage (VDS) curves were measured from 0 to 40 V at several gate voltages (VGS), for devices with 80, 40 and 20 μm channel lengths. The family of IDS–VDS curves as a function of gate voltage shows that IDS saturates at pffiffiffiffiffiffi reasonable values of VDS. The IDS versus VGS is shown in Fig. 4. These curves were measured at a fixed VDS of 40 V. The linear region of these curves were fit to the following equation [17] 1= 2
IDS
=
Ci Wμ sat 1 = 2 ðVGS −VT Þ 2L
ð1Þ
to determine the channel mobility, μsat, and threshold voltage, VT, for the devices. In Eq. (1), which is valid for VDS N VGS − VT, Ci is the capacitance per unit area of the gate dielectric layer. The best fits to Eq. (1) are shown as dotted lines in this graph. The threshold voltage, which corresponds to the intersections of the dotted lines with the VGS-axis, decreases for the devices with a lower channel length. The values determined for VT are 25, 19.5, and 8.8 V for the devices with 80, 40, and 20 μm channel length, respectively. The TFT devices operate in the enhancement mode. In this mode, at VGS = 0 V, the device is in the off-state. The channel mobility, which is related to the
a)
200 nm
b)
CdS SiO2 p-Si 100 nm Fig. 1. a) Scheme of the cross section layer structure of the CdS-based thin film transistor. b) Top view image showing the CdS layer surface and a set of two source and drain gold contacts with different channel lengths, L = 40 and 80 μm, and W = 450 μm.
Fig. 2. a) SEM image showing the surface morphology of the CdS layer. b) SEM image showing the cross section of the device.
G. Arreola-Jardón et al. / Thin Solid Films 519 (2010) 517–520
As-deposited VDS=40 V 1) L=80 µm 2) L=40 µm 3) L=20 µm
10-5
35 V
6.0x10-7
L= 80 µm
4.0x10-7
3 0.004
10-6
30 V
2.0x10-7
25 V
10-7
2
0.0
b)
3.0x10-6
As-deposited 35 V
Current (A)
3
40 V
2.0x10-6
1
10-8
1
L= 40 µm 30 V
10-9
0.000 10
0
1.0x10-6 20 V 0.0
c)
As-deposited
40 V
1.5x10-5
35 V
1.0x10-5
L= 20 µm
30 V
20
30
Gate Voltage (V)
25 V
Current (A)
2
0.002
SqrtCurrent (A1/2)
40 V
Current (A)
Current (A)
As-deposited
a)
8.0x10-7
519
pffiffiffiffiffiffi Fig. 4. IDS versus VGS plots (right axis) for the as-deposited CdS-based TFTs with different channel lengths. The dotted straight lines correspond to the best linear fits to Eq. 1. Semi-log plots of IDS versus VGS (left axis) for the same devices.
Ioff = 106 were obtained [6]. Although our results show that chemically as-deposited CdS thin films yield good TFT devices, their electrical parameters are inferior to most of those in literature, even in the case of our best devices with channel length L = 20 μm. To
25 V 5.0x10-6
a)
20 V
Annealed L= 80 µm
40 V
20
30
Voltage (V) Fig. 3. Characteristic IDS versus VDS plots for several values of VGS for the as-deposited CdS-based TFTs with a) 80, b) 40 and c) 20 μm channel lengths.
slope of the dotted line, was 0.13, 0.12 and 0.16 cm2V−1 s−1, for the devices with 80, 40, and 20 μm channel lengths, respectively. Fig. 4 also shows semi-log plots of IDS versus VGS for the three devices, measured at VDS 40 V. The lowest value of IDS corresponding to the offstate of the devices (off-current, Ioff) is 10−9 A, while the on-state currents are 10−5–10−6 A, depending on channel length. Thus the current ratio Ion/Ioff of the devices is of the order of 103–104. The electron mobility of bulk CdS is 210 cm2V−1 s−1 [18], much higher than the field effect mobility measured in CdS-based TFTs. The main reason for lower mobility is the polycrystalline nature of the CdS layers in these devices. As is well known, the grain boundaries in polycrystalline semiconductors have an impact on the electrical transport because they act as dispersion and trapping centers for the charge carriers, reducing the mobility. Thermal treatments at a high temperature in different atmospheres can enhance the crystallinity and passivate defects, including those at the grain boundaries in polycrystalline semiconductors. CdS-based TFTs annealed at 300 °C at a low pressure for 1 h have the characteristics: μsat = 0.5 cm2V−1 s−1, VT = 14 V and Ion/Ioff = 107 [7], devices annealed in vacuum at 200 °C had a mobility of 1.25 cm2V−1 s−1 [4]. No mention of the other parameters were included in this reference. Some reports have included two annealing steps in the TFT fabrication process, before and after deposition of source and drain contacts [3,6]. The first anneal is done to enhance the crystallinity of the CdS layer and the second one to improve the source/drain resistance. By using two rapid thermal anneals at 500 °C in Ar for 5 min, before and after Al contact deposition, devices with μsat = 1.5 cm2V−1 s−1, VT = 14 V and Ion/
30 V 2.0x10-4
20 V 10 V
0.0 1.0x10-3
b)
8.0x10-4
Current (A)
10
Annealed L= 40 µm
40 V
6.0x10-4
30 V
4.0x10-4 20 V
2.0x10-4
10 V 0.0
c)
1.0x10-3
Current (A)
0
Current (A)
4.0x10-4
0.0
Annealed L= 20 µm
40 V
8.0x10-4 6.0x10-4 30 V 4.0x10-4 2.0x10-4
20 V 10 V
0.0 0
10
20
30
Voltage (V) Fig. 5. Characteristic IDS versus VDS plots for several values of VGS for the CdS-based TFTs annealed at 250 °C in forming gas for 1 h with a) 80, b) 40 and c) 20 μm channel lengths.
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Annealed
Current (A)
10-4
VDS=40 V
1) L=80 µm 2) L=40 µm 3) L=20 µm
0.04
3
10-5
3
1
10-6
0.02
2
10-7
SqrtCurrent (A1/2)
10-3
1
2 10-8
0.00
10-9
0
10
20
30
Gate Voltage (V) pffiffiffiffiffiffi Fig. 6. IDS versus VGS plots (solid lines, right axis scale) for the thermally annealed CdSbased TFTs with different channel lengths. The dotted straight lines correspond to the best linear fits to Eq. 1. Semi-log plots of IDS versus VGS (dashes lines, left axis scale) for the same devices.
improve the device performance we annealed the devices in forming gas (N2(90%) + H2(10%)) at 250 ° C for 1 h. The thermal annealing was done on the finished devices, so it impacted the CdS semiconductor layer and the source/drain Au contacts. Fig. 5 shows the family of IDS–VDS curves, measured at several values of VGS, for the thermally annealed CdS-based devices with a) 80, b) 40 and c) 20 μm channel lengths. The thermal annealing significantly increased the drain current in the devices. The devices saturate at IDS levels between 5 × 10−4 and 1 × 10−3 A, N100× higher than in the unannealed devices. The transfer characteristic curves for the annealed devices, measured at VDS = 40 V, with 80, 40 and 20 μm pffiffiffiffiffiffi channel lengths are shown in Fig. 6. The IDS versus VGS curves are plotted as solid lines with the best fits to Eq. 1 in the linear region of these curves plotted as dotted lines (right axis). From the parameters of the linear fits the following electrical characteristics were determined; μsat = 8.8, 6.2 and 4.8 cm2V−1 s−1 and VT = 12, 10.6 and 8.4 V for the annealed devices with L = 80, 40 and 20 mm, respectively. The mobility of the annealed device improves N10× and VT in the annealed devices is sensitive to their channel length. The IDS versus VGS curves plotted as dashed lines in the semi-log graph of Fig. 6 (left axis) show that the off-current of the annealed devices is still 10−9 A, but the on-current increases to 10−4–10−3 A. The thermal annealing process increased the Ion/Ioff ratio of the devices to 105–106. The results described above show that the CdS films deposited using the ammonia-free sodium citrate-based CBD process have good performance as the semiconductor layer in TFT devices. The thermal annealing process in forming gas at a relatively low temperature (250 °C) improved the performance of the devices, with electrical parameters comparable to those reported in literature for chemically deposited CdS-based TFTs. We can assign the device improvement mainly to the benefits of the forming gas annealing on the CdS layer. As it has been reported in several papers [19,20], annealing in forming gas passivates interface states, and chemi-adsorbed impurities at the
grain boundaries in polycrystalline semiconductors with a consequent positive impact on their electrical conductivity and crystalline structure. The ammonia-free CBD process described in this work provides very good quality CdS layers with the advantages of the ammonia elimination and reduced cadmium, making the process promising for application to the development of CdS-based TFT devices. 4. Conclusions In this paper we have reported the electrical performance of chemically deposited CdS layers, obtained from an ammonia-free CBD process, as the active semiconductor layer in field effect thin film transistors. Devices with as-deposited CdS film layers showed good electrical behavior with the following parameters: μsat = 0.13, 0.12 and 0.16 cm2V−1 s−1 , VT = are 25, 19.5, and 8.8 V and Ion/ Ioff ~ 103– 104, for channel lengths of 80, 40 and 20 μm, respectively. The electrical characteristics of the CdS-based TFTs were improved by thermal annealing in forming gas at 250 °C for 1 h. After annealing the measured electrical parameters on the devices were; μsat = 8.8, 6.2 and 4.8 cm2V−1 s−1, VT = 12, 10.6 and 8.4 V and Ion/Ioff ~ 105–106 for the channel lengths of 80, 40 and 20 μm, respectively. Based on these results and on the advantages of the ammonia-free CBD process for the growth of CdS layers, we conclude that it is quite promising for the cost-effective development of TFT devices. Acknowledgements This work was supported by CONACYT through the Becas Mixtas and Sabbatical Programs. The technical assistance of C.A. AvilaHerrera is also acknowledged. References [1] R.E.I. Schropp, B. Stannowski, J.K. Rath, J. Non-Cryst. Solids 299–302 (2002) 1304. [2] W.E. Howard, in: C.R. Kagan, P. Andry (Eds.), Thin Film Transistors, Marcel Dekker, Inc, New York, 2003. [3] F.Y. Gan, I. Shih, IEEE Trans. Electron Devices 49 (2002) 15. [4] C. Voss, S. Subramanian, C.-H. Chang, J. Appl. Phys. 96 (2004) 5819. [5] B. Mereu, G. Sarau, E. Pentia, V. Draghici, M. Lisca, T. Botila, L. Pintilie, Mater. Sci. Eng. B 109 (2004) 260. [6] Y.-J. Chang, C.L. Munsee, G.S. Herman, J.F. Wager, P. Mugdur, D.-H. Lee, C.-H. Chang, Surf. Interface Anal. 37 (2005) 398. [7] J.H. Lee, J.W. Yoon, I.G. Kim, J.S. Oh, H.J. Nam, D.Y. Jung, Thin Solid Films 516 (2008) 6492. [8] M.B. Ortuño-López, J.J. Valenzuela-Jáuregui, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 429 (2003) 34. [9] M.B. Ortuño-López, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 457 (2004) 278. [10] M.B. Ortuño-López, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Vacuum 76 (2004) 181. [11] M.G. Sandoval-Paz, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 515 (2007) 3356. [12] H. Komaki, A. Yamada, K. Sakurai, S. Ishizuka, Y. Kamikawa-Shimizu, K. Matsubara, H. Shibata, S. Niki, Phys. Status Solidi A 206 (2009) 1072. [13] M.F. Hossain, S. Biswas, T. Takahashi, Thin Solid Films 518 (2009) 1599. [14] R. Ochoa-Landín, J. Sastre-Hernández, O. Vigil-Galan, R. Ramírez-Bon, Sol. Energy 84 (2010) 208. [15] R. Ochoa-Landín, M.G. Sandoval-Paz, M.B. Ortuño-López, M. Sotelo-Lerma, R. Ramírez-Bon, J. Phys. Chem. Solids 70 (2009) 1034. [16] M.G. Sandoval-Paz, R. Ramírez-Bon, Thin Solid Films 517 (2009) 6747. [17] J. Jang, in: C.R. Kagan, P. Andry (Eds.), Thin Film Transistors, Marcel Dekker, Inc, New York, 2003. [18] J.I. Pankove, Optical Processes in Semiconductors, Dover Publications Inc., New York, 1971. [19] H. Kim, D. Kim, Sol. Energy Mater. Sol. Cells 67 (2001) 297. [20] S.K.V. Zinoviev, O. Zelaya-Angel, Mater. Chem. Phys. 70 (2001) 100.
Contents lists available at ScienceDirect
Thin Solid Films j o u r n a l h o m e p a g e : w w w. e l s ev i e r. c o m / l o c a t e / t s f
Ammonia-free chemically deposited CdS films as active layers in thin film transistors G. Arreola-Jardón a, L.A. González b, L.A. García-Cerda c, B. Gnade d, M.A. Quevedo-López d,e, R. Ramírez-Bon a,⁎ a
Centro de Investigación y Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro., 76001, México Centro de Investigación en Física, Universidad de Sonora, Apdo. Postal 5-088, CP 83000, Hermosillo, Son., México Centro de Investigación en Química Aplicada, Blvd. Enrique Reyna Hermosillo No. 140, Saltillo, Coah. 25253, México d Material Science and Engineering, The University of Texas at Dallas. Richardson 75083, TX, USA e Departamento de Polímeros y Materiales, Universidad de Sonora, Apdo. Postal 130, CP 83000, Hermosillo, Sonora, México b c
a r t i c l e
i n f o
Article history: Received 8 January 2010 Received in revised form 11 August 2010 Accepted 16 August 2010 Available online 20 August 2010 Keywords: Cadmium sulfide Chemical bath deposition Field effect transistors Electrical properties and measurements
a b s t r a c t In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12–0.16 cm2V−1 s−1 and 8.8–25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8–8.8 cm2V−1 s−1 and the threshold voltage decreased to 8.4–12 V. Ion/Ioff for the annealed devices was approximately 105–106. © 2010 Elsevier B.V. All rights reserved.
1. Introduction The widespread application of flat panel displays has made thin film transistor (TFT) one of the most common devices employed in the electronics industry. In a flat panel display the role of the TFT is to individually control each pixel, for which amorphous silicon is the semiconductor active layer in the current active matrix displays. While amorphous silicon provides adequate performance and reliability for a voltage controlled device like a liquid crystal display, the performance is not adequate for current controlled devices such as an organic light emitting diode, therefore the search for alternative semiconductor materials as active layers in TFTs is still very relevant [1]. Metal chalcogenides such as CdS and CdSe have been studied as semiconductor active layers in TFTs since the early developments of TFTs [2]. More recently, interest in CdS films has been focused on their applications in CdS/CdTe and CdS/CuInxGa1 − xSe2 (CIGS) thin film solar cells. CdS has also been studied in TFT applications for many years [3–7]. Evaporated CdS active layers were used in early work, while chemical bath deposited CdS layers have been used in more recent work. Chemical bath deposition (CBD) provides a costeffective, low-temperature and large-area compatible processing technique for the growth of high quality semiconductor layers. In particular, chemically deposited CdS active layers have shown good performance in TFTs with values of field effect mobility in the range of 0.5–1.5 cm2V−1 s−1 [3–7], comparable to those of amorphous silicon. ⁎ Corresponding author. Tel.: +52 442 2119906; fax: +52 442 2119939. E-mail address: [email protected] (R. Ramírez-Bon). 0040-6090/$ – see front matter © 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2010.08.097
In these previous reports, the recipes generally include ammonia as the complexing agent. Subsequent thermal annealing is performed to improve the electrical properties. In previous papers we have reported the properties of chemically deposited CdS films from an ammonia-free cadmium chloride– sodium citrate–thiourea system [8–11]. We found that this system is very convenient for the growth of CdS films by CBD because it avoids the utilization of ammonia as the complexing agent, allowing a reduction in the amount of cadmium in the reaction solution. The properties of these CdS films are equivalent, or even better, than those of films obtained using conventional CBD recipes based on ammonia as the complexing agent for the cadmium ions. In recent papers our group, as well as others have shown the feasibility of using the ammonia-free chemically deposited CdS films as window layers in CdS–CdTe, CdS–CIGS and CdS sensitized thin film solar cells [12–14]. In this paper we used the cadmium chloride–sodium citrate–thiourea system to grow CdS active layers by CBD for field effect TFT. A p-Si/ SiO2/CdS device with a common bottom gate and Au source/drain contacts, with different channel lengths, was fabricated using lift-off processes. We determined the output responses of the CdS-based TFTs as a function of channel length and thermal annealing conditions. 2. Experimental details The TFTs were fabricated on a RCA cleaned p-Si wafer with a 100 nm thermal SiO2 layer as the dielectric layer of the device. The chemical deposition of the CdS layers on the p-Si/SiO2 substrates was done in a reactive solution prepared in a 100 ml beaker by the
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sequential addition of 15 ml of 0.05 M cadmium chloride (CdCl2, Baker, 99.3%), 15 ml of 0.5 M sodium citrate (C6H5O7Na3, Baker, 99.1%), 5 ml of 0.5 M potassium hydroxide (KOH, Baker, 89.13%), 5 ml of pH 10 buffer solution (Baker) and 7.5 ml of 0.5 M thiourea (CS (NH2)2, Baker, 99.6%). The solution was diluted with deionized water to complete a total volume of 100 ml. The beaker with the reaction solution was immersed in a water bath at 70 °C. The amount of cadmium in this reaction solution is 0.84 mg/ml, which is the optimum concentration for this ammonia-free system to obtain CdS layers with optimum crystalline properties, as shown in recent papers [15]. For the deposition of source and drain contacts, a photoresist layer was deposited on the CdS layer, cured, UV exposed through a shadow mask and developed. The shadow mask consists of pairs of rectangular patterns that represent sets of parallel electrodes (source and drain) whose separation (channel length) decreases from 80 to 20 μm. A 100 nm gold layer was deposited on each sample by e-beam evaporation. The gold source/drain contacts were formed using lift-off process. Chromium (10 nm) and gold (100 nm) were evaporated on the back side of the p-Si wafer to form the back side contact. In order to improve the electrical response of the semiconductor layer some devices were thermal annealed at 250 °C in forming gas for 1 h. The morphology of the semiconductor layer was studied using scanning electron microscopy (SEM). The thicknesses of the dielectric and semiconductor layers were determined using cross sectional SEM. The electrical response of the as-deposited and thermally annealed CdSbased TFTs was determined using current versus voltage measurements at room temperature in a probe station with a 4200 Keithley semiconductor parameter analyzer. 3. Results and discussion A schematic diagram of the final layer structure of the CdS-based TFT is shown in Fig. 1a). Source and drain Au contacts with two
different channel lengths (L), 80 and 40 μm, on top of the CdS layer are shown in Fig. 1b). The width (W) of the Au contacts is 450 μm. The SEM image in Fig. 2a) shows the surface morphology of the CdS layer. The surface of the films is smooth with nanocrystalline grains in a compact granular structure with very well-defined grain boundaries. These are characteristics of the ion-by-ion growth mechanism taking place during the chemical deposition process of the CdS layer [9,16]. An image of the cross section of the device is shown in Fig. 2b), where it is observed from top to bottom the semiconductor CdS layer, the SiO2 dielectric layer and the p-Si substrate. The thickness values were determined to be 110 and 100 nm for the CdS and SiO2 layers, respectively. The output characteristics of the CdS-based TFTs are shown in Fig. 3. The drain current (IDS) versus source–drain voltage (VDS) curves were measured from 0 to 40 V at several gate voltages (VGS), for devices with 80, 40 and 20 μm channel lengths. The family of IDS–VDS curves as a function of gate voltage shows that IDS saturates at pffiffiffiffiffiffi reasonable values of VDS. The IDS versus VGS is shown in Fig. 4. These curves were measured at a fixed VDS of 40 V. The linear region of these curves were fit to the following equation [17] 1= 2
IDS
=
Ci Wμ sat 1 = 2 ðVGS −VT Þ 2L
ð1Þ
to determine the channel mobility, μsat, and threshold voltage, VT, for the devices. In Eq. (1), which is valid for VDS N VGS − VT, Ci is the capacitance per unit area of the gate dielectric layer. The best fits to Eq. (1) are shown as dotted lines in this graph. The threshold voltage, which corresponds to the intersections of the dotted lines with the VGS-axis, decreases for the devices with a lower channel length. The values determined for VT are 25, 19.5, and 8.8 V for the devices with 80, 40, and 20 μm channel length, respectively. The TFT devices operate in the enhancement mode. In this mode, at VGS = 0 V, the device is in the off-state. The channel mobility, which is related to the
a)
200 nm
b)
CdS SiO2 p-Si 100 nm Fig. 1. a) Scheme of the cross section layer structure of the CdS-based thin film transistor. b) Top view image showing the CdS layer surface and a set of two source and drain gold contacts with different channel lengths, L = 40 and 80 μm, and W = 450 μm.
Fig. 2. a) SEM image showing the surface morphology of the CdS layer. b) SEM image showing the cross section of the device.
G. Arreola-Jardón et al. / Thin Solid Films 519 (2010) 517–520
As-deposited VDS=40 V 1) L=80 µm 2) L=40 µm 3) L=20 µm
10-5
35 V
6.0x10-7
L= 80 µm
4.0x10-7
3 0.004
10-6
30 V
2.0x10-7
25 V
10-7
2
0.0
b)
3.0x10-6
As-deposited 35 V
Current (A)
3
40 V
2.0x10-6
1
10-8
1
L= 40 µm 30 V
10-9
0.000 10
0
1.0x10-6 20 V 0.0
c)
As-deposited
40 V
1.5x10-5
35 V
1.0x10-5
L= 20 µm
30 V
20
30
Gate Voltage (V)
25 V
Current (A)
2
0.002
SqrtCurrent (A1/2)
40 V
Current (A)
Current (A)
As-deposited
a)
8.0x10-7
519
pffiffiffiffiffiffi Fig. 4. IDS versus VGS plots (right axis) for the as-deposited CdS-based TFTs with different channel lengths. The dotted straight lines correspond to the best linear fits to Eq. 1. Semi-log plots of IDS versus VGS (left axis) for the same devices.
Ioff = 106 were obtained [6]. Although our results show that chemically as-deposited CdS thin films yield good TFT devices, their electrical parameters are inferior to most of those in literature, even in the case of our best devices with channel length L = 20 μm. To
25 V 5.0x10-6
a)
20 V
Annealed L= 80 µm
40 V
20
30
Voltage (V) Fig. 3. Characteristic IDS versus VDS plots for several values of VGS for the as-deposited CdS-based TFTs with a) 80, b) 40 and c) 20 μm channel lengths.
slope of the dotted line, was 0.13, 0.12 and 0.16 cm2V−1 s−1, for the devices with 80, 40, and 20 μm channel lengths, respectively. Fig. 4 also shows semi-log plots of IDS versus VGS for the three devices, measured at VDS 40 V. The lowest value of IDS corresponding to the offstate of the devices (off-current, Ioff) is 10−9 A, while the on-state currents are 10−5–10−6 A, depending on channel length. Thus the current ratio Ion/Ioff of the devices is of the order of 103–104. The electron mobility of bulk CdS is 210 cm2V−1 s−1 [18], much higher than the field effect mobility measured in CdS-based TFTs. The main reason for lower mobility is the polycrystalline nature of the CdS layers in these devices. As is well known, the grain boundaries in polycrystalline semiconductors have an impact on the electrical transport because they act as dispersion and trapping centers for the charge carriers, reducing the mobility. Thermal treatments at a high temperature in different atmospheres can enhance the crystallinity and passivate defects, including those at the grain boundaries in polycrystalline semiconductors. CdS-based TFTs annealed at 300 °C at a low pressure for 1 h have the characteristics: μsat = 0.5 cm2V−1 s−1, VT = 14 V and Ion/Ioff = 107 [7], devices annealed in vacuum at 200 °C had a mobility of 1.25 cm2V−1 s−1 [4]. No mention of the other parameters were included in this reference. Some reports have included two annealing steps in the TFT fabrication process, before and after deposition of source and drain contacts [3,6]. The first anneal is done to enhance the crystallinity of the CdS layer and the second one to improve the source/drain resistance. By using two rapid thermal anneals at 500 °C in Ar for 5 min, before and after Al contact deposition, devices with μsat = 1.5 cm2V−1 s−1, VT = 14 V and Ion/
30 V 2.0x10-4
20 V 10 V
0.0 1.0x10-3
b)
8.0x10-4
Current (A)
10
Annealed L= 40 µm
40 V
6.0x10-4
30 V
4.0x10-4 20 V
2.0x10-4
10 V 0.0
c)
1.0x10-3
Current (A)
0
Current (A)
4.0x10-4
0.0
Annealed L= 20 µm
40 V
8.0x10-4 6.0x10-4 30 V 4.0x10-4 2.0x10-4
20 V 10 V
0.0 0
10
20
30
Voltage (V) Fig. 5. Characteristic IDS versus VDS plots for several values of VGS for the CdS-based TFTs annealed at 250 °C in forming gas for 1 h with a) 80, b) 40 and c) 20 μm channel lengths.
520
G. Arreola-Jardón et al. / Thin Solid Films 519 (2010) 517–520
Annealed
Current (A)
10-4
VDS=40 V
1) L=80 µm 2) L=40 µm 3) L=20 µm
0.04
3
10-5
3
1
10-6
0.02
2
10-7
SqrtCurrent (A1/2)
10-3
1
2 10-8
0.00
10-9
0
10
20
30
Gate Voltage (V) pffiffiffiffiffiffi Fig. 6. IDS versus VGS plots (solid lines, right axis scale) for the thermally annealed CdSbased TFTs with different channel lengths. The dotted straight lines correspond to the best linear fits to Eq. 1. Semi-log plots of IDS versus VGS (dashes lines, left axis scale) for the same devices.
improve the device performance we annealed the devices in forming gas (N2(90%) + H2(10%)) at 250 ° C for 1 h. The thermal annealing was done on the finished devices, so it impacted the CdS semiconductor layer and the source/drain Au contacts. Fig. 5 shows the family of IDS–VDS curves, measured at several values of VGS, for the thermally annealed CdS-based devices with a) 80, b) 40 and c) 20 μm channel lengths. The thermal annealing significantly increased the drain current in the devices. The devices saturate at IDS levels between 5 × 10−4 and 1 × 10−3 A, N100× higher than in the unannealed devices. The transfer characteristic curves for the annealed devices, measured at VDS = 40 V, with 80, 40 and 20 μm pffiffiffiffiffiffi channel lengths are shown in Fig. 6. The IDS versus VGS curves are plotted as solid lines with the best fits to Eq. 1 in the linear region of these curves plotted as dotted lines (right axis). From the parameters of the linear fits the following electrical characteristics were determined; μsat = 8.8, 6.2 and 4.8 cm2V−1 s−1 and VT = 12, 10.6 and 8.4 V for the annealed devices with L = 80, 40 and 20 mm, respectively. The mobility of the annealed device improves N10× and VT in the annealed devices is sensitive to their channel length. The IDS versus VGS curves plotted as dashed lines in the semi-log graph of Fig. 6 (left axis) show that the off-current of the annealed devices is still 10−9 A, but the on-current increases to 10−4–10−3 A. The thermal annealing process increased the Ion/Ioff ratio of the devices to 105–106. The results described above show that the CdS films deposited using the ammonia-free sodium citrate-based CBD process have good performance as the semiconductor layer in TFT devices. The thermal annealing process in forming gas at a relatively low temperature (250 °C) improved the performance of the devices, with electrical parameters comparable to those reported in literature for chemically deposited CdS-based TFTs. We can assign the device improvement mainly to the benefits of the forming gas annealing on the CdS layer. As it has been reported in several papers [19,20], annealing in forming gas passivates interface states, and chemi-adsorbed impurities at the
grain boundaries in polycrystalline semiconductors with a consequent positive impact on their electrical conductivity and crystalline structure. The ammonia-free CBD process described in this work provides very good quality CdS layers with the advantages of the ammonia elimination and reduced cadmium, making the process promising for application to the development of CdS-based TFT devices. 4. Conclusions In this paper we have reported the electrical performance of chemically deposited CdS layers, obtained from an ammonia-free CBD process, as the active semiconductor layer in field effect thin film transistors. Devices with as-deposited CdS film layers showed good electrical behavior with the following parameters: μsat = 0.13, 0.12 and 0.16 cm2V−1 s−1 , VT = are 25, 19.5, and 8.8 V and Ion/ Ioff ~ 103– 104, for channel lengths of 80, 40 and 20 μm, respectively. The electrical characteristics of the CdS-based TFTs were improved by thermal annealing in forming gas at 250 °C for 1 h. After annealing the measured electrical parameters on the devices were; μsat = 8.8, 6.2 and 4.8 cm2V−1 s−1, VT = 12, 10.6 and 8.4 V and Ion/Ioff ~ 105–106 for the channel lengths of 80, 40 and 20 μm, respectively. Based on these results and on the advantages of the ammonia-free CBD process for the growth of CdS layers, we conclude that it is quite promising for the cost-effective development of TFT devices. Acknowledgements This work was supported by CONACYT through the Becas Mixtas and Sabbatical Programs. The technical assistance of C.A. AvilaHerrera is also acknowledged. References [1] R.E.I. Schropp, B. Stannowski, J.K. Rath, J. Non-Cryst. Solids 299–302 (2002) 1304. [2] W.E. Howard, in: C.R. Kagan, P. Andry (Eds.), Thin Film Transistors, Marcel Dekker, Inc, New York, 2003. [3] F.Y. Gan, I. Shih, IEEE Trans. Electron Devices 49 (2002) 15. [4] C. Voss, S. Subramanian, C.-H. Chang, J. Appl. Phys. 96 (2004) 5819. [5] B. Mereu, G. Sarau, E. Pentia, V. Draghici, M. Lisca, T. Botila, L. Pintilie, Mater. Sci. Eng. B 109 (2004) 260. [6] Y.-J. Chang, C.L. Munsee, G.S. Herman, J.F. Wager, P. Mugdur, D.-H. Lee, C.-H. Chang, Surf. Interface Anal. 37 (2005) 398. [7] J.H. Lee, J.W. Yoon, I.G. Kim, J.S. Oh, H.J. Nam, D.Y. Jung, Thin Solid Films 516 (2008) 6492. [8] M.B. Ortuño-López, J.J. Valenzuela-Jáuregui, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 429 (2003) 34. [9] M.B. Ortuño-López, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 457 (2004) 278. [10] M.B. Ortuño-López, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Vacuum 76 (2004) 181. [11] M.G. Sandoval-Paz, M. Sotelo-Lerma, A. Mendoza-Galván, R. Ramírez-Bon, Thin Solid Films 515 (2007) 3356. [12] H. Komaki, A. Yamada, K. Sakurai, S. Ishizuka, Y. Kamikawa-Shimizu, K. Matsubara, H. Shibata, S. Niki, Phys. Status Solidi A 206 (2009) 1072. [13] M.F. Hossain, S. Biswas, T. Takahashi, Thin Solid Films 518 (2009) 1599. [14] R. Ochoa-Landín, J. Sastre-Hernández, O. Vigil-Galan, R. Ramírez-Bon, Sol. Energy 84 (2010) 208. [15] R. Ochoa-Landín, M.G. Sandoval-Paz, M.B. Ortuño-López, M. Sotelo-Lerma, R. Ramírez-Bon, J. Phys. Chem. Solids 70 (2009) 1034. [16] M.G. Sandoval-Paz, R. Ramírez-Bon, Thin Solid Films 517 (2009) 6747. [17] J. Jang, in: C.R. Kagan, P. Andry (Eds.), Thin Film Transistors, Marcel Dekker, Inc, New York, 2003. [18] J.I. Pankove, Optical Processes in Semiconductors, Dover Publications Inc., New York, 1971. [19] H. Kim, D. Kim, Sol. Energy Mater. Sol. Cells 67 (2001) 297. [20] S.K.V. Zinoviev, O. Zelaya-Angel, Mater. Chem. Phys. 70 (2001) 100.