An AI constraint network-based approach to bed-of-nails DFT for digital circuit design

World Abstracts on Microelectronics and Reliability product is modeled, optimized, and controlled using a methodology called "Multiple Response Surfaces" which may be used to characterize the results of an experimental design. Multiple, loworder polynomial models are used to model the output characteristics at each of several sites within a batch of product. The uniformity model is then obtained by manipulating these multiple models. The Multiple Response Surfaces approach is compared to the traditional method of fitting a single high-order polynomial to the calculated uniformity. Experimental results on several processes, confirm the expectation that similar or improved modeling accuracy is obtained with fewer data points using the new methodology due to the ability to use low-order models. Characteristics of the Multiple Response Surfaces approach including noise immunity and restrictions to classes of model forms are examined both analytically and in application to plasma etching, silicon epitaxy, tungsten CVD and the simulation of polysilicon LPCVD.

Systematic design of phase-shifting masks with extended depth of focus and/or shifted focus plane. YONG LIU, ANTON PFAU and AVIDEHZAKHOR. I E E E Transactions

on

Semiconductor

Manufacturing,

6(1), 1 (1993). We propose an optimization based algorithm for designing phase-shifting masks. Our approach is an extension of our previous work in the sense that the intensity image is optimized at a number of optical planes rather than just the focus plane. In addition, our algorithm can be used to design masks with shifted focus plane and/or extended depth of focus. We also propose the concept of "dual mask" and show its consequences to practical phase-shifting mask design. Finally we show examples of our proposed design techniques for single line phase connectors, cross phase connectors, contact holes and bright lines. Simulation and experimental results verify the capability of our design technique to extend depth of focus and shift the focus plane.

The effect of fan-reliability and cooling-performance on electronic-chassis reliability. JOHN M. HOGAN. I E E E Transactions on Reliability, 42(1), 172 (1993). This paper develops a tractable model for predicting the failure rates of electronic chassis cooled by fans with finite failure rates. The model accounts for two regimes prior to electronics failure: (1) The electronic chassis is operated at a temperature which occurs with a fan that is operational; (2) The electronic chassis is operated at a temperature which occurs when the fan has failed. Fan failures alone do not constitute a failure of the chassis. Such a model applies where cooling fans are not actively monitored and their failure is noticed only during the maintenance associated with an electronic failure of the chassis; i.e., the model accounts for the fact that the electronics in general continues to

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operate for a period of time following a fan failure. The model directly applies to cost/benefit studies in electronics packaging including the determination of the improvement in MTBF to be anticipated when a chassis is implemented with a cooling fan, and the determination of the performance benefit to be anticipated when fans are actively monitored and replaced upon failure.

An AI constraint network-based approach to bed-ofnails DFT for digital circuit design. J. BOWEN, D. BAHLER and A. DHOLAKIA. Computers and Electrical Engineering, 19(2), 73 (1993). One approach to design for testability (DFT) is to provide on-line D F T advice systems which can give designers the kind of feedback that would be provided by test engineers. This paper presents an approach to implementing such systems on an AI programming technology called constraint networks. We illustrate the approach by outlining some aspects of the implementation of RICK, a bed-of-nails DFT advisor which advises printed wiring board (PWB) designers by interjecting testability-oriented feedback throughout the design activity. Automated malfunction diagnosis of semiconductor fabrication equipment: a plasma etch application. GARY S. MAY and COSTASJ. SPANOS. I E E E Transactions on Semiconductor Manufacturing, 6(1), 28 (1993). In-line measurements and electrical test data have historically been used to detect process fluctuations in an integrated circuit manufacturing facility. Unfortunately, these methods alone cannot rapidly identify possible problems in processes with a very narrow range of acceptable performance. When unreliable equipment performance causes processes to vary beyond desired limits, product quality is jeopardized. It is therefore essential that root causes for the malfunctions be diagnosed and corrected quickly to prevent expensive misprocessing. This paper presents a general methodology for the automated diagnosis of integrated circuit fabrication equipment. This technique combines the best aspects of quantitative algorithmic diagnosis and qualitative knowledge-based approaches. Evidence from equipment maintenance history, realtime tool data and in-line measurements are integrated using evidential reasoning. This methodology is applied to the identification of faults in the Lam Research Autoetch 490 automated plasma etching system located in the Berkeley Microfabrication Laboratory. A layout-driven yield predictor and fault generator for VLSI. ALEXANDERR. DALALet al. I E E E Transactions on Semiconductor Manufacturing, 6(1), 77 (1993). IC faults arise from manufacturing defects. Layout analysis is required to determine the yield that is limited by these defects and the probability-graded fault lists that can be used to determine the optimal testing sequence. This requires (1) Accurate