An analysis of interconnect line capacitance and coupling for VLSI circuits

SolrC.!hfe Elecrroni~s Vol. 27. Nos. 8/9. Prinrcd in Great Britain

pp. 741-749.

1984 0

0038%1101/84 $3.00 + 00 1984 Pergamon Press Ltd.

AN ANALYSIS OF INTERCONNECT LINE CAPACITANCE AND COUPLING FOR VLSI CIRCUITS E. T.

LEWIS

Raytheon Co., Microelectronics Center, Bedford, MA 01730, U.S.A. (Received 16 November 1982)

Abstract-As the density, complexity, and speed of VLSI circuits are continuing to increase, the management of on-chip interconnects becomes of paramount concern to the I.C. designer, especially with respect to internal noise immunity. This paper presents two methods for analyzing and predicting the line-to-line coupling between high-speed VLSI interconnects using distributional and lumped element analysis techniques. In a broader sense, the analyses presented provide all pertinent line capacitances and inductances needed to characterize any array of interconnect. The basic model consists of representing the interconnects as a regular periodic array, considering the worst-case interaction occurring between two adjacent lines. It is shown that the proximity of a ground plane is essential in achieving acceptable ( > 20 db) isolation between interconnects that are used specifically for reasonably long data and control distribution functions. This translates to the eventual establishment of scaling rules for linewidth and spacing with respect to field oxide thickness. 1. INTRODUCTION

VLSI circuit a significant portion of the chip area is generally used for data and control signal distribution. In order to minimize the percentage of the chip area required for this communication function, the partitioning of the chip into functional data blocks that tend to minimize the interconnect overhead is always one of the main design goals. However, even for the most optimally architectured designs, interconnects of varying lengths and density are required (often with appreciable length and periodicity). This combination of factors results in a concern for internal noise immunity, i.e. line-to-line interaction, or coupling. ‘This concern becomes most acute as the edge speeds of the data being transmitted approach the region in which the interconnects must be treated distributionally, i.e. as transmission lines. Such a condition occurs when the rise or fall time, rR, rF of the digital signal approaches the characteristic line propagation delay constant, tPd Tagis simply the reciprocal of the phase velocity along the interconnect. As the data enters or leaves the chip at the next level of signal communication (the hybrid substrate, printed circuit board, or other chip-to-chip communication path) the concern for signal isolation is ever present. Many design guidelines exist for this level of interconnect design, based on well established transmission line theory. In fact, many approaches have been considered to enhance the density of the external interconnect structures that can accommodate a high chip I/O density, and, yet preserve the signal speed while assuring adequate isolation for high speed data communication[l, 21. At the chip level the interconnect design must consider similar problems, whether distributional, or nondistributional (lumped) in character. The basic model of an on-chip signal group is shown in Fig. l(a). Here, it is shown as a regular periodic array, but, in general, In any reasonably

dense, multifunction

it can consist of variable widths and spacings. Figure 1(b) shows a simple static capacitor model of this array while Fig. l(c) shows it as a coupled transmission line. In the analyses to follow both models will be considered, and it will be shown that the simple static capacitor representation of the coupled structure is an adequate representation for worst-case design purposes. In fact, the analyses to be presented will provide all pertinent line capacitances and inductances needed to fully characterize any interconnect array, whether distributed or lumped. To this can be added the effects of signal attenuation[l, 21 and crossover (multilevel) capacitance. Note that in Fig. l(a) a conducting plane is assumed to exist at the oxide-silicon substrate boundary which confines the induced fields to regions above the silicon surface. In general, this is an adequate assumption since the silicon surface concentration must normally be enhanced for field control. 2. ANALYSIS

OF THE COUPLED TRANSMISSION

LINE

MODEL

2.1 Basic considerations In order to properly analyze a periodic array of interconnect lines which have distributional characteristics, the system can be viewed as a coupled microstrip structure. In its most elemental form this structure consists of only two adjacent lines which can support two different modes of propagation, each with different characteristic impedances and phase velocities. If the lines are symmetric the two modes of propagation reduce to even and odd modes corresponding to an even and odd symmetry about a plane which can be replaced by a magnetic or electric wall for the purpose of analysis, as shown in Fig. 2. For reference purposes an excellent treatment of this subject can be found in [3] which also has an extensive set of references to much of the original work in this area. The analysis to be presented in this

E. T. LEWIS

742 t--+-+-t---I-s-l-w--)1

t

OXIDE

h 1,

,

,

,

,

,

,

,

,

,

,

,

,

,

,

,

,

,

SILICON

LINE0

n+ OR P’

LINE

@

LINE@

LINE

Fig.

I. Periodic chip interconnect

structure, (a) basic on-chip interconnect line array, model, (c) coupled transmission line model.

ELECTRIC --

--

-

EVEN

MAGNETIC

FIELD FIELD

LINES LINES

MODE

ELECTRIC

ODD

(b) coupled

WALL

MODE

Fig. 2. Even and odd mode field configurations

in coupled

microstrip

lines.

capacitor

Analysis of capacitance and coupling for VLSI circuits section is an application of the analysis summaries found in Ref. [3]. It should be noted that the coupling between two adjacent lines with no nearest neighbors is greater than the equivalent coupling that would occur in a periodic array, since field sharing would be expanded to include the other conductors in the system. Thus, the analysis of only the two-line coupled structure would yield a good baseline (worst-case) for VLSI interconnect design purposes. As a start on this analysis let us define some of the pertinent baseline parameters from dispersive transmission line theory. It is known from elemental symmetric line coupler analysis that the even and odd modes of propagation can be characterized by the following elements. characteristic impedance; Z, s even mode Z,, 3 odd mode characteristic impedance; C,, C, = even and odd mode capacitances; L,, L, = even and odd mode inductances; v,, v, = even and odd mode phase velocities. Furthermore, from basic theory it can be shown that the voltage coupling between two adjacent lines is given by: -T?e- ZOO kc=----ZO, + -TxJ

(1)

The even and odd mode characteristic impedances and associated phase velocities can be related to the elemental inductances and capacitances as follows: z,,=

2 c

$ Z0, =

&J J- G

“e=& vO=&.

(2)

(3)

(4)

(5)

With reference to Fig. 2, if we assume that crZ= c, (air) and t,, = t, (oxide), then effective dielectric constants can be defined for each mode as:

743

Now, using the above definitions and relationships it can be shown that the coupling coefficient, k,, can be expressed as: -

vz .

k,.=

c/-

,/$

(8)

c,

Thus, with only a calculation of the even and odd mode capacitances with no dielectric interface, and relative effective associated dielectric constants, the line coupling can be determined. For VLSI interconnects, the goal is to keep this small (k, 5 -20 dB or look). Note that the determination of the effective dielectric constants does require a solution for the actual boundary condition. However, it has been shown (3) that for the simplified system described where L,*< t,, the even mode dielectric constant is always higher than is odd mode counterpart because of the higher density of electric field lines in region 2 over region 1 for the odd mode (see Fig. 2). Thus, for this condition the coupling is reduced as the difference between the individual effective dielectric constants is increased. In a practical VLSI chip all interconnects usually have a dielectric overlay whose dielectric constant is the same as that of the underlying oxide. This tends to equalize the phase velocities of the even and odd modes, yielding equalized effective dielectric constants. In fact, this technique (dielectric overlays) is used for the construction of microwave line couplers to equalize the phase velocities, thus improving directivity and midband coupling. Thus, by simply calculating the even and odd mode capacitances in a vacuum (-air) the worst-case coupling coefficient can be determined. With a dielectric overlay, it is convenient to assume that no dielectric interface exists and the total propagation media is the dielectric. With this assumption worst-case self and mutual capacitances can be determined for overall design purposes. 2.2 Even and odd mode capacitance model The even and odd mode capacitances of the basic line coupler can be determined with the aid of the models shown in Fig. 3. In Fig. 3(a) the even mode model yields (all per unit length)

c,=c,+c,+c; and for the odd mode model of Fig. 3(b) where,

co= c, + c/+ c,, + c,,.

CPU,C,’ = even and odd mode capacitances when e, = e0 (no dielectric interface). Since we are assuming a non-magnetic medium, P = k, and,

C, is simply the parallel plate capacitance between the strip and the reference plane. C, is the fringe capacitance of a simple microstrip line given by:

L, = L, C,=L

L, = L/.

c,-c 2

(11)

E.

744

T.

LEWIS

MAGNETIC WALL I

ELECTRIC WALL

Fig. 3. Capacitance models for determining,

(a) even mode capacitance,

where, CM is the microstrip capacitance whose formulae have been developed[3] as (for I = 0)

Gff

capacitance.

where,

A=exp[-O.lexp(2.33-2.53:):

for w > 2h:

C.&f =

(b) odd mode

1

In most cases C; can be simplified:

;+1.393+0.66ln(;+l.444)}

(16)

for w < 2h: s

(12) where.

t eff

,+,2h

61 fE2 =_+?q

2

W

i

- 1,2

(13)

>

For the odd mode capacitance two additional elements are required. C,, describes the capacitance in region 2, and C,, describes the capacitance in region 1. These capacitances are functionally different and their forms[3] are given by the following simplified equations. For CR, we have,

C, is given by the simple equation:

c, = L,

;.

(b,=~ln{2~j

forO
(14)

In these equations the actual permittivity values are being used (not relative). Note that if t, = 62 then t,+c,, as we have already discussed. C; is a modified fringe capacitance (magnetic wall influence) whose value[3] can be determined by:

where, k=

and.

s/h s/h + 2w/h

745

Analysis of capacitance and coupling for VLSI circuits The above equations are simplifications of the results of Owyang and Wu[4] for the capacitance of a slotline of width W.

(18) where K (k) and K (k’) are the elliptic function and its complement, respectively. For C,, we have

The capacitance elements defined above can now be used to determine all pertinent interconnect design information (exclusive of line loss and intrinsic line delay.) It should be noted that the even and odd mode capacitances can be used to determine the self and mutual capacitances and inductances if desired. These are given by:

+ 0.65 C,

+{$$+[1-@I+

(25) (19) and

The above set of capacitance equations apply only when the thickness of the interconnect line is small compared to its width. For the case when lines have a reasonable thickness (the typical case in a VSLI chip) some of the capacitance formulae must be adjusted. C, remains the same functionally with a modification to C, (and CJ. C,(t) = c, + C#) + c;ct>

(20)

where,

(26)

The inductance formulae were derived from the earlier relationships. For the case in which & = c;~ the coupling coefficient reduces to the equation

2C,(t) = CM(f) -6, ;

(27)

CM(t) has the same functional forms as for t = 0, except for modifications to the w/h ratio and the effective permittivity. These are given by[3]

( t>

we w +!A?! l+ln2h _=_

(21)

c&t) = L,tf(t = 0) + c

(22)

h

7rh

h

a very simple result. The self and mutual elements are useable for performing lumped circuit analysis for those cases in which tR, rF < r,,pd. In the next section the analysis of the coupled capacitor model will be considered for which a TEM mode of propagation is assumed.

and, 3. ANALYSIS OF THE COUPLED

where. c

=

Cl -

62

(t/h)

4.6_’

Note that for the worst case approach (6, = Q) we have that

The odd mode capacitance is modified by CAt) (also C,,(t)) and a new term, C,,, the gap capacitance, must be added. Thus,

CAPACITOR

V, = A,,Q, + A,zQz + . c, = c, + qt,

+ C,,(t) + c,, + c,,

(23)

MODEL

The analysis of this representation of the coupled interconnect structure has been presented in an earlier paper[l]. In essence the model assumes only one mode of propagation (TEM) but makes additional assumptions on the array geometry. It draws on earlier work[5] that permits the representation of a linear array of charged rectangular structures as round conductor equivalents. This was found permissible if w I 2h (Fig. la). It simplifies the analysis considerably. The approach uses the fact that in a multiconductor system superposition may be used to determine the charge-voltage relationships. This is expressed as follows: . + A, Qn (28) k=A,,Q,+A,,Q,+

.....

+A,Q,.

where C,, can be simply represented as c,, = 2c, t 1s.

(24)

A, are coefficients relating the various charges to an induced potential on any conductor in the system.

E. T.

146

The A, coefficients ,&

are defined as:

(29)

= 0,except I =, Q, allCJ,

Using the equivalent structure shown in Fig. 4 where the rectangular to circular conversion shown in Fig. 5 can be applied (w 2 2h) then the A, coefficients can be determined using static field analysis. One such technique is the well known Method of Images. This yields: A,, =-

1

271k

1,3! a,

LEWIS

as defined earlier for a microstrip system (eqn 13). The various elements of the system can be determined by first establishing the proper boundary conditions, and then solving for the parameter of interest. The self or mutual capacita .nces can be determined as follows:

The line coupling following:

can be determined

by solving

the

(30) k,.=1; 2)I p,=o

where. Cl

+

61-62

62

Gff ~-----+---2

As an example, consider the pair of coupled lines discussed in the last section. The charge-voltage equations for this system are?:

-‘j2

2

(32)

v, =

A,,Q, + A,,Q,

Vz =

AnQ, + A,,Q,.

‘/‘We could transform this set of equations into a set ifde;s[2’!“] yielding capacitance coefficients C, by matrix

(33)

Fig. 4. Microstrip array and IIS equlvalcnt.

0.8

-

0

0.2

0.4

0.6

0.8

c

Fig. 5. Equivalence

between

a rectangular

and a circular

cross-section.

10

Analysis of capacitance and coupling for VLSI circuits The self capacitance of, say line 1, is: c,,

=QI 5

A22

VT=0

=

Ad22

coupling parameters for VLSI interconnects, consider the representation for two typical metal interconnect line structures shown in Fig. 6. In this figure, two cases are established. In both situations the field oxide thickness is maintained a constant and both have oxide overlays. Case @ is representing the situation for which a greater line density is being achieved with no scaling in the thickness of the field oxide. Since an oxide overlay is shown to exist, we can treat the analysis as one of uniform permittivity where Gff= 60, = 4,. The thickness of the metal is assumed to be 0.5 pm for each. Note that if the interconnect was polysilicon, the same capacitance analysis can be used, but we must add distributed resistance to the final model for line delay and attenuationll, 21.

(34)

-&A,,

The mutual capacitance between the two lines is:

cml.2 =

I II Q2 -

V,

A21

v,=o

= A,,&

-

(35)

4,-b

The line coupling is:

k,+ I

Q*=O

=-. A21 Al,

(36)

4.2 Distributed even-odd mode analysis Applying the equations developed in Section 2 to both cases, we have the following results.

Note that for symmetric lines (A,, = A,,)

k,=> s

747

(erg>

(37)

Case @

s

as was shown in the previous section for the even and odd mode distributed analysis when even and odd mode propagation velocities are equalized. This method of analysis permits the geometrical structures to be non-symmetric, but does assume only one mode of propagation. The determination of the A, coefficients becomes much more complex if the simplified models (rectangular to circular geometries for w I 2 h) cannot be applied. Fortunately, this is the case when line coupling is of greatest concern. 4. APPLICATION

OF THE MODELS INTERCONNECTS

C, = 0.708 pf/cm; CPo= 0.177 pf/cm C,=P-C&4-C,_ 2

(C, = 1.645 pf/cm; CM”= 0.411 pf/cm (&I = 60X= 4%) C; = 0.3 13 pf/cm; (C$

TO VLSI

= 0.0783 pf/cm

C,, = 0.554 p pf/cm; C;, = 0.139 pf/cm

4.1 VLSI interconnect model As an example of the use of the models and their relative merits in determining the capacitance and

OXIDE

t /

C,, = 0.302 pf/cm; C;, = 0.0032 pf/cm C,, = 0.118 pf/cm; C;, = 0.023 pf/cm.

OVERLAY,E~~

FIELD

/I///

0.469 pf/cm; C; = 0.177 pf/cm

/

OXIDE.

/

fOX

/

/

/I/

/

SILICON n+ OR P+

Fig. 6. The interconnect lines in a VLSI chip

/

E. T.

748

LEWIS

have:

Therefore, C, = C, + C, + C; = 1.49 pf/cm; Cea = 0.372 pf/cm

CT, =

A 22 A,,Az

- AuAz,

C, = C, + c, + c,, + c,, f c,, = 2.151 pf/cm: C,’ = 0.459 pf/cm

C, = 1 (C, + C,) = 1.82 pf/cm; Ct = 0.416 pf/cm

where, 1 A,, = A,, = ~ 2n+

C, = i (C, - C,) = 0.331 pf/cm; C,”

kV=+?=

a

1 ,n J(2)* + d’ A,, = A,, = __ d 27%

= 0.0435 pf/cm c U

lnE

0.0435 = 0.1046 = - 19.6 dB 0.416

lnz

a

C.4 = 2Wf ln 2h d@@= ad

Case @

k =lnJ@Zj%P Y In?

C, = 0.472 pf/cm; C,,’ = 0.118 pf/cm CM-q_ C,=----_2

0.444 pf/cm; Cy = 0.111 pf/cm For the above,

2hd

,n

a&ZjGF

!(

>

a we shall assume

tee z t,,.

(C, = I .36 pf/cm; C,” = 0.34 pf/cm Case (TJ

t 1 w =;;d=6pm;h

C; = 0.254 pf/cm; (C;)’ = 0.0635 pf/cm C,, = 0.554 pf/cm; C;, = 0.139 pf/cm

From

C,, = 0.307 pf/cm; C;, = 0.0081 pf/cm C$ = 0.177 pf/cm;

Fig. 5, (do/w) = 0.65-+a = 0.975 pm.

Therefore, C, = 2 pf/cm

C,R”I = 0.0443 pf/cm

C, = 0.2 pf/cm

Therefore,

k,=

C, = 1.17 pf/cm; C,’ = 0.2925 pf/cm

-2OdB.

Case @

C, = 1.955 pf/cm; C,’ = 0.4204 pf/cm

t

C, = 1.563 pf/cm; Cp = 0.356 pf/cm C, = 0.393 pf/cm; C,,,O= 0.064 pf/cm

k, = g

= 1.5pm.

From

= 0.18 = - 14.9 dB.

1

Fig. 5, (d,,/w) = 0.73+a

= 0.73 pm

Therefore, C, = 1.6 pf/cm

As can be seen, a change in the surface scaling without a comparable in-depth scahng (reduction of field oxide thickness) can yield a marginal worst-case, on-chip noise immunity. Now let us perform a similar calculation using the capacitor model described in Section 3.

4.3 Coupled capacitor analysis For the same symmetric two conductor

system we

c, = 0.255 pf/cm k,= 5.

-16dB.

DISCUSSION

AND SUMMARY

Except for small differences, which could be related to many of the various model assumptions (for example, see Ref. [3]), the correlation between both methods is very good (especially for C, and k,).

Analysis of capacitance and coupling for VLSI circuits In both methods, the assumption of c& x L,, is not exact since some of the field lines do extend beyond the dielectric overlay which should yield a lower effective dielectric constant. This would imply that the absolute values of self and mutual line capacitance would be lower in an actual VLSI chip. However, the line coupling coefficients should be reasonably close to actual (worst-case) as discussed earlier. It can be observed that the largest differences between the two models appear in the prediction of mutual capacitance. This difference becomes less as w/h increases. The difference would also be reduced if the effective dielectric constant used in the even and odd mode approach was reduced, representing the actual environment of a limited thickness dielectric overlay. In any case, the isolation predictions agree very closely. One final comment can be made with respect to the isolation concerns for other device technologies, specifically for SOS and GaAs based circuit tech-

149

nologies. If this analysis is applied to these structural forms, where the supporting material in the field regions is essentially “insulating”, one finds that for closely spaced interconnect lines the isolation is very low ( a great amount of line-to-line interaction). Thus, as the edge speeds become exceedingly short, the onchip noise immunity for these circuit technologies should be poor, again, for those cases in which a significant amount of signal bussing is required. REFERENCES

1. E. T. Lewis, IEEE Trans. CHMT, CHMT (4), 441450

(1979). 2. E. T. Lewis, “VHSIC Packaging”, 4th Digital Avionics Conference, St. Louis, MO., Nov. 1981. 3. K. C. Gupta, R. Garg and I. J. Bahl, Microstrip and Slotlines, Artech, (1979). 4. G. H. Owyang and T. T. Wu, IRE Trans. AP-6, 49-55, 1958. 5. Final Report on U.S. Army Contract DA-36-039

SC-63232, Strip Transmission Lines and Components, Feb. 1967, Stanford Research Institute.