An analytical approach to dynamic crosstalk in coupled interconnects

ARTICLE IN PRESS Microelectronics Journal 41 (2010) 85–92

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An analytical approach to dynamic crosstalk in coupled interconnects Brajesh Kumar Kaushik a,, Sankar Sarkar b,1, Rajendra Prasad Agarwal c,2, R.C. Joshi d,3 a

Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee- 247667 Uttarakhand India School of Electronics Engineering, Shobhit University, NH-58, Modipuram, Meerut - 250 110, Uttar Pradesh, India Shobhit University, NH-58, Modipuram, Meerut - 250 110, Uttar Pradesh, India d Department of Electronics and Computer Engineering, Indian Institute of Technology-Roorkee, Roorkee-247667 Uttarakhand India b c

a r t i c l e in fo

abstract

Article history: Received 10 October 2008 Received in revised form 14 October 2009 Accepted 16 December 2009 Available online 6 February 2010

This paper deals with waveform analysis, crosstalk peak and delay estimation of CMOS gate driven capacitively and inductively coupled interconnects. Simultaneously switching inputs for the coupled interconnects are considered. A transmission line-based coupled model of interconnect is used for analysis. Alpha-power Law model of MOS transistor is used to represent the transistors in CMOS driver. Peaks and delays at far-end of victim line are estimated for conditions when the inputs to the two coupled interconnects are switching in-phase and out-of-phase. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy, such as not more than 5% error in crosstalk peak estimation. & 2009 Elsevier Ltd. All rights reserved.

keywords: Coupled transmission lines Crosstalk VLSI CAD Interconnections Signal integrity

1. Introduction The function of interconnects or wiring systems is to distribute clock and other signals and to provide power/ground to and among the various circuits/systems functions on the chip. The performance such as time delay and power dissipation of a highspeed chip is highly dependent on the interconnects, which connect different macro cells within a VLSI chip. To escape prohibitively large delays, designers scale down global wire dimensions more sluggishly than the transistor dimensions [1]. Wide wires are frequently encountered in global and semi-global interconnects in upper metal layers. These wires are low resistive lines that can exhibit significant inductive effects [1]. Due to presence of these inductive effects, the new generation VLSI designers have been forced to model interconnects as distributed RLC transmission lines [2–6]. These RLC transmission lines when running parallel to each other have substantial capacitive and inductive couplings leading to crosstalk between the lines. The elimination of crosstalk is thus a concern of interconnect designer. The most important requirement of a circuit design is a thorough understanding of the interdependence of the circuit

 Corresponding author. Tel.: + 91 94 12 30 76 94; fax: + 91 1332 273560.

E-mail addresses: [email protected] (B.K. Kaushik), [email protected] (S. Sarkar), [email protected] (R.P. Agarwal), [email protected] (R.C. Joshi). 1 Tel.: + 91 94 58 81 90 02; fax: + 91 121 2575724. 2 Tel.: + 91 98 37 19 11 43; fax: + 91 121 2575724 3 Tel.: + 91 98 97 01 59 46; fax: + 91 1332 273560. 0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2009.12.011

parameters and their control over the circuit behavior. Such knowledge is more easily acquired with the help of a relatively simpler analytical model than a highly accurate circuit simulation model, generally used by the circuit simulators such as SPICE. Many often, a preliminary design is made on the basis of analytical models. This is then improvised through comparison with circuit simulation results. Prevention of crosstalk thus calls for analytical models that depict a clear picture of originating mechanism and magnitude of the noise. Until recently, most of the crosstalk noise models ignored inductive effects in interconnects and treated crosstalk between adjacent lines as the result of capacitive coupling [13–16]. However, at the current frequencies, mutual inductance between adjacent lines is substantial and hence it must be accounted for in a crosstalk analysis. Considering capacitive as well as inductive couplings between adjacent interconnects, Tang et al. [17] obtained closed form analytical expressions for crosstalk noise in victim line. The expression was used for study of crosstalk noise under varying load and signal waveforms. Comparison with SPICE simulations showed the errors to be within 20%. A limitation of this approach is that it is applicable to loosely coupled interconnects only. Davis and Meindl [18,19] extended the interconnect RC-model of Sakurai et al. [13] to obtain a model that includes the effects of self and mutual inductances. The model was used for timing analysis and crosstalk estimation. Two and three coupled lines and multilevel networks were considered for the analytical purposes. A major drawback of the analyses was that interconnects were assumed to be open at their far-ends. Later, Venkatesan et al. [20,21] removed this deficiency and further

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developed it into a unified crosstalk model compatible with both RC and RLC interconnect concepts. However, the complexities of these models [18–21] render crosstalk noise dependencies on its governing parameters difficult to understand. Based on the basic concepts of theory of coupled transmission lines [22], Agarwal et al. [11] developed a crosstalk model for coupled interconnects. The model is generalized enough to be able to deal with purely capacitive, purely inductive and combination of capacitive and inductive couplings. The model is simple, comprehensive and highly explicit about the physical influence of the interconnect parameters on crosstalk noise. The model can be used to obtain an easy estimate of the effects of design optimization on crosstalk noise. The accuracy of the model is verified by SPICE simulation. An important result of the study through this model is that crosstalk is dependent on interconnect self-inductance. This dependency is more pronounced if the coupling is capacitive. Driver impedance significantly affects the performance of a Driver-Interconnect-Load (DIL) system. In crosstalk analyses reported so far the driver CMOS gate is approximated by a simple resistor [7–10,18]. Same assumption is also involved in the model of Agarwal et al. [11]. Over the entire transition period of an input signal, such an assumption cannot be justified for a CMOS driver. The reason is that during switching, a transistor in a CMOS gate operates partially in the linear region and partially in the saturation region of its characteristics. It is in the linear region that a transistor can be well approximated by a resistor. In the saturation region, the transistor is more accurately modeled as a current source with a high resistance in parallel. Thus an appropriate MOS model should be used as in reality CMOS drivers are used. Kaushik et al. [23] proposed a simple crosstalk noise model for coupled on-chip interconnects driven by CMOS gates. The crosstalk model is based on coupled transmission line theory and assumes CMOS gate driving different line configurations. The Alpha Power Law model of MOS transistor is used to represent a CMOS driver. This is combined with a transmission line-based coupled RLC model of interconnect to develop a composite model for analytical purpose. The composite DIL model assumes only one of coupled lines i.e. aggressor is switching while the other line i.e. victim is quiet. On this basis a transient analysis of crosstalk noise is carried out. The comparisons of the analytical results with SPICE showed that the model captured noise peaks, timing and waveform shape quite well. However, the composite DIL model proposed in this paper deals with simultaneously switching of both lines either in-phase or out-of-phase. While considering out-of-phase switching in the two coupled lines Agarwal et al. [11] assumed simultaneous occurrence of 0 to VDD transition at the input of one line and 0 to VDD transition at the input of the other line. The later transition is not a realistic scenario for CMOS technology. Noise in coupled lines can be broadly divided into two categories viz: (1) functional crosstalk noise, and (2) dynamic crosstalk noise. Under functional crosstalk noise category, a victim (quiet) line experiences a voltage spike when an aggressor (active) line switches, whereas, dynamic crosstalk noise is experienced when aggressor and victim line switches simultaneously [1,6]. Under the effect of dynamic crosstalk, a change in signal-propagation delay is observed when adjacent lines switch simultaneously either in-phase or out-of-phase. As dynamic crosstalk is commonly encountered in practice, its analysis is as important as that of functional crosstalk noise. Furthermore, CMOS logic gates tend to have very good functional-noise rejection capabilities, whereas the dynamic form of coupling noise impacts the critical issue of timing. An accurate model for timing analysis of dynamic crosstalk is therefore important. This

paper, therefore, focuses on waveform analysis, crosstalk peak and delay estimation on victim line in the simultaneously switching scenario. A composite DIL model similar to the model proposed by Kaushik et al. [23] that includes the accurate Sakurai’s Alpha power law model for transistors [12] is used for crosstalk analyses of in-phase and out-of-phase switching. As an improvement over the analysis of Agarwal et al. [11], the more realistic transitions of 0 to VDD and VDD to 0 at the inputs of the two coupled lines is considered.

2. Driver-interconnect-load model The aggressor and victim line CMOS driver transistors is represented by Alpha Power Law model [12], which is given by 8 VGS r VTO : cut-off region > <0 a=2 ðV V Þ V VDS oVDSAT : linear region k ð1Þ ID ¼ TO DS l GS > : k ðV V Þa VDS ZVDSAT : saturation region s GS TO where VD  SAT is drain saturation voltage; kl and ks are transconductance parameters in linear and saturation regions respectively; a is velocity saturation index; and VTO is zero bias threshold voltage. The proposed DIL model comprises of the coupled transmission line model [11], which is mathematically represented by following set of equations V1 ¼ A1 ðege z þege z Þ þA3 ðego z þ ego z Þ; I1 ¼ ðA1 =Z0e Þðege z ege z Þ þðA3 =Z0o Þðego z ego z Þ; V2 ¼ A1 ðege z þ ege z ÞA3 ðego z þ ego z Þ; I2 ¼ ðA1 =Z0e Þðege z ege z ÞðA3 =Z0o Þðego z ego z Þ

ð2Þ

Here, V1(z,t), I1(z,t), and V2(z,t), I2(z,t) are voltage and current waveforms on lines 1 (aggressor) and 2 (victim), respectively. The Ai’s are constants whose values are obtained from the boundary conditions. The constants ge, Z0e and go, Z0o are propagation constant and characteristic impedance for even and odd modes. The coupled interconnects are assumed to be symmetric. Receivers at the far-end of the lines are modeled as lumped capacitive loads. An input signal to CMOS driver is categorized to fast or slow ramp depending on the state PMOS (for falling ramp)/NMOS (for rising ramp) device attains when the input voltage reaches its final value [23]. If the MOSFET continues to operate in saturation region when the input ramp has reached its final value, the ramp is called fast. On the other hand, if the MOS transistor switches to linear region of operation before the input ramp attain its final value, the input ramp is said to be slow. Considering the operating conditions of the MOSFETs, the input transition period is divided into different regions for fast and slow input ramps. For in-phase and out-of-phase switching, timing analyses over each of these regions are presented in Appendix A and Appendix B, respectively. In these analyses the rising/falling slope of input ramp is assumed to be Ms = VDD/t, where t is the input transition time. Based on these analyses the far-end voltage waveforms on the victim line are then obtained.

3. In-phase switching The far-end voltage waveform on victim line as generated by the present model is compared with SPICE simulations results. Fig. 1 shows the coupled lines and the in-phase ramps at the driver end. The parameters ‘, W, S, Ltot, Ctot, Cc, and M represents length, width, spacing between interconnects, line inductance, line capacitance, coupling capacitance, and mutual inductance, respectively. The coupled interconnects have length (‘), width (W)

ARTICLE IN PRESS B.K. Kaushik et al. / Microelectronics Journal 41 (2010) 85–92

m11

and spacing (S) of 2 mm, 1.2 mm and 0.4 mm, respectively. The values of parasitic impedance parameters for the two lines are directly inherited from [11], where-in the line parasitics are extracted using the commercial extraction tool Raphael. These line parasitics are: total line inductance (Ltot)= 2.15 nH and total line capacitance (Ctot)= 257 fF. The two lines are coupled through coupling capacitance (Cc) of 184 fF and mutual inductance (M) of 1.68 nH. The rise time (t) of the input is 50 ps. For CMOS driver, data of an IBM 0.13 mm, 1.2 V and Level-49 technology are used through out this paper. Furthermore, for the CMOS drivers, PMOS width (Wp) is double the NMOS width (Wn). Figs. 2 and 3 show the comparison of waveforms generated by analytical model and SPICE simulation for fast and slow input ramps respectively. The proposed model waveform closely matches with SPICE waveform. For fast and slow input ramps, 90% propagation delay and peak voltage are analytically determined for in-phase switching. Different CMOS driver widths are considered. Table 1 provides these results along with computational errors with respect to (wrt) SPICE simulation results. It may be seen that the proposed model, yields average errors in estimating crosstalk peak and 90% propagation delay as 2.18% and 6.89%, respectively, whereas the maximum errors involved are 4.5% and 7.98%, respectively.

z=ℓ RLC Interconnect (Aggressor)

τ m12

Inductive Coupling

Capacitive Coupling

m21 z=ℓ

RLC Interconnect (Victim)

τ

m22

Fig. 1. CMOS gates driving mutually coupled interconnects in-phase.

In-Phase, Fast Input Ramp, Wp=34μm

1.4 Voltage at Far-end of Victim (V)

1.2 1.0 0.8 SPICE Analytical

0.6

4. Out-of-phase switching

0.4

In case of out-of-phase switching, it is observed that only fast input ramp is valid in majority of cases. This is because of Miller’s effect where the coupling capacitance is effectively doubled for out-of-phase switching. Due to this the charging/discharging of interconnect line is quite slow, which inhibits MOS transistor operation in linear region during the transition period of input ramp. Thus, for out-of-phase switching, only fast input ramp case is considered. In case of in-phase switching for falling input signals, the analysis carried out focused on only PMOS transistors through all regions of operation. Since the NMOS transistors were neglected, therefore they can be called as Recessive transistor, whereas PMOS transistor that contributed mostly for even (A1) and odd (A3) waves can be termed as Dominant transistor. Similarly, for rising input the PMOS and NMOS transistors are called recessive and dominant transistors, respectively. In sharp contrast to in-phase switching, all MOSFETs (either dominant or recessive) contribute towards even and odd waves under out-of-phase switching condition. For rising and falling inputs to aggressor and victim lines respectively, transistors m12 (NMOS) and m21 (PMOS) are dominant, whereas transistors m11 (PMOS) and m22 (NMOS) are recessive. The CMOS drivers of aggressor and victim lines have to pass through ten different regions of operation. These regions of operation are shown in Table 2. The inputs to aggressor and victim lines are rising and falling respectively.

0.2 0.0

0

50

100 Time (ps)

-0.2

150

200

Fig. 2. Waveform on victim line under in-phase switching for fast ramp.

1.6 Voltage at Far-end of Victim (V)

87

In-Phase, Slow Input Ramp, Wp=40μm

1.4 1.2 1.0 0.8

SPICE Analytical

0.6 0.4 0.2 0.0 -0.2

0

20

40

60

80 100 Time (ps)

120

140

160 180

Fig. 3. Waveform on victim line under in-phase switching for slow ramp.

Table 1 Computational error involved in analytically calculated 90% propagation delay (ps) and peak voltage (V) wrt SPICE simulation. Driver width of PMOS Wp = 2Wn (lm)

33 34 40 70 100

Input ramp type

Fast Fast Slow Slow Slow

90% propagation delay

Vmax

SPICE (ps)

Analytical (ps)

% Error wrt SPICE

SPICE

Analytical

% Error wrt SPICE

77.65 77.19 74.79 68.78 66.69

73.04 72.72 69.65 63.37 61.37

 5.94  5.79  6.87  7.86  7.98

1.23 1.24 1.39 1.83 2.06

1.24 1.25 1.37 1.75 1.97

0.49 0.65  1.08  4.19  4.5

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crosstalk peak and 90% propagation delay are 1.77% and 6.85%, respectively.

Table 2 Generalized regions of operation under out-of-phase switching. Region

Time

I II III IV V VI VII VIII IX X

Recessive transistors

From

To

m12-NMOS

m21-PMOS

m11-PMOS

m22-NMOS

0 t1 t2 t3 t4 t5 t6

t1 t2 t3 t4 t5 t6

t

t7 t8 End

Cut-off Saturation Saturation Saturation Saturation Saturation Saturation Saturation Saturation Linear

Cut-off Cut-off Saturation Saturation Saturation Saturation Saturation Saturation Linear Linear

Linear Linear Linear Saturation Cut-off Cut-off Cut-off Cut-off Cut-off Cut-off

Linear Linear Linear Linear Linear Saturation Cut-off Cut-off Cut-off Cut-off

t7 t8

t

1.4

Out-of-Phase, Wp=20 μm

1.2 1.0 0.8 0.6

SPICE Analytical

0.4

5. Comparison of linear and non-linear driver operation This section compares the performance of linear resistive driver model with a non-linear CMOS driver model in a driverinterconnect-load circuit. Figs. 5 and 6 demonstrate the comparison of the waveforms generated by (1) proposed analytical model using non-linear driver; (2) SPICE simulations using CMOS driver; and (3) analytical model using equivalent linear region resistance driver for in-phase (Wp = 40 mm and Wn = 20 mm) and out-of-phase (Wp = 70 mm and Wn = 35 mm) switching, respectively. It may be seen that with respect to SPICE simulation results, the noise peaks and their timings are more effectively estimated by the model which uses a-power law transistor model in a CMOS driver than the model the driver as a linear resistance. Table 4 shows the computational errors involved in estimating 90% propagation and transition time delays using either linear driver or non-linear driver with respect to SPICE simulations employing CMOS driver. Different PMOS widths are used for inphase (slow and fast input ramps) and out-of-phase (fast input ramps) switching.

1.8

0.2 0.0

In-Phase Switching

1.6 0

100

200

-0.2

300 Time (ps)

400

500

600

Fig. 4. Waveform under out-of-phase switching for fast input ramp.

Table 3 Computational error involved for analytically calculated 90% propagation delay (ps) and peak voltage (V) wrt SPICE simulation. Driver width of PMOS Wp = 2Wn (lm)

90% prop. delay SPICE

Vmax

Voltage at Far End of Victim (V)

Voltage at Far-end of Victim (V)

Dominant transistors

1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0

Analytical Error wrt SPICE Analytical Error SPICE (%) wrt SPICE (%)

SPICE CMOS Linear Driver Analytical CMOS

-0.2

0

50

100 Time (ps)

150

200

Fig. 5. Comparison of waveforms under in-phase switching (Slow input ramp). 296.08 162.92 141.97 121.23 107.13

275.8 154.5 136.46 118.43 104.93

 6.85  5.17  3.88  2.31  2.05

1.20 1.21 1.23 1.38 1.57

1.2 1.22 1.23 1.39 1.6

0.025  1.24  0.28  0.97  1.77

In the analysis presented in Appendix B, contributions towards even (A1) and odd (A3) waves through dominant transistors are represented as A1d and A3d, and similar contributions through recessive transistors are A1r and A3r. The contributions of dominant and recessive transistors are added up for finally generating even and odd waves. Every region of operation hereby dealt will show each contribution separately. Fig. 4, confirms the validity of proposed model by comparing the waveforms generated analytically and SPICE simulations for PMOS of width 20 mm. Table 3 shows the computational error (wrt SPICE) involved for analytically calculated 90% propagation delay and peak voltage in case of out-of-phase switching for different CMOS driver widths. While estimating crosstalk peak and 90% propagation delay, the proposed model yields, average errors of 0.86% and 4.05%, respectively, whereas the maximum errors involved for

1.6

Out-of-Phase Switching

1.4 Voltage at far-end of victim (V)

20 40 50 70 100

1.2 1.0 0.8 0.6

SPICE CMOS Linear Driver Analytical CMOS

0.4 0.2 0.0 -0.2

0

50

100 150 Time (ps)

200

250

Fig. 6. Comparison of waveforms under out-of-phase switching (fast input ramp).

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Table 4 Computational error involved for 90% propagation delay (ps) and transition time delay (ps) for resistive and cmos driver wrt SPICE simulation. Switching type

Ramp type

PMOS width (lm)

SPICE

90% Prop. delay In-Phase

Slow Fast

Out-ofphase

Fast Fast

Transition delay

Proposed model

Agarwal et al. model [11]

% Error with respect to SPICE

90% Prop. delay

90% Prop. delay

90% Prop. delay our model

Transition delay our model

90% prop. delay [11]

Transition delay [11]

Transition delay

Transition delay

40 70 33 35

74.79 68.78 77.65 76.74

18.88 12.98 21.51 20.69

69.65 63.37 73.04 72.47

21.6 14.79 24.5 23.53

59.41 55.03 61.7 61.01

29.15 25.16 31.24 30.61

6.87 7.86 5.94 5.56

 14.41  13.94  13.90  13.73

20.56 19.99 20.54 20.50

 54.40  93.84  45.23  47.95

20 40 70 100

303.45 162.92 121.23 107.13

225.95 118.87 78.64 68.7

275.8 154.5 118.43 104.93

217.73 114.73 76.36 66.98

167.74 102.03 83.53 55.84

144.93 83.36 66.46 39.57

6.85 5.17 2.31 2.05

3.64 3.48 2.90 2.50

44.72 37.37 31.10 47.88

35.86 29.87 15.49 42.40

The 90% propagation delay predicted by proposed model using non-linear CMOS gate for out-of-phase switching has average and maximum errors (wrt SPICE) of 4.09% of 6.85%, respectively. For similar switching condition, the maximum and average errors involved using linear resistive driver are as large as 47.88% and 40.27%, respectively. Similarly, under in-phase switching, the 90% propagation delay estimated by proposed model has average and maximum errors of 6.55% and 7.86%, respectively, whereas, the errors involved in linear driver instead of CMOS driver are as large as 20.56% and 20.4%, respectively. The maximum and average errors involved in transition time delay calculation by proposed model using non-linear driver for out-of-phase switching are 3.64% and 3.13%, respectively. For similar switching condition, the maximum error involved using linear driver is as large as 42.4%, while average error is also quite high i.e. 30.91%. For in-phase switching, the average and maximum errors using non-linear driver are 13.9% and 14.4%, respectively. In sharp contrast, the maximum error involved using linear driver is as large as 93.84%, while the average error is also alarmingly high i.e. 60.35%.

6. Conclusions This paper analyzed crosstalk noise for in-phase and out-ofphase switching in coupled interconnects both having CMOS drivers. In either case input switching is assumed to be between logic 1 (VDD) and logic 0 (Gnd). Alpha-power law MOS model is used to represent a transistor in CMOS-driver. The comparisons of the analytical results with SPICE for CMOS gate driven interconnect shows that the proposed model captures noise peaks and their timings; 90% propagation delay; transition time delay with good accuracy. Comparative studies with SPICE as reference show that the modeling of CMOS gate driver by a linear resistance, as was done previously by researchers can lead to erroneous estimations. It also indicates that inclusion of a-power law model in DIL model significantly improves accuracy of the composite model for analyzing output noise waveform. The analytical results are obtained by the use of 0.13 mm IBM data. The close agreement between these results and those obtained by SPICE simulation clearly shows that the approach is useful for the present day industrial use. However, as technology scaling brings much shorter transistors for industrial consumption the transistor model may have to be replaced while following the same basic approach presented here. Industries generally practice lookup table based approaches for modeling the actual behavior of CMOS during final design phases. Although lookup table approach is considered to be superior but has certain limitations for initial design cycles. Table

lookup is technology dependent and is therefore quite impossible for everyone having access to it. While being accurate, Table lookup method requires a carefully constructed table which is made even more difficult by the fact that the input slews can vary over a wide range, especially during the initial stages of design. On the other hand the proposed model is extremely simple and therefore suitable for initial design level.

Appendix A. Analytical model for in-phase switching For in-phase switching we divide the transition time into four regions on the basis of the operating conditions of the transistors. We now develop the timing analysis region wise. A. Fast input ramp Region-I (0ot ot1): During this interval of time, PMOS (m11 and m21) are in cut-off state and NMOS (m12 and m22) operates in linear region. Since the voltage drop across drain and source is very low, the current through NMOS (m12 and m22) is negligible. Thus, NMOS of aggressor and victim drivers are in high impedance state. The instant of time t1, when PMOS just enters saturation region, can be obtained directly by knowing the threshold voltage of the device. The collective gate–to-drain capacitance of NMOS and PMOS (Cm) is negligible in comparison to the interconnect line capacitance. Thus, during the short transition period of input the interconnect capacitance is negligibly charged/discharged through Cm. Using these boundary conditions and through the analysis of Agarwal et al. [11] it can be shown that ðA1 =Z0e Þ þ ðA3 =Z0o Þ ¼ 0; and ðA1 =Z0e ÞðA3 =Z0o Þ ¼ 0

ð3Þ

Solving the set of Eq. (3), we obtain A1 = 0; and A3 = 0 Region-II (t1 ot o t): During this region of the transition time, PMOS m11 and m21 operates in saturation region. Although, the voltage at node z=0 rises during this stage, but does not rise appreciably to drive significant current through NMOS. The current through the PMOS parasitic gate-to-drain capacitance is considered to be negligible as compared to the drain current, IDSp of the PMOS. Therefore, IDSp ffi I1(z= 0). For PMOS of driver by (1) IDSp ðsatÞ ¼ ks ðVGS VTO Þa

ð4Þ

where ks = IDO/(VDD  VTO)a and VGS ¼ ðVDD :tÞ=t ¼ Ms :t

ð5Þ

From (4) and [11], ðA1 =Z0e Þ þ ðA3 =Z0o Þ ¼ ks1 ðMs :tVTO1 Þa1

ð6Þ

ðA1 =Z0e ÞðA3 =Z0o Þ ¼ ks2 ðMs :tVTO2 Þa2

ð7Þ

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ks1 and VTO1 corresponds to PMOS m11, whereas ks2 and VTO2 corresponds to PMOS m21.Solving Eqs. (6) and (7) a1

a2

ð8Þ

A3 ¼ ð1=2ÞZ0o ½ks1 ðMs :tVTO1 Þa1 ks2 ðMs :tVTO2 Þa2 

ð9Þ

A1 ¼ ð1=2Þ:Z0e ½ks1 ðMs :tVTO1 Þ

þks2 ðMs :tVTO2 Þ 

For homogeneous drivers (ks1 = ks2 = ks; VTO1 =VTO2 = VTO and

a1= a2= a), A1 =Z0eks(Mst VTO)a; and A3 =0. Region-III (t ot ot2): Over this region, PMOS m11 and m21 are in saturation and the input ramp has reached its final value. At time t2, PMOS enters into linear region of operation. Since the input has reached its final value the gate-to-source parasitic capacitances are d.c. biased, and therefore negligible current flows through them. The current IDS,p and the current I1(z =0)at the near end of the interconnect are equal. NMOS (m12/m22) is cut-off and therefore no current flows through it. If, t2 is the instant when |VDS(sat)| =|V1(z= 0)  VDD|; and I1(z =0) = IDS,p(sat) then by (1) and because the input has reached its final value VDS(sat)=(ks/k1)(VDD VTO)a/2 and IDS,p(sat)=IDO. Therefore at time t2, V1 ðz ¼ 0Þ ¼ VDD ðks =kl Þ:ðVDD VTO Þa=2 and I1 ðz ¼ 0Þ ¼ IDO : With these boundary conditions and by the approach of ref.[11], ðA1 =Z0e Þ þ ðA3 =Z0o Þ ¼ IDO1 ; and ðA1 =Z0e ÞðA3 =Z0o Þ ¼ IDO2

ð10Þ

IDO1 and IDO2 are saturation region current for m11 and m21, respectively. Solving the set of Eq. (10), we obtain A1 ¼ ð1=2Þ:Z0e ðIDO1 þ IDO2 Þ; and A3 ¼ ð1=2Þ:Z0o ðIDO1 IDO2 Þ

ð11Þ

Homogeneous drivers (IDO1 = IDO2 = IDO) reduces (11) to A1 = Z0eIDO; and A3 =0. Region-IV (t4t2): This region of input transition time has the PMOS operating in its linear region, whereas, the NMOS remains in cut-off state. The near ends of aggressor and victim lines at node z= 0 are connected to VDD through linear resistance Rs and Rv, respectively. Using these boundary conditions A1 ¼

ðRv þ2Z0o þ Rs ÞVDD Z0e 2Rv Rs þ Rv Z0e þ Rs Z0o þ 2Z0e Z0o þRv Z0o þ Rs Z0e

ð12Þ

A3 ¼

VDD Z0o ðRs Rv Þ 2Rv Rs þ Rv Z0e þ Rs Z0o þ 2Z0e Z0o þRv Z0o þ Rs Z0e

ð13Þ

For homogeneous drivers (Rs = Rv), (12) and (13) reduces to A1 = VDDZ0e/(Rs + Z0e) and A3 = 0.

for this linear region, the resistance of PMOS is Rsp ðtÞ ¼ ½VDO =IDO :ðVDD VTO Þa=2 :ðMs :tVTO Þa=2

ð16Þ

Applying boundary conditions, A1 and A3 are obtained as ðRsp2 þ2Z0o þ Rsp1 ÞVs Z0e 2Rsp2 Rsp1 þ Rsp2 Z0e þRsp1 Z0o þ2Z0e Z0o þ Rsp2 Z0o þ Rsp1 Z0e ðRsp1 Rsp2 ÞVs Z0o A3 ¼  2Rsp2 Rsp1 þ Rsp2 Z0e þRsp1 Z0o þ2Z0e Z0o þ Rsp2 Z0o þ Rsp1 Z0e A1 ¼

Rsp1 and Rsp2 is linear resistance of m11 and m21, respectively. Homogeneous drivers (Rsp1 = Rsp2 =Rsp), results in A1 ¼ Vs :Z0e =ðRsp þ Z0e Þ; and A3 ¼ 0: Region-IV: Region-IV is solved exactly as for fast ramps.

Appendix B. Analytical model for out-of-phase switching For timing analysis the transition time is divided into ten regions in this case. Region-I (0ot ot1): During this region of operation, the dominant transistors are in cut-off state, whereas the recessive transistors are in linear region of operation. Dominant Transistors: Using boundary conditions and through the analysis of Agarwal et al. [11], it can be shown that A1d = 0; and A3d = 0. The instant of time t1, when NMOS m12 just enters saturation region, is obtained directly by knowing the threshold voltage of device. Recessive Transistors: Both transistors are in linear region and the gate-to-source voltages of both transistors are varying with time. Using boundary conditions ½ðVDD ðA1r þ A3r ÞÞ=ðA1r =Z0e Þ þ ðA3r =Z0o Þ ¼ R11

ð17Þ

½ðA1r A3r Þ=ððA1r =Z0e ÞðA3r =Z0o ÞÞ ¼ R22

ð18Þ

Here R11 and R22 corresponds to transistors m11 and m22, respectively. Similarly, the transistor parameters (such as VTO, VDO, IDO, ks, kl and a) with subscript 11, 12, 21 and 22 correspond to transistor m11, m12, m21 and m22, respectively. Using Alpha power law model Eq. (1) the resistances during this region of operation are R11 ¼ ½VDO;11 =ðIDO;11 :ðVDD VTO;11 Þa11 =2 Þ:ðVDD Ms :tVTO;11 Þa11 =2 R22 ¼ ½VDO;22 =IDO;22 :ðVDD VTO;22 Þa22 =2 ðVDD Ms :tVTO;22 Þa22 =2 Solving (17) and (18), one obtains ðR22 þZ0o ÞVDD Z0e 2R22 R11 þ R22 Z0e þ R11 Z0o þ 2Z0e Z0o þ R22 Z0o þ R11 Z0e ðR22 þZ0e ÞVDD Z0o A3r ¼  2R22 R11 þ R22 Z0e þ R11 Z0o þ 2Z0e Z0o þR22 Z0o þ R11 Z0e A1r ¼

B. Slow input ramp Region-I (0ot ot1): The operating condition of the structure in region-I is same as for fast input ramps. Region-II (t1 ot ot2): The operating condition for this region is also similar to that of fast inputs; however, it extends from time t1 to t2, where t2 o t. Time t2 is obtained by following analysis: As per a-power law model [12] and (1) VDS ðsatÞ ¼ ðks =kl ÞðMs :tVTO Þa=2

ð14Þ

Hence t2 is reached when V1 ðz ¼ 0Þ ¼ VDD ðks =kl Þ:ðMs :tVTO Þa=2 ;

ð15Þ

V1(z= 0) is evaluated with help of A1 and A3. With passage of time, the values of V1(z = 0) and VDS(sat) rises; whereas |VDD  V1(z= 0)| falls. The magnitude of |VDD  V1(z = 0)| will be equal to VDS(sat) at time t2. Region-III (t2 ot o t): During this region, the PMOS transistor operates in linear mode while the input is still a ramp. Using (1)

Region-II (t1 otot2): Dominant Transistors: Using boundary conditions [11] and Eq. (1) ðA1d =Z0e Þ þ ðA3d =Z0o Þ ¼ ks;12 :ðMs :tVTO;12 Þa12 ¼ K12 ðtÞ

ð19Þ

ðA1d =Z0e ÞðA3d =Z0o Þ ¼ 0

ð20Þ

Solving (19) and (20) results in A1d = 0; and A3d = 0. The time t2, when PMOS m21 just enters saturation region, can be obtained by knowing the threshold voltage of the device. Recessive Transistors: During this region, A1r and A3r are obtained exactly as that in region-I. Region-III (t2 ot ot3): Dominant Transistors: Using boundary conditions and through the analysis of [11] ðA1d =Z0e Þ þ ðA3d =Z0o Þ ¼ ks;12 ðMs :tVTO;12 Þa12 ¼ K12 ðtÞ

ð21Þ

ðA1d =Z0e Þ þðA3d =Z0o Þ ¼ ks;21 ðMs :tVTO;21 Þa21 ¼ K21 ðtÞ

ð22Þ

ARTICLE IN PRESS B.K. Kaushik et al. / Microelectronics Journal 41 (2010) 85–92

Solving (37) and (38), results in

Solving (21) and (22) A1d ðtÞ ¼ ð1=2Þ:Z0e :ðK12 ðtÞK21 ðtÞÞ

ð23Þ

A3d ðtÞ ¼ ð1=2Þ:Z0o :ðK12 ðtÞ þK21 ðtÞÞ

ð24Þ

Recessive Transistors: A1r and A3r are obtained exactly as that in region-I. However, the time t3 is found by following analysis. As per Alpha power law model [12] and (1), the drain to source voltage of m11 during saturation region is given as VDS ðsatÞ ¼ ðks;11 =kl;11 ÞðVDD Ms :tVTO;11 Þa11 =2

ð25Þ

The time instant t3 is reached when V1 ðz ¼ 0Þ ¼ VDD VDS;11 ðsatÞ

91

ð26Þ

V1(z= 0) is evaluated with help of A1 and A3. The value of V1(z= 0) and VDS,11(sat) falls with time whereas, the value of |VDD  V1(z= 0)| rises with respect to time. The values of |VDD  V1(z= 0)| and VDS,11(sat) will be equal at time t3. Region-IV (t3 ot ot4): Dominant Transistors: During this region, A1d and A3d are obtained exactly as that in region-III. Recessive Transistors: Using boundary conditions [11] and Eq. (1) ðA1r =Zoe Þ þ ðA3r =Z0o Þ ¼ ks;11 ðVDD Ms :tVTO;11 Þa11 ¼ K11 ðtÞ

ð27Þ

ðA1r A3r Þ=½ðA1r =Z0e ÞðA3r =Z0o Þ ¼ R22

ð28Þ

Solving Eqs. (27) and (28) results in

A1d ¼ ðZ0e =2Þ:ðIDO;12 IDO;21 Þ; A3d ¼ ðZ0o =2Þ:ðIDO;12 þ IDO;21 Þ The timing instant t7 is found by following analysis: As per Alpha power law model VDS;21 ðsatÞ ¼ ðks;21 =kl;21 ÞðMs :tVTO;21 Þa21 =2

ð39Þ

V2 ðz ¼ 0Þ ¼ VDD VDS;21 ðsatÞ

ð40Þ

V2(z = 0) is evaluated with help of A1 and A3. With passage of time, the values of V2(z= 0) and VDS,21(sat) rises, whereas, |VDD  V2(z= 0)| falls. |VDD  V2(z= 0)| and VDS,21(sat) will be equal at time t7. Recessive Transistors: Solved exactly as region-VII. Region-IX (t7 ot ot8): Dominant Transistors ðA1d =Z0e Þ þðA3d =Z0o Þ ¼ IDO;12

ð41Þ

½VDD ðA1d A3d Þ=½ðA1d =Z0e ÞðA3d =Z0o Þ ¼ Rc21

ð42Þ

where Rc21 =VDO,21/IDO,21. Solving (41) and (42), results to   Rc21 :IDO;12 þ Z0e :IDO;12 VDD A1d ¼ Z0e : IDO;12  Z0o :ððZ0e =Z0o Þ þ2:ðRc21 =Z0o Þ þ 1Þ Rc21 :IDO;12 þZ0e :IDO;12 VDD A3d ¼ ððZ0e =Z0o Þ þ 2:ðRc21 =Z0o Þ þ 1Þ The timing instant t8 is found by following analysis: As per Alpha power law model

A1r ¼ K11 Z0e ðR22 þ Z0o Þ=ðZ0o þ 2R22 þZ0e Þ

ð29Þ

VDS;12 ðsatÞ ¼ ðks;12 =kl;12 ÞðMs :tVTO;12 Þa12 =2

ð43Þ

A3r ¼ K11 Z0o ðR22 þ Z0e Þ=Z0o þ 2R22 þ Z0e

ð30Þ

V1 ðz ¼ 0Þ ¼ VDS;12 ðsatÞ

ð44Þ

The instant of time t4, when PMOS m11 just enters cut-off region, is obtained by knowing the threshold voltage of device. Region-V (t4 ot ot5): Dominant Transistors: During this region, A1d and A3d are obtained exactly as that in region-III. Recessive Transistors: ðA1r =Z0e Þ þ ðA3r =Z0o Þ ¼ 0

ð31Þ

V1(z = 0) is evaluated with help of A1 and A3. With course of time the value of V1(z= 0) falls, whereas VDS,12(sat) rises. The value of V1(z =0) will be equal to VDS,12(sat) at time t8. Recessive Transistors: Solved exactly as for region-VII. Region-X (t 4t8): Dominant Transistors Z0e :ðRc12 þZ0o Þ:VDD ½ðRc21 þZ0o Þ:ðRc12 þ Z0e Þ þðRc12 þZ0o Þ:ðRc21 þ Z0e Þ Z0o :ðRc12 þ Z0e Þ:VDD A1d ¼ ½ðRc21 þZ0o Þ:ðRc12 þ Z0e Þ þðRc12 þZ0o Þ:ðRc21 þ Z0e Þ

A1d ¼ ðA1r A3r Þ=½ðA1r =Z0e ÞðA3r =Z0o Þ ¼ R22

ð32Þ

Solving (31) and (32) results in A1r =0; and A3r =0 The time t5 is found by following analysis: As per Alpha power law model [12],

where Rc12 = VDO,12/IDO,12 Recessive Transistors: Solved exactly as for region-VII.

VDS;22 ðsatÞ ¼ ðks;22 =kl;22 ÞðVDD Ms :tVTO;22 Þa22 =2

ð33Þ

V2 ðz ¼ 0Þ ¼ VDS;22 ðsatÞ

ð34Þ

V2(z=0) is evaluated with help of A1 and A3. The value of V2(z=0) rises with time whereas, the value of VDS,22(sat) falls with respect to time. The values of V2(z=0) and VDS,22(sat) will be equal at time t5. Region-VI (t5 ot ot6): Dominant Transistors: During this region, A1d and A3d are obtained exactly as that in region-III. Recessive Transistors: ðA1r =Z0e Þ þ ðA3r =Z0o Þ ¼ 0

ð35Þ

ðA1r =Z0e ÞðA3r =Z0o Þ ¼ ks;22 ðMs :tVTO;22 Þa22 ¼ K22 ðtÞ

ð36Þ

On solving (35) and (36) results to A1r =0; and A3r = 0. The instant of time t6, when NMOS m22 just enters cut-off region, is obtained directly by knowing the threshold voltage of device. Region-VII (t6 ot o t): Dominant Transistors: During this region, A1d and A3d are obtained exactly as that in region-III. Recessive Transistors: By boundary conditions A1r = 0; and A3r = 0 Region-VIII (t ot ot7): Dominant Transistors: Applying boundary conditions ðA1d =Z0e Þ þ ðA3d =Z0o Þ ¼ IDO;12

ð37Þ

ðA1d =Z0e Þ þ ðA3d =Z0o Þ ¼ IDO;21

ð38Þ

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