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An area efficient body contact for low and high voltage SOI MOSFET devices
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Solid-State Electronics 52 (2008) 196–204 www.elsevier.com/locate/sse
Review
An area efficient body contact for low and high voltage SOI MOSFET devices Arash Daghighi b
a,*
, Mohamed Osman b, Mohamed A. Imam
c
a Department of Electrical Engineering, Islamic Azad University Majlesi Branch, Isfahan, Iran School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA 99164-2752, USA c ON Semiconductor, 5005 East McDowell Road, MD D145, Phoenix, AZ 85008, USA
Received 7 January 2007; received in revised form 14 September 2007; accepted 24 October 2007 Available online 21 December 2007
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract A simple and high-performance area efficient body-tied-source (BTS) contact for SOI MOSFET is presented. By simple modification to the physical layout and without introducing any increase to the fabrication process steps, the proposed body contact can be implemented. Three-dimensional (3D) non-isothermal simulation on SOI CMOS devices showed higher current drive while floating body effects were completely suppressed. In addition, improved performance is achieved when comparing on-resistance (RON) and breakdown voltage (VBR) with the conventional BTS structures. The new body contact structure is applicable to both low and high voltage (planar or trench) SOI and bulk devices. Experimental results obtained from fabricated bulk MOSFET devices utilizing the proposed body contact structure agreed well with the simulation findings. 2007 Elsevier Ltd. All rights reserved. Keywords: High voltage; Low voltage; Partially depleted SOI MOSFET; On-resistance; Breakdown voltage; Floating body effects; Body contact; Threedimensional simulation; Non-isothermal drift-diffusion model
Contents 1. 2. 3.
4. 5.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-dimensional simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1. New body contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. Body contact misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1. Introduction
*
Corresponding author. Tel.: +98 311 6268408. E-mail address: [email protected] (A. Daghighi).
0038-1101/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.10.052
Recently, there has been a growing interest in using SOI for high speed digital and RF circuits because it offers performance gain over Bulk CMOS in terms of speed, isolation, density, yield and performance gain in low/high
A. Daghighi et al. / Solid-State Electronics 52 (2008) 196–204
power electronics [1]. Additionally, SOI MOSFET has been the technology of choice for radiation hard, space and hostile environment applications. As the technology moves to the deep sub-micron generation, its application is spreading to microprocessors, memories, RF CMOS and low power electronics. However, compared to bulk MOSFETs, the static and dynamic performances of SOI MOSFETs are considerably different due to various effects that are introduced by the complete isolation of the devices. The presence of buried oxide layer results in a floating body region and its low thermal conductivity causes self-heating effects [2]. The area efficiency of floating body design configuration makes it more desirable in high-density applications. However, floating body device design complicates device performance and suffers from several floating body modulation effects such as drain voltage induced fluctuations in body potential which give rise to reduction of the breakdown voltage, variations in the threshold voltage, current kink, increased noise and disturbances in the static and dynamic characteristics of the device. The body potential modulation and the associated effects are critical especially for partially depleted (PD) SOI devices [3] where depending on the device bias condition, the body potential may be elevated and attain a positive value which causes the conduction of a parasitic lateral bipolar junction transistor (BJT) formed with the source as emitter, floating body as base, and drain as collector. This lateral BJT in the SOI MOSFET structure is important as it accounts for the loss of the gate control and poor breakdown voltage characteristics. Several approaches have been proposed to suppress the floating body effects in PD SOI. These include introducing
197
recombination centers for the holes below the source, using Ge implantation in the source region, or making a path for the generated holes in the body to escape to contact(s) [4– 9]. The first method adds to the fabrication process complexity while the Ge implanted source structure is not CMOS compatible. All of the methods that have been developed to make a path for the generated holes (such as H-gate and body-tied-source structures) suffer from one or more of the following drawbacks: (1) increased fabrication process complexity, (2) larger device area, or (3) lower effective device width. For high voltage power ICs the impact is translated to the ‘‘RON · area’’ figure of merit. This indicates that for the same area devices, the one with the lower RON (higher current drive) has a smaller figure of merit. A lower ‘‘RON · area’’ allows a designer to use a smaller high voltage MOSFET to meet ON-resistance requirements for a given application, which reduces the area and cost of a power integrated-circuit. In this paper, we propose a novel area efficient body contact for SOI devices and investigate its performance using three-dimensional simulation study. Additionally, to confirm the simulation findings, we also fabricated bulk n-MOSFET structures with both conventional and the proposed body contacts. Fig. 1 shows the layout view of few conventional SOI body contact structures and our proposed body contact. The H-gate body contact shown in Fig. 1A, has considerably large footprint (i.e. area inefficient) whereas allowing independent control of the body voltage. Body-tied-source (BTS) structure controls body voltage by introducing P+ regions in the source end of the device to allow low resistance path(s) for the holes at the expense of reduced current drive for the device as depicted in Fig. 1B and C shows the proposed area efficient
Fig. 1. SOI body contacts (arrows show the current flow in the channel), (A) H-gate, (B) conventional body-tied-source and (C) novel body contact.
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body contact, which can be implemented by simple modification to the physical layout design [10]. Compared to the H-gate body contact (Fig. 1A), the novel body-contacted device occupies a smaller silicon area whereas the current drives are approximately equal. This is due to the small contact area at the edge of the P+ doped region to the body of the device, which results in almost equal effective device widths. In comparison with the conventional body-tiedsource structure (Fig. 1B), the proposed body-contacted device has a larger effective width and as a result a higher current drive for the same drawn widths. In this work, we investigate the performance of the proposed body contact structure and analyze its effect in suppressing floating body effects using three-dimensional (3D) device simulation. In the following sections, we review the 3D simulation model and analyze the simulation results of the proposed structure and the conventional structures. The three-dimensional simulation model is explained in Section 2, simulation results of the new body contact and the effect of process misalignment on the performance of the device as obtained from simulations are presented in Section 3, followed by discussion of the measurement results on fabricated bulk n-MOSFETs in Section 4 and a conclusion in Section 5. 2. Three-dimensional simulation model The Body of BTS SOI MOSFET is not uniformly at ground potential due to the high sheet resistance of the body. As holes generated in impact ionization process move toward the body contacts, a potential gradient builds up along the device width [7]. The increase in body voltage decreases the threshold voltage and consequently increases the channel current and portions of the device away from the body contacts pass higher channel current. This changes the operation characteristics of the device in the third dimension (along device width). In addition, body-contacted devices can be viewed as a series of diodes P+/P/N+ (inactive regions) and regular active MOSFETs. Therefore, three-dimensional simulation is required to simulate body-contacted devices. In an earlier investigation, we proposed a simple 2D model for simulation of body-contacted devices using fictitious photo-generated e-h pairs to induce the floating body voltage [11]. The 2D model provides a computational efficient approach to get a first order estimate of the body potential profile, but does not allow investigating I–V characteristics, accurate carrier potential and charge distributions. This makes it necessary to use three-dimensional simulation for our detailed analysis. The low thermal conductivity of the buried oxide layer beneath the active silicon film layer in SOI MOSFETs causes self-heating effect, which strongly affects carrier mobility and electron-hole generation rates. Better comprehensibility, we used non-isothermal drift-diffusion model to take into account the impact of lattice temperature variation on performance of the device. The three-dimensional
simulation was performed using ISE TCAD’s device simulator (DESSIS) [12]. It is well known that drift-diffusion approach overestimates the impact ionization process. The model for generation due to impact ionization, implemented in DESSIS, is given by [12] Gk ¼ an nV n þ ap pV p
ð1Þ
where Vn,p denotes drift velocity and n (p) denotes the carrier concentration of electrons (holes). The model for impact ionization generation coefficients (an, ap) suitable for simulation at high temperatures (300–700 K) is given by an;p ðF ; T Þ ¼
F aðT Þ þ bðT ÞedðT Þ=ðF þCðT ÞÞ
ð2Þ
where F is the driving force, a(T), b(T), c(T) and d(T) are the temperature dependent model parameters. They can be defined by constant coefficient functions. The temperature dependence of model parameters, for electrons, can be read as [12]: aðT Þ ¼ a0 þ a1 T a2 ;
bðT Þ ¼ b0 ;
dðT Þ ¼ d 0 þ d 1 T þ d 2 T 2
cðT Þ ¼ c0 þ c1 T þ c2 T 2 ; ð3Þ
In order to reduce the impact ionization generation rate, we noticed that drift-diffusion approach can not reproduce velocity overshoot. In this case, the hydrodynamic model provides a very good compromise. As a result, we modified the coefficients (ai, bi, ci and di) to get a first order estimate of avalanche generation using hydrodynamic model. For this purpose, the generation rate in the pinch-off region of two identical devices using non-isothermal drift-diffusion and hydrodynamic models were compared. Having modified the above coefficients, the avalanche generation rates using both the models were equal in the biasing points of interest. ISE TCAD MESH routine was used to generate the grid for the 3D simulations [13]. Impurity concentrations and user required element sizes can be described using dimension-independent syntax and grids can be adapted according to analytical profiles. The desired grid point densities for a given concentration profiles are obtained by refining the elements in an anisotropic way, generating fine elements for the critical parts of the device and coarse elements in the bulk regions. Fig. 2 shows the generated grid structure for part of the device including one of the proposed body contacts. As can be seen, very fine grid structure is required to cover body contacts especially at the edges where the body contact connects to the body of the device. We used approximately 2000 grid points for each body contact. For the case of three body-contacted structure, this adds 6000 grid points to the total number of the grids required to capture the physical characteristic of the device making the simulation more complex. The parameters of the simulated PD SOI MOSFET device shown in Fig. 3 are: buried oxide layer thickness tbox = 0.4 lm; Silicon film thickness tbody = 0.15 lm; gate ˚ . The source and drain lateral difoxide thickness tox = 80 A fusions were modeled by Gaussian profiles along the X-axis.
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Fig. 2. 3D Mesh structure (part of the device including one of the novel body contacts is shown in the picture).
Fig. 3. 3D BTS SOI structure.
The gate of the devices was an n+polysilicon with dimensions L = 0.35 lm and W = 5 lm. The bulk contact was an electrical contact at zero volt and thermal contact at 300 K. 3. Simulation results Using non-isothermal drift-diffusion model, threedimensional simulations of body-contacted to source structures were examined. All the simulation results on current
drive, body voltage and breakdown voltage are presented at gate voltage of 1.0 V. This is due to the fact that the largest impact ionization rate happens at low gate voltages where the body effect is the largest [7,11]. In the following, Section 3.1 shows the simulation results of a floating body, two conventional BTS structures and the new body contact. In Section 3.2, the effect of process misalignment on the performance variation of the new body-contacted devices is discussed.
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3.1. New body contact Four device structures were simulated: (1) a floating body (FB) device, (2) a conventional body-contacted device with two body contacts (one at each end of the source as shown in Fig. 1B, and each had a width WB = 0.35 lm), (3) a conventional body-contacted device with three body contacts, one at each source end and one in the middle of source with WB = 0.35 lm as depicted in Fig. 3, and (4) a device with three of the proposed novel body contacts, one at both ends and one in the middle of the source. Fig. 4A has already been reported [16] and it shows the current–voltage characteristic (IDS vs. VDS) of the four simulated devices. As can be seen, the proposed body contact eliminates the kink inherent in the FB device characteristic. Also the novel body-contacted device has a higher current drive than the device with three conventional body contacts structure. Reducing the number of conventional contacts to two, increases current drive at the expense of increased body voltage, dynamic variation of threshold voltage,
Fig. 4. (A) Drain current vs. drain voltage; (B) sub-threshold characteristic.
Fig. 5. Body potential variation along the device width.
and lower breakdown voltage. Notice that the drain current starts increasing at higher rate for drain voltages beyond 2 V indicating lower breakdown voltage. The sub-threshold characteristics of the simulated devices are shown in Fig. 4B. Significant sub-threshold slope variation of DS = 16.8 mV/dec can be observed when the drain voltage changes from 50 mV to 1.5 V for the floating body device. This value decreases to DS = 3.3 mV/dec for the proposed novel body-contacted device and DS = 1.1 mV/dec for the three conventional body contacts structure. This indicates that novel body contact (narrow contact) is as effective as conventional body contacts (wide contacts) in controlling the body voltage [14]. The magnitude of the resulting floating body voltage near the source body junction provides a more accurate way of comparing the different BTS structures. Fig. 5 shows the magnitude of the electrostatic potential along a line close to and parallel to the body/source junction for the FB and BTS structures. This provides a measure of the floating body voltage at gate voltage of 1 V and drain voltage of 3 V. Note that introducing two conventional body contacts at the ends of the source reduces maximum floating body voltage from about 770–480 mV. The maximum body voltage reduces to 390 mV and 170 mV for the novel proposed body contact and three conventional body contact structures, respectively. The breakdown voltage and on-resistance of the devices are also investigated and the simulation results are summarized in Table 1. The on-state breakdown voltage shows the impact of floating body voltage on the breakdown characteristic while the device is turned on. The breakdown voltage characteristic of the proposed body contact is clearly better than that of the floating body and the conventional two body-contacted structures. In order to simulate the onresistance, gate voltage is ramped to 3 V and drain voltage to 50 mV. Faced with consistent divergence of non-isothermal drift-diffusion simulation during ramping gate voltage, we ran 2D simulations to determine the magnitude of the
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Table 1 Breakdown voltage, drive current and on-resistance of the devices Floating body
2 Body contacts
3 Body contacts
Novel body contact
Comment
VBR (V)
4
5
6
6.7
VGS = 1V (on-state breakdown)
Drive current
163%
86%
79%
104%
Ratio of IDS at VGS = 1 V, VDS = 2 V to the reference SOI
RON (X)
203
235
250
221
VGS = 3 V, VDS = 50 mV
drain current and the role of self-heating. The 2D non-isothermal simulation on a floating body device revealed negligible self-heating effects. Consequently, we used isothermal drift-diffusion model for our 3D simulations of the on-resistance (RON). The proposed novel body-contacted device showed smaller RON compared to both conventional body-contacted devices due to the increased channel current. However, it’s less than the floating body device, which has the best RON. Furthermore, we also examined influence of different body contact structures on the device current. The strong dependence of the current on the floating body voltage, which is determined by the geometry and location of body contacts, requires defining a suitable structure to act as a reference. To overcome this problem, we chose as a reference a SOI device with uniform body voltage distribution along the device width. A uniform body voltage distribution can be achieved in a device structure with a narrow and continues P+ implant under the source region and connected to the source contact. The drain current for this device was then determined at a gate voltage of 1 V and drain voltage of 2 V through simple two-dimensional simulations and then scaled to determine the desired current for any device width. Table 1 shows the ratios of current drives of the body-contacted devices (obtained from three-dimensional simulations) to that of the reference body-contacted SOI device. Notice that the floating body device exhibits a significant current drive increase (63%) due to lowering of threshold voltage and activation of lateral BJT. The proposed novel body-contacted device shows a slight increased current (104%) drive due to the modulation in body voltage. On the other hand, there is large reduction in the current drives of both two conventional body-contacted (86%) and three conventional body-contacted (79%) devices due to the decreased effective device width. Influence of the new body contact on the output conductance and transistor parasitic capacitances were also investigated. Body-contacted devices are the major component of analog circuits using partially depleted SOI MOSFETs. One of the main device characteristics, which directly affects the gain of amplifiers is the output conductance (gDS) at the biasing point of interest. It has been shown that the new body contact and the three conventional body-contacted structures show the lowest variation in drain conductance as drain voltage changes [16]. However, drain conductance of the two conventional body-contacted
device showed drain voltage dependency. For analog applications this translates to the undesired reduction of intrinsic gain of transistor. In addition to the output conductance, parasitic capacitances have an important impact on the performance of the circuits especially for high speed applications such as microprocessors and analog radio frequency (RF) circuits. Total extrinsic plus intrinsic gatesource (CGS) capacitance as the most sensitive capacitance to the geometry of the body-tied-source contacts were also examined [16]. It was shown that CGS of the new body contact in saturation region is equal to that of the conventional body contact structures and it was constant as drain voltage increased. This was different with the floating body device where CGS increased as drain voltage increased due to the variation of the body voltage. 3.2. Body contact misalignment One major concern regarding the proposed body contact is the effect of process misalignment of P+ doped regions on device performance. The ideal situation occurs when the tip of the P+ implant diamond region touches the source/body junction as shown in Fig. 6 (structure B) which lead to zero misalignment (DX = 0). Two other possible situations are when the tip shifts away from junction and in this situation there is no direct contact between the P-body and the P+ contacts (Structure A where DX = 50 nm). The other situation is where the tip shifts inside the P-body making a wider contact to the body (structure C where DX = 50 nm). Fig. 7 shows the simulation results of drain current vs. drain-source voltage for these three cases. It’s interesting to note that for structure A, the I–V characteristic in Fig. 7, does not exhibit a well defined kink as in floating body device (see Fig. 4A) and instead shows a gradual increase beyond 1.3 V at rates well below that for the FB device. This is due to the fact that accumulated holes in the body region face low potential barrier to escape to body contacts. Note that in this case, part of the source near the tip of body contact is depleted and this reduces the effective device width even smaller than the effective device width in Structure B. However, at higher drain voltages, body voltage increases resulting in increased channel current. Structure C, on the other hand, results in smaller effective device width which leads to current drive that is lower than the perfectly aligned contacts (structure B).
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The body voltage distributions provide more insight into how body contact misalignment can affect performance of the devices and can be determined from the three-dimen-
Fig. 8. Body voltage distribution along the device width for the three different misalignment schemes.
Fig. 6. Top view of three misalignment structures, (A) DX = 50 nm, (B) DX = 0 and (C) DX = +50 nm.
Fig. 7. Novel body contact, IDS vs. VDS for three different misalignment schemes.
sional simulations. Fig. 8 shows the body voltage variation along the device width at VGS = 1 V and VDS = 3 V. As can be seen from the figure, the body voltage for structure A increases to a maximum of 650 mV. On the other hand, when P+ implant tip reaches to the body region as case C, the maximum body voltage drops to 310 mV. This amounts to a reduction of 80 mV from that of perfectly aligned body contact and is due to the wider body contact, which leads to less body contact resistance for the structure C. The higher body potential for situation A leads to lower breakdown voltage in comparison to structure B due to the activation of lateral bipolar at lower drain voltages. Furthermore, the breakdown voltage is equal for both the structures B and C since the average body voltage is almost equal. Comparing the current drives in Table 2 with structure B, one can see higher current drive for structure A (107%) and less for structure C (95%). The increased body voltage and decreased threshold voltage results in higher current and slight reduction in breakdown voltage. On the other hand, the reduced effective device width is responsible for the decrease in current drive in structure C compared to perfectly aligned body contact case. However, the on-resistance of the devices with structures B and C are relatively equal. Based on the above discussion, it is desirable to avoid the situation where the body contacts moves away from the body as in situation A of Fig. 6. This can be achieved by intentionally shifting the P+ implant diamond region in physical layout design to target structure C (DX = +50 nm) as the ideal body-contacted structure, therefore avoiding the effect of (negative) misalignment. Although this comes at the expense of a relatively reduced drive current capability (reduced effective width), it insures the presence of a body contact region with better transistor cell density and performance compared to conventional structures.
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Table 2 Effect of body contact misalignment on characteristic of the device
VBR (V) Drive current RON (X)
Structure A (DX = 50 nm)
Structure B (DX = 0)
Structure C (DX = + 50 nm)
Comment
6.4 107% 212
6.7 104% 221
6.7 95% 221
VGS = 1 V (on-state breakdown) Ratio of IDS at VGS = 1 V, VDS = 2 V to the reference SOI VGS = 3 V, VDS = 50 mV
4. Experimental results Floating body effects can also be observed in Bulk high voltage devices due to the large impact ionization current and high substrate resistance. Body contacts are used to increase breakdown voltage and eliminate the kink in the output current. Furthermore, to increase the latch-up immunity in CMOS technology body contacts are required. In order to demonstrate the performance functionality of the proposed structure, a test chip containing a set of NMOS devices with different body P+ contact structures (floating, CMOS conventional BTS, and proposed BTS) along with several CMOS and LDMOS devices is designed. The technology is based on a fully manufacturable bulk CMOS process targeting power conversion markets [15] with a high resistivity P-type float-zone wafer substrate, on which an N-well implant is performed with a subsequent drive. To form the body region of the tested NMOS devices, a P-tub implant and a subsequent drive are performed. The P-tub is implanted in the N-well region prior to growing the field oxide. The gate regions are then formed. To produce the source and drain regions, a P+ and N+ implants are performed followed by a 900 C
Fig. 10. Drain current vs. drain voltage for the three devices. Table 3 Breakdown voltage measurement
VBR (V)
Floating body
Conventional body contact
Novel body contact
Comment
4.6
13.75
13.78
Off-state breakdown
anneal and the subsequent formation of interlayer dielectric, metal, and final passivation layers. Fig. 9 depicts the cross-section of the three NMOS devices tested. A test setup employing a probe station with HP4156 Semiconductor Parameter Analyzer is used for the measurements of IDS–VDS output curves and the breakdown voltage of the three devices. Fig 10 displays the output curves of the tested structures at a gate voltage of 5.0 V. Here, the N-well is tied to 5.0 V supply and the substrate is grounded. As evident from the Figure, the proposed structure yields almost identical current drive results as the conventional one and that the FB effects are clearly not present. This is further supported by the breakdown voltage results shown in Table 3. These findings clearly demonstrate the viability of the structure for SOI CMOS type devices. 5. Conclusion
Fig. 9. Cross-section of the three NMOS devices fabricated: (A) bulk, (B) conventional body-contacted (top view) and (C) novel body-contacted device (top view).
A simple body contact structure is described to optimally suppress the floating body effects in partially depleted SOI devices. The structure requires only a novel layout design for the P+ diffusion region; no manufacturing
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process modification is required. Using the proposed structure, 3D simulations were performed and showed improved performance in comparison to floating body structures. Experimental data of the fabricated devices confirmed the simulation results. The simple nature of the described structure offers the possibility of its extension to other type of device structures and technologies.
References [1] Shahidi GG. SOI technology for the GHz era, IBM J Res Dev 2002;42(2/3):121–31. [2] Dallman DA, Shenai K. Scaling constraints imposed by self-heating in sub-micron SOI MOSFET’s. IEEE Trans Electron Dev 1995;42(March):489–96. [3] Colinge JP. Silicon-on-insulator technology: materials to VLSI. Kluwer Academic Publishers; 1997. [4] Horiuchi M, Tamura M. BESS: a source structure that fully suppresses the floating body effects in SOI CMOSFET’s. IEEE Trans Electron Dev 1998;45(May):1077–83. [5] Nishiyama A, Arisumi O, Yoshimi M. Suppression of the floating body effect in partially depleted SOI MOSFET’s with SiGe source and its mechanism. IEEE Trans Electron Dev 1997;44(December): 2187–92. [6] Yunlong L, Xinyu L, Zhiyong Z, He Q. A novel Salicide bodycontacted structure for partially depleted SOI nMOSFETs. In: Proc of 6th international conference on solid-state and integrated-circuit technology, vol. 1; 2001. p. 531–34.
[7] Kuehne SC, Chan ABY, Nguyen CT, Wong SS. SOI MOSFET with buried body strap by wafer bonding. IEEE Trans Electron Dev 1998;45(May):1084–91. [8] Lee J, Kim H, Kim J, Lee W, Oh J, Kang D, et al. Performance improvements in high-density DRAM application using 0.15 lm body-contacted SOI technology. In: Proc of IEEE international SOI conference; 2000. p. 76–7. [9] Kotani N, Ito S, Yasui T, Wada A, Yamaoka T, Hori T. Suppression of leakage current in SOI CMOS LSIs by using silicon sidewall body contact (SSBC) technology. In: Symposium on VLSI technology digest of technical papers; 2002. p. 44–5. [10] Daghighi A. Area efficient body contact for partially depleted SOI MOSFETs. Ph.D. Thesis 2004. Washington State University. [11] Daghighi A, Osman MA. A two-dimensional model for investigating body contact structures in PD SOI MOSFETs. J Microelectron Eng 2003;70(October):83–92. [12] DESSIS Manual. ISE integrated system engineering, Version 7.0; 2001. [13] MESH Manual. ISE integrated system engineering, Version 7.0; 2001. [14] Daghighi A, Osman MA. Three-dimensional simulation of body contact structures in PD SOI MOSFETs. In: Proc of the 15tth IEEE UGIM symposium; July 2003. p. 288–91. [15] Imam M, Hossain Z, Quddus M, Adams J, Hoggatt C, Ishiguro T, et al. Design and optimization of double-resurf high-voltage lateral devices for a manufacturable process. IEEE Trans Electron Dev 2003;50(July):1697–701. [16] Daghighi A, Osman MA. Small signal analysis of a SOI MOSFET device with a novel area efficient body contact. Proc IEEE SoutheastCon 2005:88–91.
Solid-State Electronics 52 (2008) 196–204 www.elsevier.com/locate/sse
Review
An area efficient body contact for low and high voltage SOI MOSFET devices Arash Daghighi b
a,*
, Mohamed Osman b, Mohamed A. Imam
c
a Department of Electrical Engineering, Islamic Azad University Majlesi Branch, Isfahan, Iran School of Electrical Engineering and Computer Science, Washington State University, Pullman, WA 99164-2752, USA c ON Semiconductor, 5005 East McDowell Road, MD D145, Phoenix, AZ 85008, USA
Received 7 January 2007; received in revised form 14 September 2007; accepted 24 October 2007 Available online 21 December 2007
The review of this paper was arranged by Prof. S. Cristoloveanu
Abstract A simple and high-performance area efficient body-tied-source (BTS) contact for SOI MOSFET is presented. By simple modification to the physical layout and without introducing any increase to the fabrication process steps, the proposed body contact can be implemented. Three-dimensional (3D) non-isothermal simulation on SOI CMOS devices showed higher current drive while floating body effects were completely suppressed. In addition, improved performance is achieved when comparing on-resistance (RON) and breakdown voltage (VBR) with the conventional BTS structures. The new body contact structure is applicable to both low and high voltage (planar or trench) SOI and bulk devices. Experimental results obtained from fabricated bulk MOSFET devices utilizing the proposed body contact structure agreed well with the simulation findings. 2007 Elsevier Ltd. All rights reserved. Keywords: High voltage; Low voltage; Partially depleted SOI MOSFET; On-resistance; Breakdown voltage; Floating body effects; Body contact; Threedimensional simulation; Non-isothermal drift-diffusion model
Contents 1. 2. 3.
4. 5.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-dimensional simulation model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1. New body contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2. Body contact misalignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1. Introduction
*
Corresponding author. Tel.: +98 311 6268408. E-mail address: [email protected] (A. Daghighi).
0038-1101/$ - see front matter 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.10.052
Recently, there has been a growing interest in using SOI for high speed digital and RF circuits because it offers performance gain over Bulk CMOS in terms of speed, isolation, density, yield and performance gain in low/high
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power electronics [1]. Additionally, SOI MOSFET has been the technology of choice for radiation hard, space and hostile environment applications. As the technology moves to the deep sub-micron generation, its application is spreading to microprocessors, memories, RF CMOS and low power electronics. However, compared to bulk MOSFETs, the static and dynamic performances of SOI MOSFETs are considerably different due to various effects that are introduced by the complete isolation of the devices. The presence of buried oxide layer results in a floating body region and its low thermal conductivity causes self-heating effects [2]. The area efficiency of floating body design configuration makes it more desirable in high-density applications. However, floating body device design complicates device performance and suffers from several floating body modulation effects such as drain voltage induced fluctuations in body potential which give rise to reduction of the breakdown voltage, variations in the threshold voltage, current kink, increased noise and disturbances in the static and dynamic characteristics of the device. The body potential modulation and the associated effects are critical especially for partially depleted (PD) SOI devices [3] where depending on the device bias condition, the body potential may be elevated and attain a positive value which causes the conduction of a parasitic lateral bipolar junction transistor (BJT) formed with the source as emitter, floating body as base, and drain as collector. This lateral BJT in the SOI MOSFET structure is important as it accounts for the loss of the gate control and poor breakdown voltage characteristics. Several approaches have been proposed to suppress the floating body effects in PD SOI. These include introducing
197
recombination centers for the holes below the source, using Ge implantation in the source region, or making a path for the generated holes in the body to escape to contact(s) [4– 9]. The first method adds to the fabrication process complexity while the Ge implanted source structure is not CMOS compatible. All of the methods that have been developed to make a path for the generated holes (such as H-gate and body-tied-source structures) suffer from one or more of the following drawbacks: (1) increased fabrication process complexity, (2) larger device area, or (3) lower effective device width. For high voltage power ICs the impact is translated to the ‘‘RON · area’’ figure of merit. This indicates that for the same area devices, the one with the lower RON (higher current drive) has a smaller figure of merit. A lower ‘‘RON · area’’ allows a designer to use a smaller high voltage MOSFET to meet ON-resistance requirements for a given application, which reduces the area and cost of a power integrated-circuit. In this paper, we propose a novel area efficient body contact for SOI devices and investigate its performance using three-dimensional simulation study. Additionally, to confirm the simulation findings, we also fabricated bulk n-MOSFET structures with both conventional and the proposed body contacts. Fig. 1 shows the layout view of few conventional SOI body contact structures and our proposed body contact. The H-gate body contact shown in Fig. 1A, has considerably large footprint (i.e. area inefficient) whereas allowing independent control of the body voltage. Body-tied-source (BTS) structure controls body voltage by introducing P+ regions in the source end of the device to allow low resistance path(s) for the holes at the expense of reduced current drive for the device as depicted in Fig. 1B and C shows the proposed area efficient
Fig. 1. SOI body contacts (arrows show the current flow in the channel), (A) H-gate, (B) conventional body-tied-source and (C) novel body contact.
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body contact, which can be implemented by simple modification to the physical layout design [10]. Compared to the H-gate body contact (Fig. 1A), the novel body-contacted device occupies a smaller silicon area whereas the current drives are approximately equal. This is due to the small contact area at the edge of the P+ doped region to the body of the device, which results in almost equal effective device widths. In comparison with the conventional body-tiedsource structure (Fig. 1B), the proposed body-contacted device has a larger effective width and as a result a higher current drive for the same drawn widths. In this work, we investigate the performance of the proposed body contact structure and analyze its effect in suppressing floating body effects using three-dimensional (3D) device simulation. In the following sections, we review the 3D simulation model and analyze the simulation results of the proposed structure and the conventional structures. The three-dimensional simulation model is explained in Section 2, simulation results of the new body contact and the effect of process misalignment on the performance of the device as obtained from simulations are presented in Section 3, followed by discussion of the measurement results on fabricated bulk n-MOSFETs in Section 4 and a conclusion in Section 5. 2. Three-dimensional simulation model The Body of BTS SOI MOSFET is not uniformly at ground potential due to the high sheet resistance of the body. As holes generated in impact ionization process move toward the body contacts, a potential gradient builds up along the device width [7]. The increase in body voltage decreases the threshold voltage and consequently increases the channel current and portions of the device away from the body contacts pass higher channel current. This changes the operation characteristics of the device in the third dimension (along device width). In addition, body-contacted devices can be viewed as a series of diodes P+/P/N+ (inactive regions) and regular active MOSFETs. Therefore, three-dimensional simulation is required to simulate body-contacted devices. In an earlier investigation, we proposed a simple 2D model for simulation of body-contacted devices using fictitious photo-generated e-h pairs to induce the floating body voltage [11]. The 2D model provides a computational efficient approach to get a first order estimate of the body potential profile, but does not allow investigating I–V characteristics, accurate carrier potential and charge distributions. This makes it necessary to use three-dimensional simulation for our detailed analysis. The low thermal conductivity of the buried oxide layer beneath the active silicon film layer in SOI MOSFETs causes self-heating effect, which strongly affects carrier mobility and electron-hole generation rates. Better comprehensibility, we used non-isothermal drift-diffusion model to take into account the impact of lattice temperature variation on performance of the device. The three-dimensional
simulation was performed using ISE TCAD’s device simulator (DESSIS) [12]. It is well known that drift-diffusion approach overestimates the impact ionization process. The model for generation due to impact ionization, implemented in DESSIS, is given by [12] Gk ¼ an nV n þ ap pV p
ð1Þ
where Vn,p denotes drift velocity and n (p) denotes the carrier concentration of electrons (holes). The model for impact ionization generation coefficients (an, ap) suitable for simulation at high temperatures (300–700 K) is given by an;p ðF ; T Þ ¼
F aðT Þ þ bðT ÞedðT Þ=ðF þCðT ÞÞ
ð2Þ
where F is the driving force, a(T), b(T), c(T) and d(T) are the temperature dependent model parameters. They can be defined by constant coefficient functions. The temperature dependence of model parameters, for electrons, can be read as [12]: aðT Þ ¼ a0 þ a1 T a2 ;
bðT Þ ¼ b0 ;
dðT Þ ¼ d 0 þ d 1 T þ d 2 T 2
cðT Þ ¼ c0 þ c1 T þ c2 T 2 ; ð3Þ
In order to reduce the impact ionization generation rate, we noticed that drift-diffusion approach can not reproduce velocity overshoot. In this case, the hydrodynamic model provides a very good compromise. As a result, we modified the coefficients (ai, bi, ci and di) to get a first order estimate of avalanche generation using hydrodynamic model. For this purpose, the generation rate in the pinch-off region of two identical devices using non-isothermal drift-diffusion and hydrodynamic models were compared. Having modified the above coefficients, the avalanche generation rates using both the models were equal in the biasing points of interest. ISE TCAD MESH routine was used to generate the grid for the 3D simulations [13]. Impurity concentrations and user required element sizes can be described using dimension-independent syntax and grids can be adapted according to analytical profiles. The desired grid point densities for a given concentration profiles are obtained by refining the elements in an anisotropic way, generating fine elements for the critical parts of the device and coarse elements in the bulk regions. Fig. 2 shows the generated grid structure for part of the device including one of the proposed body contacts. As can be seen, very fine grid structure is required to cover body contacts especially at the edges where the body contact connects to the body of the device. We used approximately 2000 grid points for each body contact. For the case of three body-contacted structure, this adds 6000 grid points to the total number of the grids required to capture the physical characteristic of the device making the simulation more complex. The parameters of the simulated PD SOI MOSFET device shown in Fig. 3 are: buried oxide layer thickness tbox = 0.4 lm; Silicon film thickness tbody = 0.15 lm; gate ˚ . The source and drain lateral difoxide thickness tox = 80 A fusions were modeled by Gaussian profiles along the X-axis.
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Fig. 2. 3D Mesh structure (part of the device including one of the novel body contacts is shown in the picture).
Fig. 3. 3D BTS SOI structure.
The gate of the devices was an n+polysilicon with dimensions L = 0.35 lm and W = 5 lm. The bulk contact was an electrical contact at zero volt and thermal contact at 300 K. 3. Simulation results Using non-isothermal drift-diffusion model, threedimensional simulations of body-contacted to source structures were examined. All the simulation results on current
drive, body voltage and breakdown voltage are presented at gate voltage of 1.0 V. This is due to the fact that the largest impact ionization rate happens at low gate voltages where the body effect is the largest [7,11]. In the following, Section 3.1 shows the simulation results of a floating body, two conventional BTS structures and the new body contact. In Section 3.2, the effect of process misalignment on the performance variation of the new body-contacted devices is discussed.
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3.1. New body contact Four device structures were simulated: (1) a floating body (FB) device, (2) a conventional body-contacted device with two body contacts (one at each end of the source as shown in Fig. 1B, and each had a width WB = 0.35 lm), (3) a conventional body-contacted device with three body contacts, one at each source end and one in the middle of source with WB = 0.35 lm as depicted in Fig. 3, and (4) a device with three of the proposed novel body contacts, one at both ends and one in the middle of the source. Fig. 4A has already been reported [16] and it shows the current–voltage characteristic (IDS vs. VDS) of the four simulated devices. As can be seen, the proposed body contact eliminates the kink inherent in the FB device characteristic. Also the novel body-contacted device has a higher current drive than the device with three conventional body contacts structure. Reducing the number of conventional contacts to two, increases current drive at the expense of increased body voltage, dynamic variation of threshold voltage,
Fig. 4. (A) Drain current vs. drain voltage; (B) sub-threshold characteristic.
Fig. 5. Body potential variation along the device width.
and lower breakdown voltage. Notice that the drain current starts increasing at higher rate for drain voltages beyond 2 V indicating lower breakdown voltage. The sub-threshold characteristics of the simulated devices are shown in Fig. 4B. Significant sub-threshold slope variation of DS = 16.8 mV/dec can be observed when the drain voltage changes from 50 mV to 1.5 V for the floating body device. This value decreases to DS = 3.3 mV/dec for the proposed novel body-contacted device and DS = 1.1 mV/dec for the three conventional body contacts structure. This indicates that novel body contact (narrow contact) is as effective as conventional body contacts (wide contacts) in controlling the body voltage [14]. The magnitude of the resulting floating body voltage near the source body junction provides a more accurate way of comparing the different BTS structures. Fig. 5 shows the magnitude of the electrostatic potential along a line close to and parallel to the body/source junction for the FB and BTS structures. This provides a measure of the floating body voltage at gate voltage of 1 V and drain voltage of 3 V. Note that introducing two conventional body contacts at the ends of the source reduces maximum floating body voltage from about 770–480 mV. The maximum body voltage reduces to 390 mV and 170 mV for the novel proposed body contact and three conventional body contact structures, respectively. The breakdown voltage and on-resistance of the devices are also investigated and the simulation results are summarized in Table 1. The on-state breakdown voltage shows the impact of floating body voltage on the breakdown characteristic while the device is turned on. The breakdown voltage characteristic of the proposed body contact is clearly better than that of the floating body and the conventional two body-contacted structures. In order to simulate the onresistance, gate voltage is ramped to 3 V and drain voltage to 50 mV. Faced with consistent divergence of non-isothermal drift-diffusion simulation during ramping gate voltage, we ran 2D simulations to determine the magnitude of the
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Table 1 Breakdown voltage, drive current and on-resistance of the devices Floating body
2 Body contacts
3 Body contacts
Novel body contact
Comment
VBR (V)
4
5
6
6.7
VGS = 1V (on-state breakdown)
Drive current
163%
86%
79%
104%
Ratio of IDS at VGS = 1 V, VDS = 2 V to the reference SOI
RON (X)
203
235
250
221
VGS = 3 V, VDS = 50 mV
drain current and the role of self-heating. The 2D non-isothermal simulation on a floating body device revealed negligible self-heating effects. Consequently, we used isothermal drift-diffusion model for our 3D simulations of the on-resistance (RON). The proposed novel body-contacted device showed smaller RON compared to both conventional body-contacted devices due to the increased channel current. However, it’s less than the floating body device, which has the best RON. Furthermore, we also examined influence of different body contact structures on the device current. The strong dependence of the current on the floating body voltage, which is determined by the geometry and location of body contacts, requires defining a suitable structure to act as a reference. To overcome this problem, we chose as a reference a SOI device with uniform body voltage distribution along the device width. A uniform body voltage distribution can be achieved in a device structure with a narrow and continues P+ implant under the source region and connected to the source contact. The drain current for this device was then determined at a gate voltage of 1 V and drain voltage of 2 V through simple two-dimensional simulations and then scaled to determine the desired current for any device width. Table 1 shows the ratios of current drives of the body-contacted devices (obtained from three-dimensional simulations) to that of the reference body-contacted SOI device. Notice that the floating body device exhibits a significant current drive increase (63%) due to lowering of threshold voltage and activation of lateral BJT. The proposed novel body-contacted device shows a slight increased current (104%) drive due to the modulation in body voltage. On the other hand, there is large reduction in the current drives of both two conventional body-contacted (86%) and three conventional body-contacted (79%) devices due to the decreased effective device width. Influence of the new body contact on the output conductance and transistor parasitic capacitances were also investigated. Body-contacted devices are the major component of analog circuits using partially depleted SOI MOSFETs. One of the main device characteristics, which directly affects the gain of amplifiers is the output conductance (gDS) at the biasing point of interest. It has been shown that the new body contact and the three conventional body-contacted structures show the lowest variation in drain conductance as drain voltage changes [16]. However, drain conductance of the two conventional body-contacted
device showed drain voltage dependency. For analog applications this translates to the undesired reduction of intrinsic gain of transistor. In addition to the output conductance, parasitic capacitances have an important impact on the performance of the circuits especially for high speed applications such as microprocessors and analog radio frequency (RF) circuits. Total extrinsic plus intrinsic gatesource (CGS) capacitance as the most sensitive capacitance to the geometry of the body-tied-source contacts were also examined [16]. It was shown that CGS of the new body contact in saturation region is equal to that of the conventional body contact structures and it was constant as drain voltage increased. This was different with the floating body device where CGS increased as drain voltage increased due to the variation of the body voltage. 3.2. Body contact misalignment One major concern regarding the proposed body contact is the effect of process misalignment of P+ doped regions on device performance. The ideal situation occurs when the tip of the P+ implant diamond region touches the source/body junction as shown in Fig. 6 (structure B) which lead to zero misalignment (DX = 0). Two other possible situations are when the tip shifts away from junction and in this situation there is no direct contact between the P-body and the P+ contacts (Structure A where DX = 50 nm). The other situation is where the tip shifts inside the P-body making a wider contact to the body (structure C where DX = 50 nm). Fig. 7 shows the simulation results of drain current vs. drain-source voltage for these three cases. It’s interesting to note that for structure A, the I–V characteristic in Fig. 7, does not exhibit a well defined kink as in floating body device (see Fig. 4A) and instead shows a gradual increase beyond 1.3 V at rates well below that for the FB device. This is due to the fact that accumulated holes in the body region face low potential barrier to escape to body contacts. Note that in this case, part of the source near the tip of body contact is depleted and this reduces the effective device width even smaller than the effective device width in Structure B. However, at higher drain voltages, body voltage increases resulting in increased channel current. Structure C, on the other hand, results in smaller effective device width which leads to current drive that is lower than the perfectly aligned contacts (structure B).
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The body voltage distributions provide more insight into how body contact misalignment can affect performance of the devices and can be determined from the three-dimen-
Fig. 8. Body voltage distribution along the device width for the three different misalignment schemes.
Fig. 6. Top view of three misalignment structures, (A) DX = 50 nm, (B) DX = 0 and (C) DX = +50 nm.
Fig. 7. Novel body contact, IDS vs. VDS for three different misalignment schemes.
sional simulations. Fig. 8 shows the body voltage variation along the device width at VGS = 1 V and VDS = 3 V. As can be seen from the figure, the body voltage for structure A increases to a maximum of 650 mV. On the other hand, when P+ implant tip reaches to the body region as case C, the maximum body voltage drops to 310 mV. This amounts to a reduction of 80 mV from that of perfectly aligned body contact and is due to the wider body contact, which leads to less body contact resistance for the structure C. The higher body potential for situation A leads to lower breakdown voltage in comparison to structure B due to the activation of lateral bipolar at lower drain voltages. Furthermore, the breakdown voltage is equal for both the structures B and C since the average body voltage is almost equal. Comparing the current drives in Table 2 with structure B, one can see higher current drive for structure A (107%) and less for structure C (95%). The increased body voltage and decreased threshold voltage results in higher current and slight reduction in breakdown voltage. On the other hand, the reduced effective device width is responsible for the decrease in current drive in structure C compared to perfectly aligned body contact case. However, the on-resistance of the devices with structures B and C are relatively equal. Based on the above discussion, it is desirable to avoid the situation where the body contacts moves away from the body as in situation A of Fig. 6. This can be achieved by intentionally shifting the P+ implant diamond region in physical layout design to target structure C (DX = +50 nm) as the ideal body-contacted structure, therefore avoiding the effect of (negative) misalignment. Although this comes at the expense of a relatively reduced drive current capability (reduced effective width), it insures the presence of a body contact region with better transistor cell density and performance compared to conventional structures.
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Table 2 Effect of body contact misalignment on characteristic of the device
VBR (V) Drive current RON (X)
Structure A (DX = 50 nm)
Structure B (DX = 0)
Structure C (DX = + 50 nm)
Comment
6.4 107% 212
6.7 104% 221
6.7 95% 221
VGS = 1 V (on-state breakdown) Ratio of IDS at VGS = 1 V, VDS = 2 V to the reference SOI VGS = 3 V, VDS = 50 mV
4. Experimental results Floating body effects can also be observed in Bulk high voltage devices due to the large impact ionization current and high substrate resistance. Body contacts are used to increase breakdown voltage and eliminate the kink in the output current. Furthermore, to increase the latch-up immunity in CMOS technology body contacts are required. In order to demonstrate the performance functionality of the proposed structure, a test chip containing a set of NMOS devices with different body P+ contact structures (floating, CMOS conventional BTS, and proposed BTS) along with several CMOS and LDMOS devices is designed. The technology is based on a fully manufacturable bulk CMOS process targeting power conversion markets [15] with a high resistivity P-type float-zone wafer substrate, on which an N-well implant is performed with a subsequent drive. To form the body region of the tested NMOS devices, a P-tub implant and a subsequent drive are performed. The P-tub is implanted in the N-well region prior to growing the field oxide. The gate regions are then formed. To produce the source and drain regions, a P+ and N+ implants are performed followed by a 900 C
Fig. 10. Drain current vs. drain voltage for the three devices. Table 3 Breakdown voltage measurement
VBR (V)
Floating body
Conventional body contact
Novel body contact
Comment
4.6
13.75
13.78
Off-state breakdown
anneal and the subsequent formation of interlayer dielectric, metal, and final passivation layers. Fig. 9 depicts the cross-section of the three NMOS devices tested. A test setup employing a probe station with HP4156 Semiconductor Parameter Analyzer is used for the measurements of IDS–VDS output curves and the breakdown voltage of the three devices. Fig 10 displays the output curves of the tested structures at a gate voltage of 5.0 V. Here, the N-well is tied to 5.0 V supply and the substrate is grounded. As evident from the Figure, the proposed structure yields almost identical current drive results as the conventional one and that the FB effects are clearly not present. This is further supported by the breakdown voltage results shown in Table 3. These findings clearly demonstrate the viability of the structure for SOI CMOS type devices. 5. Conclusion
Fig. 9. Cross-section of the three NMOS devices fabricated: (A) bulk, (B) conventional body-contacted (top view) and (C) novel body-contacted device (top view).
A simple body contact structure is described to optimally suppress the floating body effects in partially depleted SOI devices. The structure requires only a novel layout design for the P+ diffusion region; no manufacturing
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process modification is required. Using the proposed structure, 3D simulations were performed and showed improved performance in comparison to floating body structures. Experimental data of the fabricated devices confirmed the simulation results. The simple nature of the described structure offers the possibility of its extension to other type of device structures and technologies.
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