An automated, low power, high speed complementary PLA design system for VLSI applications

An automated, low power, high speed complementary PLA design system for VLSI applications

590 World Abstracts on Microelectronics and Reliability 6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S , SYSTEMS AND EQUIPMENTS A sin...

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590

World Abstracts on Microelectronics and Reliability 6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,

SYSTEMS

AND

EQUIPMENTS

A single-chip CMOS analog front-end for high-speed modems. B. FOTOUHI, R. GREGORIANand W. KLINE. Microelectron. J. 15 (4), 5 (1984). A single-chip analog front-end for highspeed modems has been developed in 5p_ polysilicon CMOS process. The chip contains a 10-bit A/D and an 8-bit D/A converters, a novel 128-step 0.375dB/step programmable gain stage, 20-step I dB/step programmable attenuator, switched-capacitor and active RC low-pass and high-pass filters for the receive and transmit directions, and all the associated TTL level compatible control logic. A CMOS band-gap voltage reference is shared between the receiver and transmitter. The chip, housed in 40-pin plastic package, is 223 x 219 mil 2 and dissipates 120 mW using _+5 V supplies.

ambient influences. Externally the noise generator appears in the form of an operation amplifier, whose frequency-response can be shaped with external components.

An automated, low power, high speed complementary PLA design system for VLSI applications. S. POWELL, E. IODICE and E. FRIEDMAN. Microelectron. J. 15 (4), 47 (1984). An automated Programmable Logic Array (PLA) design system that is fully compatible with the density and power constraints of VLSI is described. A low power CMOS version of the PLA has been integrated into a technology independent, automated PLA generation system to provide a self-contained, highly functional and low power, dense cell design capability. A description of the Complementary Programmable Logic Array (CPLA) technique is provided, particularly in terms of its integration into the automated PLA design system. Details of the system's input formats, minimization and verification capabilities, design flexibility, CAD compatibility, and processing speeds are discussed.

A small experimental robotic PCB assembly system. WILLIAM L. HUCK. Solid St. Technol. 303 (September 1984). To provide flexible automation for low volume production runs in order to increase productivity, an approach is described which employs microprocessor controlled robotic systems, custom configured from off-the-shelf high speed, high precision positioning subassemblies. Customized end-effectors provide vacuum and magnetic grippers and tooling for PCB assembly requirements.

The design of a truly random monolithic noise generator. W. T. PENZHORN. Microelectron. J. 15 (4), 29 (1984). This paper describes the design of a monolithic analogue noise generator, which meets the following objectives: it is self-contained in a conventional IC package, needs no unconventional precautions and operates from a standard + 5 V supply. It dissipates less than 20mW and produced a truly random gaussian noise voltage of approximately 500 mV (rms) with a band-width of 1 kHz-100kHz. Unlike the pseudo-random numbers generated by shift registers, truly random numbers can be obtained by clipping the analogue noise with an external comparator and sampling the resulting random square wave. Shot and thermal noise in bipolar transistors, manufactured with a standard bipolar process, serve as primary noise sources. The noise generated by a conventional differential amplifier, connected as a unity gain buffer, is used as a basic noise source. The noise produced by two independent unity gain buffers is differentially amplified, in order to reduce

CMOS single-chip digital signal processor. HIDEO HARA, TAKASHIAKAZAWAand YOSHIMUNEHAGIWARA.Microelectron. J. 15 (4), 20 (1984). The HSP (HD61810) is a single-chip digital signal processor which includes a high speed arithmetic logic unit, a high speed multiplier, and a large memory on a single silicon chip. Its architecture features floating point arithmetic and a pipeline structure. With the floating point arithmetic operation, the HSP can manipulate a wide dynamic range of data. The instruction cycle of the HSP is 250ns. One multiply/add operation can be executed per cycle. The HSP uses 3 gm CMOS technology and so achieves low power consumption. It is programmed by an internal instruction ROM.

7. S E M I C O N D U C T O R

INTEGRATED

ROMs to bubbles. The selection of nonvolatile memories. IAN DUTHIE. Electron. Power 865 (November/December 1984). An overview of the nonvolatile memory market is presented with the advantages and limitations of the alternative technologies discussed, together with the application areas most suited to the different choices. Each choice can still offer the user a specific advantage for his application depending on his primary concern, which may be cost, flexibility, reliability or environmental needs.

Moisture content control using alumina sensor. CARL M. ROBERTS,JR. Semiconductor Int. 134 (August 1984). Aluminum oxide sensor controls header sealed package moisture content at the point of package seal in an IC assembly process.

CMOS for high-density gate arrays. WOLFGANG ZLAMAL. Electron. Power 874 (November/December 1984). The recognition of the advantages of high-speed CMOS gate arrays is making this one of the fastest growing and competitive markets within the semiconductor industry.

CIRCUITS,

DEVICES

AND

MATERIALS

Persistent photoconductivity in sulfur-diffused silicon. H. J. QUEISSER and D. E. THEODOROU. Solid St. Commun. 51 (11), 875 (1984). A large persistent photoconductivity effect is found in single-crystal p-type bulk silicon covered by an ntype surface layer produced by a sulfur diffusion. Recombination of carriers is precluded by their spatial separation in the n p junction. The photogenerated holes exceed the relatively few remaining acceptor-introduced holes at our measurement temperature of 45 K, while the corresponding electrons are captured at the sulfur donors.

holes and using the self-consistent model development earlier for electrons, the value of the Fermi energy and the screening length is determined. The following scattering types are considered: scattering by acoustical phonons, scattering by non-polar optical phonon and scattering by ionized impurities. The influence of interband transition of heavy and light holes on the total relaxation time is analysed. It is shown that it does not lead to essential changes in mobility. The obtained results are compared with experimental results and satisfactory agreement is found.

Mobility of holes in p-type silicon determined by the selfconsistent method. D. A. TJAPKIN, T. I. Tostc and M. M. JEVTIC. Solid-St. Electron. 27 (7), 667 (1984). The mobility of majority carriers is calculated in p-type silicon in the impurity concentration range from 1016 to 102°cm -3. Taking into account the complexity of the band structure of

A valence bond theory of off-center imPurities in silicon, R. P. MESSMER and P. A. SCHULTZ. SolidSt. Commun. 52 (5), 563 (1984). We present the first cluster calculations which explicitly include electronic correlation effects in the study of impurities in Si (e.g. nitrogen and oxygen). The calculations provide a natural explanation of the observed off-center