An efficient approach to design a reversible control unit of a processor

Sustainable Computing: Informatics and Systems 3 (2013) 286–294

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An efficient approach to design a reversible control unit of a processor Lafifa Jamal, Md. Masbaul Alam, Hafiz Md. Hasan Babu ∗ Department of Computer Science and Engineering, University of Dhaka, Dhaka 1000, Bangladesh

a r t i c l e

i n f o

Article history: Received 22 January 2012 Received in revised form 1 June 2013 Accepted 25 June 2013 Keywords: Reversible logic Reversible control unit Quantum cost Garbage output

a b s t r a c t Reversible logic has captured significant attention in recent time as reducing power consumption is one of the main concern of digital logic design. It consumes less power by recovering bit loss from its unique input–output mapping. In this paper, we propose a reversible control unit, which is first ever proposed in literature. Two new 4 × 4 reversible gates, namely HL gate and BJ gate, are proposed to design reversible decoder and J-K flip-flop. An algorithm has been shown to design a reversible control unit. On the way to design the control unit, we propose reversible decoder, sequence counter, instruction register and control logic gates. These circuits are analyzed with the existing ones. The comparative results show that the proposed design outperforms the existing designs in terms of numbers of gates, garbage outputs, delay and quantum cost. In addition, some lower bounds on the numbers of gates and garbage outputs of the proposed control unit have also been presented. © 2013 Elsevier Inc. All rights reserved.

1. Introduction The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. According to Landauer [1], in logic computation every bit of information loss generates kTln2 joules of heat energy where k is the Boltzmann constant of 1.38 × 10−23 J/K and T is the absolute temperature of the environment. At room temperature the dissipating heat is around 2.9 × 10−21 J. Reversible circuits are fundamentally different from traditional irreversible ones. In reversible logic, no information is lost, i.e. the circuit that does not lose information is reversible. Bennett [2] showed that zero energy dissipation would be possible if the network consists of reversible gates only. Thus reversibility will be an essential property for the future circuit design. Synthesis of reversible logic is more complicated than irreversible one as it imposes many design constraints [3]. A reversible circuit therefore should have the following attributes [4]: • Garbage output should be as minimum as possible. • Number of reversible gate should be as minimum as possible. • Input lines that are either 0 or 1, known as constant input, should be as minimum as possible.

have proposed different components of control unit with improvement in terms of cost comparing with the existing designs. The different components are reversible decoder, sequence counter, instruction register and control logic gates. Finally, we have proposed the reversible architecture of control unit, which will result less power dissipation and will improve the performance of different processors. 2. Different reversible gates In this section, we present the basic definitions of reversible logic and an overview on few reversible gates which are relevant with this research work. Definition 2.1.a. A Reversible Gate is a k-input, k-output (denoted by k × k) circuit that produces a unique output pattern [5,6] for each possible input pattern. Definition 2.1.b. Reversible Gates are circuits in which the number of outputs is equal to the number of inputs and there is a one to one correspondence between the vector of inputs and outputs. It is always desirable to realize a circuit with minimum number of gates.

In this paper, we have proposed the reversible implementation of the internal architecture of control unit of a processor. We

Example 2.1. Let the input vector be Iv , output vector be Ov and they are defined as follows, Iv = (Ii , Ii+1 , Ii+2 , . . ., Ik−1 , Ik ) and Ov = (Oi , Oi+1 , Oi+2 , . . ., Ok−1 , Ok ). For each particular i, there exists the relationship Iv ↔ Ov.

∗ Corresponding author. Tel.: +880 1711 351055. E-mail addresses: lafi[email protected] (L. Jamal), polash [email protected] (Md. Masbaul Alam), hafi[email protected] (H.Md. Hasan Babu).

Definition 2.2. The input vector, Iv and output vector, Ov for 2 × 2 Feynman Gate (FG) [7] is defined as follows: Iv = (A, B) and Ov = (P = A, Q = A ⊕ B). The quantum cost of Feynman gate is one [7].

2210-5379/$ – see front matter © 2013 Elsevier Inc. All rights reserved. http://dx.doi.org/10.1016/j.suscom.2013.06.001

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Fig. 1. Garbage output.

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Fig. 5. Block diagram of a 4 × 4 MFRG gate.

3. Optimization parameters

Fig. 2. Block diagram of a 3 × 3 Toffoli gate.

Fig. 3. Block diagram of a 3 × 3 Fredkin gate.

Example 2.2. The block diagram for 2 × 2 Feynman gate is shown in Fig. 1. Feynman gate is also known as CNOT (Controlled Not) gate. The two key reasons to use this gate in reversible circuit are: • Make the copy of an input (putting any of the input a constant 0) • To invert an input bit (putting any of the input a constant 1) Definition 2.3. The input vector, Iv and output vector, Ov for 3 × 3 Toffoli Gate (TG) [8] is defined as follows: Iv = (A, B, C) and Ov = (P = A, Q = B, R = AB ⊕ C). The block diagram for 3 × 3 Toffoli gate is shown in Fig. 2. The quantum cost of Toffoli gate is five [8]. Definition 2.4. The input vector, Iv and output vector, Ov for 3 × 3 Fredkin Gate (FRG) [9] is defined as follows: Iv = (A, B, C) and Ov = (P = A, Q = A B ⊕ AC, R = AB ⊕ A C). The block diagram for 3 × 3 Fredkin gate is shown in Fig. 3. The quantum cost of Fredkin gate is five [9]. Definition 2.5. The input vector, Iv and output vector, Ov for 4 × 4 HNFG Gate [10] is defined as follows: Iv = (A, B, C, D) and Ov = (P = A, Q = A ⊕ C, R = B, S = B ⊕ D). The block diagram for 4 × 4 HNFG gate is shown in Fig. 4. The quantum cost of HNFG gate is two [10]. Definition 2.6. The input vector, Iv and output vector, Ov for 3 × 3 Modified Fredkin Gate (MFRG) [21] is defined as follows: Iv = (A, B, C) and Ov = (P = A, Q = AB ⊕ AC , R = AC ⊕ AB). The block diagram for 3 × 3 MFRG gate is shown in Fig. 5. The quantum cost of MFRG gate is four [21].

The main challenge of designing reversible circuits is to optimize the different parameters which result the design costly. The most important parameters which have dominant contribution in designing reversible circuits are: Garbage Output: Unwanted or unused output of a reversible gate (or circuit) is known as garbage output [6]. More formally, the outputs which are needed only to maintain reversibility are called garbage outputs. For example, to perform XOR between two inputs of a Feynman gate one garbage output is generated, which is shown in Fig. 1 with *. Number of gates: The total number of gates used in a circuit. Minimum possible number of gates must be used in a circuit. Quantum Cost: The quantum cost can be derived by substituting the reversible gates of a circuit by a cascade of elementary quantum gates [11]. Elementary quantum gates realize quantum circuits that are inherently reversible and manipulate qubits rather than pure logic values. The state of a qubit for two pure logic states can be expressed as |  = ˛|0 + ˇ|1, where |0 and |1 denote 0 and 1, respectively, and ˛ and ˇ are complex numbers such that |˛|2 + |ˇ|2 = 1. The most used elementary quantum gates are the NOT gate (a single qubit is inverted), the controlled-NOT (CNOT) gate (the target qubit is inverted if the single control qubit is 1), the controlled-V gate (also known as a square root of NOT, since two consecutive V operations are equivalent to an inversion), and the controlled-V+ gate (which performs the inverse operation of the V gate and thus is also a square root of NOT) [11]. Delay: Delay is one of the most important parameter while designing reversible circuits. Many researchers suggested different definition of delay for reversible circuits. According to [12] delay is defined as follows: The delay of a logic circuit is the maximum number of gates in a path from any input line to any output line. This definition is based on the following assumptions: • Each gate performs computation in one unit time. • All inputs to the circuit are available before the computation begins. The delay of the circuit of Fig. 1 is obviously 1 as it is the only gate in any path from input to output. In this paper, we used the definition of delay defined by Biswas et al. [12] for every calculation. 4. Control unit

Fig. 4. Block diagram of a 4 × 4 HNFG gate.

A control unit is a circuit that directs operations within the computer’s processor by directing the input and output of a computer system. A control unit consists of two decoders, a sequence counter, and a number of control logic gates [20]. It fetches the instruction from instruction register (IR). For example, the block diagram of a 16-bit control unit is shown in Fig. 6. Here, the instruction register consists of 16 bits. The operation code (bit 12 to bit 14) is decoded by the 3-to-8 decoder. The outputs of the decoder are D0 , D1 , . . ., D7 . Bit 0 to bit 11 and bit 15 are fed to the control logic gates. The 4-bit sequence counter counts from 0 to 15. The outputs of the counter

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Fig. 6. Block diagram of a 16-bit control unit.

are decoded into 16 timing signals T0 , T1 , . . ., T15 by the 4-to-16 decoder. 5. Background study In 2011, Aradhya et al. proposed a control unit for arithmetic logic unit in [22]. In 2012, Dixit and Kapse proposed another control unit for arithmetic logic unit in [23]. Both of the designs actually select the operations of arithmetic logic unit based on the combinations of the selection inputs. They are not the actual control unit of a processor. Various designs of reversible decoder have been proposed in [13,17–19]. Buch proposed a design of 2-to-4 decoder in [19] which requires large number of gates, garbage outputs and quantum cost. Huda et al. proposed a generalized approach of reversible n-to-2n decoder [13] which performs much better than [19] in terms of numbers of gates, garbage outputs and quantum cost. Later on, Nachtigal and Ranganathan proposed an improved design of 2to-4 decoder in [18] which requires only one gate. Shamsujjoha and Babu proposed a fault-tolerant generalized design of reversible n-to-2n decoder in [17]. Counter and instruction register of a control unit requires flipflops. If the flip-flop (FF) is designed in an optimized way, the components that consists of flip-flops will also be optimized.

Different approaches of reversible J-K FF have been proposed in [14–16]. Thapliyal et al. designed a J-K FF in [16] which requires large number of gates, garbage outputs, delay and quantum cost. Thapliyal and Ranganathan proposed another design of reversible J-K FF in [15] which has less number of gates, garbage outputs, delay and quantum cost in comparison with [16]. Sayem and Ueda proposed a reversible J-K FF in [14] which perform better than [16] in terms of numbers of gates, garbage outputs and quantum cost. 6. Designs of different components of the proposed control unit In this section, we present the reversible implementation of different components of the control unit. In Sections 6.1 and 6.2, we propose two new reversible gates (namely HL gate and BJ gate) that are used to design decoder and J-K FF. Sections 6.3–6.5 describe the design of reversible 2-to-4, 3-to-8 and n-to-2n reversible decoder, respectively. The complexities of n-to-2n decoder are also described in Section 6.5. The design of reversible J-K FF, sequence counter, instruction register and control gates are shown in Sections 6.6–6.9, respectively. Finally, Section 6.10 presents the construction procedure and the complexities of the proposed control unit.

Fig. 7. Proposed HL gate.

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Table 1 Truth table of the proposed HL gate. Input

Output

A

B

C

D

AB’ ⊕ B’C ⊕ BD’

AB ⊕ B’C ⊕ BD

A’B ⊕ B’C ⊕ BD

AB ⊕ BC ⊕ B’D

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 1 1 1 0 1 0 1 1 0 0 1 0 1 0

0 0 0 1 1 1 0 1 0 0 1 1 1 0 1 0

0 0 1 1 1 0 1 0 0 0 1 1 0 1 0 1

0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1

Table 2 Truth table of the proposed BJ gate. Input

The quantum cost of the BJ gate is twelve. The proposed BJ gate can be used as universal gate. The NAND implementation of the BJ gate is shown in Fig. 8(b).

Output

A

B

C

D

A

AB ⊕ C

A’B ⊕ AC’

A’B ⊕ AC’ ⊕ D

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0

0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0

0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1

6.1. HL gate In this section, a new 4 × 4 reversible gate, namely HL gate is proposed. The proposed gate is shown in Fig. 7(a). The truth table of the proposed HL gate is shown in Table 1. It can be verified from the truth table that the input pattern corresponding to a particular output pattern can be uniquely determined and vice versa. Fig. 7(b) shows that the quantum cost of the proposed HL gate is seven. 6.2. BJ gate In this section, a new 4 × 4 reversible gate, namely BJ gate is proposed. The block diagram of the proposed gate is shown in Fig. 8(a). The truth table of the BJ gate is shown in Table 2. It can be verified from the truth table that the input pattern corresponding to a particular output pattern can be uniquely determined and vice versa.

6.3. Reversible 2-to-4 decoder In this section, we propose two approaches of the design a reversible 2-to-4 decoder. In the first approach, the reversible 2to-4 decoder has been designed using one FG gate and two Fredkin gates. This design produces 1 garbage output and it requires 11 quantum cost. The second approach uses the proposed HL gate to design the reversible 2-to-4 decoder. This circuit doesn’t produce any garbage output and it requires 7 quantum cost. Fig. 9(a) and (b) shows two different approaches of the design of a reversible 2-to-4 decoder. The performance comparison of the proposed and the existing 2-to-4 decoders [13,17–19] has been shown in Table 3. Table 3 shows that the proposed design (Approach 1) is better than existing designs [13,17,19] in terms of numbers of gates, garbage outputs, delay and quantum cost. Whereas, the existing design [18] works better than the proposed first approach. While comparing the proposed design (Approach 2) with the existing designs [13,17,19], we find that the proposed design (Approach 2) is the best in terms of all parameters of reversible circuit design. 6.4. Reversible 3-to-8 decoder A reversible 3-to-8 decoder can be designed using one 2-to-4 reversible decoder and four Fredkin gates. Two approaches of the proposed design of the 3-to-8 decoder are shown in Fig. 10. The first approach of the proposed decoder produces 2 garbage outputs, whereas the second approach produces 1 garbage output. The performance comparison of the proposed and the existing 3-to-8 decoders [13,17] has been shown in Table 4. The table doesn’t show any comparison with [18] and [19] as they show the design of 2-to-4 decoder only.

Table 3 Comparison of different reversible 2-to-4 decoders. 2-to-4 decoder

No. of gates

Garbage output

Delay

Quantum cost

Proposed approach 1 Proposed approach 2 Existing design [13] Existing design [17] Existing design [18] Existing design [19]

3 1 4 3 1 10

1 0 2 2 0 8

3 1 4 3 1 3

11 7 14 15 8 28

Table 4 Comparison of different reversible 3-to-8 decoders. 3-to-8 decoder

No. of gates

Garbage output

Delay

Quantum cost

Proposed approach 1 Proposed approach 2 Existing design [13] Existing design [17]

7 5 11 7

2 1 6 3

7 4 11 14

31 27 38 32

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Fig. 8. Proposed BJ gate.

Fig. 9. Two approaches of the proposed 2-to-4 reversible decoder.

6.5. Reversible n-to-2n decoder In this section, we construct a generalized reversible n-to2n decoder and prove the complexities of the proposed circuit. A reversible n-to-2n decoder is designed with a (n−1)-to-2(n−1) reversible decoder and 2n−1 Fredkin gates. Fig. 11 shows two approaches of the proposed design of the n-to-2n decoder. Lemma 1. An n-to-2n reversible decoder (Approach 2) can be realized by at least 2n − 3 reversible gates, where n is the number of bits and n ≥ 2. Proof. We prove the above statement by mathematical induction. A 2-to-4 (n = 2) decoder (Approach 1) is constructed using one HL gate. So, a 2-to-4 decoder requires at least 1(=22 –3) reversible gates. So, the statement holds for the base case n = 2.

Assume that, the statement holds for n = k. So, a k-to-2k decoder can be realized by at least 2k − 3 reversible gates. A (k + 1)-to-2(k+1) decoder is constructed using k-to-2k decoder and 2k FRG gates. So, total number of gates required to construct a (k + 1)-to-2(k+1) decoder is at least 2k − 3 + 2k = 2.2k − 3 = 2(k+1) − 3 So, the statement holds for n = k + 1. Therefore, an n-to-2n reversible decoder (Approach 2) can be realized by at least 2n −3 reversible gates. Lemma 2. An n-to-2n reversible decoder (Approach 2) generates at least n − 2 garbage outputs, where n is the number of bits and n ≥ 2. Proof.

We prove the above statement by induction.

A 2-to-4 (n = 2) decoder (Approach 2) requires only one HL gate. All of the outputs of the HL gates are used to design a 2-to-4

Fig. 10. Two approaches of the proposed reversible 3-to-8 decoder.

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Fig. 11. Two approaches of the proposed reversible n-to-2n decoder.

decoder. So, no garbage output is produced by the HL gate (shown in Fig. 11(b)). So, a 2-to-4 decoder generates at least 0(=2–2) garbage output. So, the statement holds for the base case n = 2. Assume that, the statement holds for n = k. So, a k-to-2k decoder generates at least k − 2 garbage outputs. A (k + 1)-to-2(k+1) decoder is constructed using k-to-2k decoder and 2k FRG gates. A k-to-2k decoder generates at least k − 2 garbage outputs and only the last FRG gate produces one garbage output. So, total number of garbage outputs generated by a (k + 1)-to-2(k+1) decoder is at least k − 2 + 1 = (k + 1) − 2 So, the statement holds for n = k + 1. Therefore, an n-to-2n reversible decoder (Approach 2) generates at least n − 2 garbage outputs, where n ≥ 2. 6.6. J-K flip-flop In this section, we design the J-K FF. The proposed BJ gate, shown in Section 6.2, is used to construct a J-K FF. Fig. 12 shows the design of a J-K FF. The comparison of the proposed and the existing J-K FFs [14–16] is shown in Table 4a. From Table 4a, we find that the proposed design outperforms the existing ones in terms of numbers of gates (improvements are 66.66%, 75% and 90% with respect to [14–16], respectively), garbage

outputs (improvements are 66.66%, 66.66% and 91.66% with respect to [14–16], respectively), delay (improvements are 66.66%, 75% and 90% with respect to [14–16], respectively) and quantum cost (improvements are 4.28%, 33.33% and 60% with respect to [14–16], respectively). 6.7. Reversible sequence counter In this section, we design a 4-bit sequence counter which counts from 0 to 15. The sequence counter is designed using four J-K flipflops, that we designed Section 6.6, and four Feynman gates. The J-K FFs change states with the positive clock edge and the counter counts from 0 to 15. This optimized design of sequence counter produces 4 garbage bits (shown in Fig. 13). The performance comparison of the counters using proposed and existing techniques has been shown in the Table 5. From Table 5, we find that the proposed design outperforms the existing ones in terms of numbers of gates (improvements are 53.33%, 63.12% and 83.72% with respect to [14–16], respectively), garbage outputs (improvements are 66.66%, 66.66% and 91.66% with respect to [14–16], respectively), delay (improvements are 53.33%, 63.12% and 83.72% with respect to [14–16], respectively) and quantum cost (improvements are 13.6%, 32% and 58.54% with respect to [14–16], respectively). The sequence counter, that we design, can be expanded for any number of bits. An n-bit sequence counter requires n J-K FFs and n − 1 Feynman gates (total 2n − 1 gates), it produces n garbage outputs and it requires 12n + (n − 1) = 13n − 1 quantum cost.

Table 4a Comparison of different J-K FFs.

Fig. 12. Design of the proposed reversible J-K FF.

J-K FF with Q and Q’

No. of gates

Garbage outputs

Delay

Quantum cost

Proposed method Existing design [14] Existing design [15] Existing design [16]

1 3 4 10

1 3 3 12

1 3 4 10

12 14 18 30

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Fig. 13. Proposed design of 4-bit reversible sequence counter. Table 5 Comparison of Different Reversible Counters. Sequence counter using J-K FF

No. of gates

Garbage outputs

Delay

Quantum cost

Proposed method Design using [14] Design using [15] Design using [16]

7 15 19 43

4 12 12 48

7 15 19 43

51 59 75 123

Table 6 Comparison of different 16-bit reversible instruction registers. Instruction register using J-K FF

No. of gates

Garbage outputs

Delay

Quantum cost

Proposed method Existing design [14] Existing design [15] Existing design [16]

32 64 80 192

17 49 49 208

17 49 65 161

224 256 320 512

6.8. Reversible instruction register D5 T4 : AR ← AR + 1 Instruction register is a high-speed circuit that holds an instruction for decoding and execution. A reversible 16-bit instruction register is designed using sixteen HNFG gates and sixteen J-K FFs (that we designed Section 6.6). The J-K FFs take the inputs through HNFG gates and with the change of the clock pulse they produce the normal and complemented outputs. The instruction register produces 17 garbage bits (shown in Fig. 14). The performance comparison of instruction registers using proposed and existing techniques has been shown in the Table 6. From Table 6, we find that the proposed design outperforms the existing ones in terms of numbers of gates (improvements are 50%, 60% and 83.33% with respect to [14–16], respectively), garbage outputs (improvements are 65.3%, 65.3% and 91.83% with respect to [14–16], respectively), delay (improvements are 65.3%, 73.85% and 89.44% with respect to [14–16], respectively) and quantum cost (improvements are 12.5%, 30% and 56.25% with respect to [14–16], respectively). The instruction register, that we design, can be expanded for any number of bits. An n-bit instruction requires n J-K FFs and n HNFG gates (total 2n gates), it produces n + 1 garbage outputs and it requires 12n + 2n = 14n quantum cost.

where, D5 and D7 are decoder operations and T0 , T2 , T3 and T4 are timing signals [20].

6.9. Control of registers and memory The control inputs of the registers are LD (load), INR (increment) and CLR (clear). Suppose, we want to derive the gate structure associated with the control inputs of address register (AR). The control functions that change the content of AR are as follows: R T0 : AR ← PC R T2 : AR ← IR(0 − 11) D7  IT3 : AR ← M[AR] RT0 : AR ← 0

Fig. 14. Proposed design of 16-bit reversible instruction register.

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Fig. 15. Proposed reversible control gates associated with AR.

The above control functions can be combined into the following Boolean operations: LD (AR) = R T0 + R T2 + D7  IT3 CLR (AR) = RT0 INC (AR) = D5 T4 Here, the first statement specifies transfer of information from a register or memory to AR. The second statement clears AR and the last statement increments AR by 1 [20]. The gate structure associated with the above example is shown in Fig. 15. In a similar fashion we can derive the control gates for the other register as well as the logic needed to control the read and write inputs of memory. 6.10. Construction procedure and complexities of the proposed control unit In Section 4, we show the block diagram of a control unit. The control unit consists of two decoders, a sequence counter, and a number of control logic gates. It fetches the instruction from instruction register. The inputs to the control logic gates come from the two decoders, the I flip-flop and bits 0 through 11 of IR. The outputs of the control logic circuit are: • Signals to control the inputs of the registers • Signals to control the read and write inputs of memory • Signals to set, clear or complement the flip-flops The steps to construct a 16-bit control unit are described in Algorithm 1. Algorithm 1.

Algorithm to Construct a Reversible Control Unit

(1) Construct a 3-to-8 decoder. (2) Take the inputs of the 3-to-8 decoder from the instruction register (bit 12 to bit 15). (3) Construct a 4-bit sequence counter. (4) Construct a 4-to-16 bit decoder. (5) Take the inputs of the 4-to-16 decoder from the outputs of the sequence counter.

(6) Construct a control logic gate. (7) Take the inputs of the control logic gate from the instruction register (bit 0 to bit 11 and bit 15), 3-to-8 decoder (D0 to D7 ) and 4-to-16 decoder (T0 to T15 ). (8) The outputs of the control register provide necessary signals to carry out the operation of the instruction register. Theorem 1. Let gacu be the number of gates required to realize a reversible n-bit control unit (where, n is the number of bits) of a processor, gair be the number of gates required to realize an n-bit instruction register, gad1 be the number of gates required to realize an m-to-2m decoder (where m < n), gasc be the number of gates required to realize a (log2 n)-bit sequence counter, gad2 be the number of gates required to realize a log2 n-to-n decoder and gacl be the number of gates required to realize control logic associated to AR. Then, gacu > = gair + gad1 + gasc + gad2 + gacl = 2log2 n + 2m + 2n − 9. Proof. According to Section 6.8, an n-bit instruction set requires at least 2n reversible gates. So, gair >= n. An n-bit instruction has m-bit opcode (where m < n). An m-to-2m reversible decoder is required to decode the opcode. According to Lemma 1, an m-to-2m decoder requires at least 2m − 3 reversible gates. So, gad1 >= 2m − 3. A (log2 n)-bit reversible sequence counter counts from 0 to n − 1. According to Section 6.7, a (log2 n)-bit sequence counter requires at least 2log2 n − 1 reversible gates. Thus, gasc >= 2log2 n − 1. A log2 nto-n decoder is required to decode the output of the sequence counter. A log2 n-to-n decoder requires at least 2log2 n − 3 = n − 3 reversible gates, so gad2 >= n − 3. The number of gates of the control logic associated to IR depends on the instruction set of a computer. In our case, the number of gates (Fig. 15) for the given instruction set is 13, where, gad2 >= 15. Therefore, the total number of gates for reversible n-bit control unit of a processor is gcu > = gair + gad1 + gasc + gad2 + gacl = n + (2m − 3) + (2log2 n − 1) + (n − 3) + 13 = 2log2 n + 2m + 2n − 9.

Theorem 2. Let gocu be the number of garbage outputs generated by a reversible control unit of a processor, gair be the number of garbage outputs produced by the n-bit instruction register, god1 be the number of garbage outputs for an m-to-2m decoder (where m < n), gosc be the number of garbage outputs for a (log2 n)-bit sequence counter, god1 be the number of garbage outputs produced by a log2 n-to-n decoder and

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gocl be the number of garbage outputs generated by the control logic gates, then gocu >= goir + god1 + gosc + god2 + gocl , = 2log2 n + m + n + 16. Proof. An n-bit instruction register produces at least n + 1 garbage outputs (according to Section 6.8). So, goir >= n + 1. An n-bit instruction has m-bit opcode (where m < n). According to Lemma 2, an m-to-2m reversible decoder generates at least m − 2. So, god1 >= m − 2. According to Section 6.7, a (log2 n)-bit sequence counter generates at least log2 n garbage bits. So, gosc >= log2 n. A log2 n-to-n decoder is required to decode the output of the sequence counter. A log2 n-to-n decoder produces at least log2 n − 2 garbage outputs. Thus, god2 >= log2 n − 2. The number of garbage outputs produced by the control logic associated to IR depends on the instruction set of a computer. In our case, the number of garbage outputs (Fig. 15) for the given instruction set is 19, so god2 >= 19. Therefore, the total number of garbage bits generated by a reversible control unit of a processor is gocu > = goir + god1 + gosc + god2 + gocl, = (n + 1) + (m − 2) + log 2n + (log 2n − 2) + 19 = 2 log 2n + m + n + 16.

7. Conclusions This paper is mainly focused on a novel design of the reversible control unit of a processor. We improved the designs of the reversible decoder, J-K FF, sequence counter and the instruction registers, which are used to realize the reversible control unit. It is also demonstrated that the proposed designs are optimized in terms of numbers of reversible gates, garbage outputs, quantum cost and delay than the existing ones. Moreover, the lower bounds on the number of gates and garbage outputs have been established for the proposed circuit. For example, an n-to-2n reversible decoder requires at least 2n − 3 reversible gates and it produces n − 2 garbage outputs; an n-bit sequence counter requires 2n − 1 gates, it produces n garbage outputs and it requires 13n − 1 quantum cost; an n-bit instruction register requires 2n gates, it produces n + 1 garbage outputs and it requires 14n quantum cost. The individual components of the proposed control unit were verified using VHDL [24] and found the correctness of the function of the proposed circuit. The proposed circuit will be useful for implementing the quantum computers, reconfigurable computer [7,8] etc. References [1] R. Landauer, Irreversibility and heat generation in the computational process, IBM Journal of Research and Development 3 (1961) 183–191.

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