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An efficient critical path tracing algorithm for sequential circuits
Microprocessing and Microprogramming ELSEVIER
Microprocessing and Microprogramming 40 (1994) 913-916
An Efficient Critical Path Tracing Algorithm for Sequential Circuits Hoon Chang ~ and Jacob A. Abraham b Dept. of Software Engineering, SoongSil University, Seoul, Korea b Computer Engg. Research Center, University of Texas at Austin, Austin, TX Several timing verification algorithms for combinational circuits have been proposed in the last few years. However, similar algorithms do not exist for sequential circuits. Existing algorithms have difficulty in performing timing verification even for combinational circuits due to the excessive computation time and memory requirement for identifying the critical path. This paper presents a critical path analysis algorithm for sequential circuits. The algorithm can be used to identify the critical path of a sequential circuit while considering exact operation of the circuit without assuming the use of scan techniques. The input sequence which sensitizes the critical path is determined as well.
1. I N T R O D U C T I O N Even though there are several approaches available for timing verification in combinational circuits [1]-[4], existing algorithms have difficulty in performing timing verification due to the huge computation time and memory requirement. Since such problems in these tools have not yet been suitably handled, the focus on sequential circuit timing verification tools has been considerably less during the past years. To eliminate false paths and identify the critical path of a combinational circuit, several sensitization approaches have been proposed. A static sensitization approach [1] requires strong constraints for side inputs and does not consider the arrival time of side inputs, and so may underestimate the critical path delay. To overcome these problems, a dynamic sensitization approach has been proposed [2]. Since the arrival time of side inputs is roughly estimated using structural information only, this approach may provide an incorrect solution too [5]. One major drawback of both approaches is that they depend on the path list and sensitization checking on a path by path basis. The concept of a viable path which does not depend on the generation of path list has been proposed in [3]. Even though this gives a more accurate estimation of the critical path than former approaches, the computation of viability for the inputs of each gate is very complicated, and
requires excessive computer time for solving the sensitization problem in a large circuit [4]. Conventional timing verification tools can be used to find the critical path in combinational logic block within sequential circuits. However, the current state of memory elements may not be reachable and the true critical path of the circuit may be different from the identified critical path. This problem arises because the conventional approaches do not consider the sequential behavior of circuits, and hence incorrectly identify the critical path of the combinational logic block as the true critical path. Such a critical path, without considering the sequential behavior, may provide a very pessimistic estimation. To overcome these problems and to identify the true critical path, reachability analysis of states should be considered. An efficient sequential circuit timing verification algorithm based on the combinational timing verification tool VIPER [5], is presented here. The circuits are not assumed to be designed with scan flip-flop, and the validity of the states is checked using reachability analysis. 2.
PRELIMINARIES
A path is said to be sensitizable if it can be sensitized by at least one primary input vector and it can propagate a signal. In our work, we define vigorous sensitization criterion as follows [5]. A
0165-6074/94/$07.00 © 1994 - Elsevier Science B.V. All rights reserve~ SSDl 0165-60/4(94)00081-6
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H. Chang, JA. Abraham / Microprocessing and Microprogramming 40 (1994) 913-916
path is a vigorously sensitizable path if each gate along the path satisfies the following sensitization conditions under the given input vector. When input of a gate on the path has non-controlling value, all side inputs have non-controlling value. When input of a gate on the path has controlling value, no side input that arrives earlier than the input on the path has controlling-value. A synchronous sequential circuit consists of a combinational logic block and feedback registers [9]. The combinational logic block is fed by the primary inputs (PI) and by the outputs of Flip/Flops (PPI: pseudo primary outputs), and the outputs of the combinational logic block consist of primary outputs (POs) and the inputs of Flip/Flops (PPOs: pseudo primary outputs). We assume that all F / F s are directly driven by the same clock line with reset state, and no scan technique is assumed. The output and input values of F/Fs define current states and next state of the circuit respectively. The critical path of sequential circuit starts from PIs (PPIs) and ends at POs (PPOs), and the delay of critical path defines the system clock interval. In sequential circuits, two kinds of sensitizable paths can be defined. A sensitizable path of a combinational logic block is called combinationally sensitizable path. The combinationally longest sensitizable path (CLSP) is the critical path of combinational logic block. Since the combinationally sensitizable path is found by considering only the combinational logic block, it is not the true critical path of the sequential circuit. If the values of PPIs, initial state for the given path is a reachable state of circuit, the path is called sequentially sensitizable path. The sequentially longest sensitizable path (SLSP) becomes the critical path of sequential circuit. The conventional approaches identify the combinationally longest sensitizable path only instead of identifying the sequentially longest sensitizable path. In the preprocessing stage, the combinational logic block of circuit is transformed into a graph [5]. The specific delay values associated with the gates and interconnection lines are then assigned to the corresponding components. Two important measures are evaluated to guide the tracing of the critical path. The sink delay for each gate
is the maximum delay of a path from the given gate to POs. The sink delay is used for guiding the extension of the sensitizable path. Each component in the circuit has its own sink delay which will be used as a delay measure when the critical path is traced. The successor gates of each gate are sorted in non-increasing order of their sink delays. This ordering permits the easy selection of the best successor gate whenever the current partial path is extended. Similar to sink delay, the source delay of each gate can be defined for estimating arrival time of side inputs. The source delay for each gate is the maximum delay of a path from PIs to the given gate. 3. S E Q U E N T I A L VERIFICATION
CIRCUIT
TIMING
In most test generation algorithms, the iterative logic array model to handle sequential behavior for synchronous sequential circuits has been used [9]. In generating tests using iterative logic array model for sequential circuits, forward time processing for fault excitation and fault propagation to primary outputs is performed first, and reverse time processing has been applied for state justification [8,9]. In such methods, the propagation of an error signal requires multiple time frames in forward time processing since the error signal should be observed at POs (not PPOs) to verify the existence of fault. However, in our approach, only one time frame is needed to identify the critical path and its associated delay, since the critical path is defined as the longest sensitizable path between PIs (PPIs) and POs (PPOs). In our approach, forward time processing in current time frame is used to find the combinationally longest sensitizable path, and this phase results in an assignment of values to the PIs and PPIs which is necessary to sensitize the path. The vector representing the PPI values in the current time frame, which sensitizes the path, specifies the initial state. After this forward time processing phase, reverse time processing or the state justification phase is triggered by the initial state to see the validity of the initial state. For the identification of combinationally longest sensitizable path, the timing verification
H. Chang, JA. Abraham / Microprocessing and Microprogramming 40 (1994) 913-916
tool VIPER has been used [5]. The critical path tracing is initiated from the input (PI, PPI) which has a maximum sink delay and continued for other inputs according to the order of associated sink delay until the critical path is found. In order to reduce the search space, a threshold delay T is used in our algorithm. Only those inputs which have a sink delay greater than or equal to the threshold delay are included in the tracing of the critical path. We used five logic values which are defined in [5]. These are 0, 1, X, P and N, where P and N are special signals and are placed on the current chosen input. At the start of our algorithm, the logic values of all gates are initialized to X except the chosen input. The signal P is applied to the chosen input, and propagated through the partial path by assigning logic values to the other inputs until signal reaches the outputs (POs, PPOs). When the critical path is not found using P, the signal N is tried. Two measures, sink and source delays which have been evaluated in preprocessing stage, are used in guiding the extension of partial paths [5]. Whenever the current partial path is extended, the successor gate which has a maximum sink delay is tried. If it is not possible to extend the current partial path by assigning a new value for other inputs, backtracking is performed by inverting the most recently assigned input. If it is required that the bottom element of the input stack be changed for backtracking, it implies that there is no sensitizahle path greater than or equal to the threshold delay with the given signal. This is similar to the case of a redundant fault in conventional automatic test generation algorithms [6]. If no more inputs with sink delay greater than or equal to the threshold delay is left, the threshold delay is reduced for future critical-path traces. If P or N arrives at one of the POs (PPOs) during implication process, it indicates that there is a vigorously sensitizable path from the chosen input to this PO (PPO), and the PI and PPI values in the current PI stacks form the patterns which sensitizes this path. To verify that the path is a combinationally longest sensitizable path, the actual propagation delay of the PO (PPO) which indicate the actual propagation time for the sig-
915
nal from the input to the PO (PPO) is compared to the current threshold delay. If the propagation delay is greater than or equal to the threshold delay, it is the combinationally longest sensitizable path of the circuit. After a combinationally longest sensitizable path is found, the current states of memory elements defines the initial state, and reverse time processing is invoked to verify whether the initial state is a reachable state or not. The purpose of the reverse time processing is to generate a justification sequence which results in the initial state. If it is not possible to generate the justification sequence and the initial state is not reachable, critical path tracing using forward time processing is continued again to identify the next combinationally longest sensitizable path. The relative degree of difficulty for computing an input vector or sequence for setting each component to 0 or 1 in sequential circuit is evaluated according to the SCOAP controllability measures [7]. Whenever the state justification is performed in reverse time processing, the PPI values of next time frame become the current objectives. The objectives are sorted and justified according to the degree of controllability measures. In order to prevent a repetition of state justification process, state has been compared to the states achieved already whenever new state has been decided, and backtracking has been performed in the case. If the newly justified state consists of all unknown values or covers reset state, the initial state become a reachable state of the circuit. If the initial state is a reachable one, then the path becomes the sequentially longest sensitizable path. The justified PI values become the patterns which can sensitize the sequentially longest sensitizable path. 4. R E S U L T S
A sequential timing verification tool has been implemented in C on a Sun SPARC workstation. The algorithm has been tested on the ISCAS 89 benchmark circuits. The maximum number of time frames was fixed at 250, and the combinationally sensitizable paths which required more time frames than 250 were aborted. With more
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H. Chang, JA. Abraham / Microprocessing and Microprogramming40 (1994) 913-916
resources of memory and time, more accurate estimation of critical path would be possible. Future research should be focused on the development of efficient heuristics for handling memory and time requirements. Conventional timing verification tools will identify only the combinationally longest sensitizable path as the critical path since they do not consider the sequential behavior of circuits. We observed that there exists differences between the delay of combinationally longest sensitizable path and the delay of the sequentially longest sensitizable path for many cases, and that the combinationally longest sensitizable path is not always sequentially sensitizable. For example, the delay of structurally longest path and the combinationally longest sensitizable path of combinational logic block is 25. However, the delay of the sequentially longest sensitizable path is 23. Also, the delays of combinationally longest sensitizable path and sequentially longest sensitizable path of s400 are 9 and 7 respectively. Thus, if the system clocks of these circuits are defined using the delay of combinationally longest sensitizable path, the design will be overly conservative. For sequential circuits, the system clock should be defined using the sequentially longest sensitizable path identified using teachability analysis to get high performance. Hence our approach will improve system performance. 5. C O N C L U S I O N S Conventional timing verification tools can be used to find the critical path of sequential circuits. However, the current state of memory elements may not he reachable and the true critical path of the circuit may be different from the identified critical path. This problem arises because the conventional approaches do not consider the sequential behavior of circuits, and hence incorrectly identify the critical path of the sequential circuits. To overcome these problems and to identify the true critical path, reachability analysis of states was considered. In this paper, an efficient timing verification algorithm for sequential circuits has been presented. The algorithm does not require genera-
tion of a path list and elimination of false paths to identify the critical path of the circuit. It can identify the critical path of the sequential circuit which is the sequentially longest sensitizable path. The sensitizing input sequence is also determined as a byproduct. REFERENCES
1. Y.C. Ju, and R. A. Saleh, "Incremental Techniques for the Identification of Statically Sensitizable Critical Paths," Proceedings of the
2.
3.
4.
5.
6.
7.
8.
9.
28th ACM/IEEE Design Automation Conference, 1991, pp. 541-546. S. Perremans, L. Claesen, and H. De Man, "Static Timing Analysis of Dynamically Sensitizable Paths," Proceedings of the 26th A CM/IEEE Design Automation Conference, 1989. P.C. McGeer, and R. K. Brayton, "Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network," Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989. L.R. Liu, D. H. C. Du, and H. C. Chen, "An Efficient Parallel Critical Path Algorithm," Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991. H. Chang, and J. A. Abraham, "VIPER: an Efficient Vigorously Sensitizable Path Extractor," Proceedings of the 30th ACM/IEEE Design Automation Conference, 1993. P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, Vol. C-30, No. 3, March, 1981. L. I-I. Goldstein, and E. L. Thigpen, "SCOAP: sandia controllability/observability analysis program," Proceedings of the 17th Design Automation Conference, 1980. A. Ghosh, S. Devadas, and A. R. Newton, "Test Generation for Highly Sequential Circuits," Proceedings of the International Conference on Computer Aided Design, 1989. T. Niermann, and J. H. Patel, "HITEC: A Test Generation Package For Sequential Circuits," Proceedings of European Design Automation Conference, 1991.
Microprocessing and Microprogramming 40 (1994) 913-916
An Efficient Critical Path Tracing Algorithm for Sequential Circuits Hoon Chang ~ and Jacob A. Abraham b Dept. of Software Engineering, SoongSil University, Seoul, Korea b Computer Engg. Research Center, University of Texas at Austin, Austin, TX Several timing verification algorithms for combinational circuits have been proposed in the last few years. However, similar algorithms do not exist for sequential circuits. Existing algorithms have difficulty in performing timing verification even for combinational circuits due to the excessive computation time and memory requirement for identifying the critical path. This paper presents a critical path analysis algorithm for sequential circuits. The algorithm can be used to identify the critical path of a sequential circuit while considering exact operation of the circuit without assuming the use of scan techniques. The input sequence which sensitizes the critical path is determined as well.
1. I N T R O D U C T I O N Even though there are several approaches available for timing verification in combinational circuits [1]-[4], existing algorithms have difficulty in performing timing verification due to the huge computation time and memory requirement. Since such problems in these tools have not yet been suitably handled, the focus on sequential circuit timing verification tools has been considerably less during the past years. To eliminate false paths and identify the critical path of a combinational circuit, several sensitization approaches have been proposed. A static sensitization approach [1] requires strong constraints for side inputs and does not consider the arrival time of side inputs, and so may underestimate the critical path delay. To overcome these problems, a dynamic sensitization approach has been proposed [2]. Since the arrival time of side inputs is roughly estimated using structural information only, this approach may provide an incorrect solution too [5]. One major drawback of both approaches is that they depend on the path list and sensitization checking on a path by path basis. The concept of a viable path which does not depend on the generation of path list has been proposed in [3]. Even though this gives a more accurate estimation of the critical path than former approaches, the computation of viability for the inputs of each gate is very complicated, and
requires excessive computer time for solving the sensitization problem in a large circuit [4]. Conventional timing verification tools can be used to find the critical path in combinational logic block within sequential circuits. However, the current state of memory elements may not be reachable and the true critical path of the circuit may be different from the identified critical path. This problem arises because the conventional approaches do not consider the sequential behavior of circuits, and hence incorrectly identify the critical path of the combinational logic block as the true critical path. Such a critical path, without considering the sequential behavior, may provide a very pessimistic estimation. To overcome these problems and to identify the true critical path, reachability analysis of states should be considered. An efficient sequential circuit timing verification algorithm based on the combinational timing verification tool VIPER [5], is presented here. The circuits are not assumed to be designed with scan flip-flop, and the validity of the states is checked using reachability analysis. 2.
PRELIMINARIES
A path is said to be sensitizable if it can be sensitized by at least one primary input vector and it can propagate a signal. In our work, we define vigorous sensitization criterion as follows [5]. A
0165-6074/94/$07.00 © 1994 - Elsevier Science B.V. All rights reserve~ SSDl 0165-60/4(94)00081-6
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H. Chang, JA. Abraham / Microprocessing and Microprogramming 40 (1994) 913-916
path is a vigorously sensitizable path if each gate along the path satisfies the following sensitization conditions under the given input vector. When input of a gate on the path has non-controlling value, all side inputs have non-controlling value. When input of a gate on the path has controlling value, no side input that arrives earlier than the input on the path has controlling-value. A synchronous sequential circuit consists of a combinational logic block and feedback registers [9]. The combinational logic block is fed by the primary inputs (PI) and by the outputs of Flip/Flops (PPI: pseudo primary outputs), and the outputs of the combinational logic block consist of primary outputs (POs) and the inputs of Flip/Flops (PPOs: pseudo primary outputs). We assume that all F / F s are directly driven by the same clock line with reset state, and no scan technique is assumed. The output and input values of F/Fs define current states and next state of the circuit respectively. The critical path of sequential circuit starts from PIs (PPIs) and ends at POs (PPOs), and the delay of critical path defines the system clock interval. In sequential circuits, two kinds of sensitizable paths can be defined. A sensitizable path of a combinational logic block is called combinationally sensitizable path. The combinationally longest sensitizable path (CLSP) is the critical path of combinational logic block. Since the combinationally sensitizable path is found by considering only the combinational logic block, it is not the true critical path of the sequential circuit. If the values of PPIs, initial state for the given path is a reachable state of circuit, the path is called sequentially sensitizable path. The sequentially longest sensitizable path (SLSP) becomes the critical path of sequential circuit. The conventional approaches identify the combinationally longest sensitizable path only instead of identifying the sequentially longest sensitizable path. In the preprocessing stage, the combinational logic block of circuit is transformed into a graph [5]. The specific delay values associated with the gates and interconnection lines are then assigned to the corresponding components. Two important measures are evaluated to guide the tracing of the critical path. The sink delay for each gate
is the maximum delay of a path from the given gate to POs. The sink delay is used for guiding the extension of the sensitizable path. Each component in the circuit has its own sink delay which will be used as a delay measure when the critical path is traced. The successor gates of each gate are sorted in non-increasing order of their sink delays. This ordering permits the easy selection of the best successor gate whenever the current partial path is extended. Similar to sink delay, the source delay of each gate can be defined for estimating arrival time of side inputs. The source delay for each gate is the maximum delay of a path from PIs to the given gate. 3. S E Q U E N T I A L VERIFICATION
CIRCUIT
TIMING
In most test generation algorithms, the iterative logic array model to handle sequential behavior for synchronous sequential circuits has been used [9]. In generating tests using iterative logic array model for sequential circuits, forward time processing for fault excitation and fault propagation to primary outputs is performed first, and reverse time processing has been applied for state justification [8,9]. In such methods, the propagation of an error signal requires multiple time frames in forward time processing since the error signal should be observed at POs (not PPOs) to verify the existence of fault. However, in our approach, only one time frame is needed to identify the critical path and its associated delay, since the critical path is defined as the longest sensitizable path between PIs (PPIs) and POs (PPOs). In our approach, forward time processing in current time frame is used to find the combinationally longest sensitizable path, and this phase results in an assignment of values to the PIs and PPIs which is necessary to sensitize the path. The vector representing the PPI values in the current time frame, which sensitizes the path, specifies the initial state. After this forward time processing phase, reverse time processing or the state justification phase is triggered by the initial state to see the validity of the initial state. For the identification of combinationally longest sensitizable path, the timing verification
H. Chang, JA. Abraham / Microprocessing and Microprogramming 40 (1994) 913-916
tool VIPER has been used [5]. The critical path tracing is initiated from the input (PI, PPI) which has a maximum sink delay and continued for other inputs according to the order of associated sink delay until the critical path is found. In order to reduce the search space, a threshold delay T is used in our algorithm. Only those inputs which have a sink delay greater than or equal to the threshold delay are included in the tracing of the critical path. We used five logic values which are defined in [5]. These are 0, 1, X, P and N, where P and N are special signals and are placed on the current chosen input. At the start of our algorithm, the logic values of all gates are initialized to X except the chosen input. The signal P is applied to the chosen input, and propagated through the partial path by assigning logic values to the other inputs until signal reaches the outputs (POs, PPOs). When the critical path is not found using P, the signal N is tried. Two measures, sink and source delays which have been evaluated in preprocessing stage, are used in guiding the extension of partial paths [5]. Whenever the current partial path is extended, the successor gate which has a maximum sink delay is tried. If it is not possible to extend the current partial path by assigning a new value for other inputs, backtracking is performed by inverting the most recently assigned input. If it is required that the bottom element of the input stack be changed for backtracking, it implies that there is no sensitizahle path greater than or equal to the threshold delay with the given signal. This is similar to the case of a redundant fault in conventional automatic test generation algorithms [6]. If no more inputs with sink delay greater than or equal to the threshold delay is left, the threshold delay is reduced for future critical-path traces. If P or N arrives at one of the POs (PPOs) during implication process, it indicates that there is a vigorously sensitizable path from the chosen input to this PO (PPO), and the PI and PPI values in the current PI stacks form the patterns which sensitizes this path. To verify that the path is a combinationally longest sensitizable path, the actual propagation delay of the PO (PPO) which indicate the actual propagation time for the sig-
915
nal from the input to the PO (PPO) is compared to the current threshold delay. If the propagation delay is greater than or equal to the threshold delay, it is the combinationally longest sensitizable path of the circuit. After a combinationally longest sensitizable path is found, the current states of memory elements defines the initial state, and reverse time processing is invoked to verify whether the initial state is a reachable state or not. The purpose of the reverse time processing is to generate a justification sequence which results in the initial state. If it is not possible to generate the justification sequence and the initial state is not reachable, critical path tracing using forward time processing is continued again to identify the next combinationally longest sensitizable path. The relative degree of difficulty for computing an input vector or sequence for setting each component to 0 or 1 in sequential circuit is evaluated according to the SCOAP controllability measures [7]. Whenever the state justification is performed in reverse time processing, the PPI values of next time frame become the current objectives. The objectives are sorted and justified according to the degree of controllability measures. In order to prevent a repetition of state justification process, state has been compared to the states achieved already whenever new state has been decided, and backtracking has been performed in the case. If the newly justified state consists of all unknown values or covers reset state, the initial state become a reachable state of the circuit. If the initial state is a reachable one, then the path becomes the sequentially longest sensitizable path. The justified PI values become the patterns which can sensitize the sequentially longest sensitizable path. 4. R E S U L T S
A sequential timing verification tool has been implemented in C on a Sun SPARC workstation. The algorithm has been tested on the ISCAS 89 benchmark circuits. The maximum number of time frames was fixed at 250, and the combinationally sensitizable paths which required more time frames than 250 were aborted. With more
916
H. Chang, JA. Abraham / Microprocessing and Microprogramming40 (1994) 913-916
resources of memory and time, more accurate estimation of critical path would be possible. Future research should be focused on the development of efficient heuristics for handling memory and time requirements. Conventional timing verification tools will identify only the combinationally longest sensitizable path as the critical path since they do not consider the sequential behavior of circuits. We observed that there exists differences between the delay of combinationally longest sensitizable path and the delay of the sequentially longest sensitizable path for many cases, and that the combinationally longest sensitizable path is not always sequentially sensitizable. For example, the delay of structurally longest path and the combinationally longest sensitizable path of combinational logic block is 25. However, the delay of the sequentially longest sensitizable path is 23. Also, the delays of combinationally longest sensitizable path and sequentially longest sensitizable path of s400 are 9 and 7 respectively. Thus, if the system clocks of these circuits are defined using the delay of combinationally longest sensitizable path, the design will be overly conservative. For sequential circuits, the system clock should be defined using the sequentially longest sensitizable path identified using teachability analysis to get high performance. Hence our approach will improve system performance. 5. C O N C L U S I O N S Conventional timing verification tools can be used to find the critical path of sequential circuits. However, the current state of memory elements may not he reachable and the true critical path of the circuit may be different from the identified critical path. This problem arises because the conventional approaches do not consider the sequential behavior of circuits, and hence incorrectly identify the critical path of the sequential circuits. To overcome these problems and to identify the true critical path, reachability analysis of states was considered. In this paper, an efficient timing verification algorithm for sequential circuits has been presented. The algorithm does not require genera-
tion of a path list and elimination of false paths to identify the critical path of the circuit. It can identify the critical path of the sequential circuit which is the sequentially longest sensitizable path. The sensitizing input sequence is also determined as a byproduct. REFERENCES
1. Y.C. Ju, and R. A. Saleh, "Incremental Techniques for the Identification of Statically Sensitizable Critical Paths," Proceedings of the
2.
3.
4.
5.
6.
7.
8.
9.
28th ACM/IEEE Design Automation Conference, 1991, pp. 541-546. S. Perremans, L. Claesen, and H. De Man, "Static Timing Analysis of Dynamically Sensitizable Paths," Proceedings of the 26th A CM/IEEE Design Automation Conference, 1989. P.C. McGeer, and R. K. Brayton, "Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network," Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989. L.R. Liu, D. H. C. Du, and H. C. Chen, "An Efficient Parallel Critical Path Algorithm," Proceedings of the 28th ACM/IEEE Design Automation Conference, 1991. H. Chang, and J. A. Abraham, "VIPER: an Efficient Vigorously Sensitizable Path Extractor," Proceedings of the 30th ACM/IEEE Design Automation Conference, 1993. P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, Vol. C-30, No. 3, March, 1981. L. I-I. Goldstein, and E. L. Thigpen, "SCOAP: sandia controllability/observability analysis program," Proceedings of the 17th Design Automation Conference, 1980. A. Ghosh, S. Devadas, and A. R. Newton, "Test Generation for Highly Sequential Circuits," Proceedings of the International Conference on Computer Aided Design, 1989. T. Niermann, and J. H. Patel, "HITEC: A Test Generation Package For Sequential Circuits," Proceedings of European Design Automation Conference, 1991.