An efficient numerical-based crosstalk avoidance codec design for NoCs

Accepted Manuscript

An Efficient Numerical-Based Crosstalk Avoidance Codec Design for NoCs Zahra Shirmohammadi , Fereshte Mozafari , Seyed-Ghassem Miremadi PII: DOI: Reference:

S0141-9331(17)30032-7 10.1016/j.micpro.2017.01.003 MICPRO 2500

To appear in:

Microprocessors and Microsystems

Received date: Revised date: Accepted date:

5 July 2016 29 December 2016 10 January 2017

Please cite this article as: Zahra Shirmohammadi , Fereshte Mozafari , Seyed-Ghassem Miremadi , An Efficient Numerical-Based Crosstalk Avoidance Codec Design for NoCs, Microprocessors and Microsystems (2017), doi: 10.1016/j.micpro.2017.01.003

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Highlights 

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An efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) is proposed to alleviate crosstalk faults in NoC wires.  It is proved that PS-Fibo generates Triplet Opposite Direction (TOD)-free code words.  An algorithm for mapping data words to FPF code words is proposed using PS-Fibo. Evaluation results indicate that PS-Fibo can improve the overhead s with respect to the state-of-the-art FPF CACs.

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An Efficient Numerical-Based Crosstalk Avoidance Codec Design for NoCs Zahra Shirmohammadia, Fereshte Mozafari b, Seyed-Ghassem Miremadic a

Sharif University of Technology, International Campus, Kish Island, Iran. University of Technology, Department of Computer Engineering, Tehran, Iran.

b,cSharif

ARTICLE INFO

Keywords: Network-on-Chip Reliability Crosstalk Avoidance Code Numerical System

With technology scaling, crosstalk fault has become a serious problem in reliable data transfer through Network on Chip (NoC) channels. The effects of crosstalk fault depend on transition patterns appearing on the wires of NoC channels. Among these patterns, Triplet Opposite Direction (TOD) imposes the worst crosstalk effects. Crosstalk Avoidance Codes (CACs) are the overhead-efficient mechanisms to tackle TODs. The main problem of CACs is their high imposed overheads to NoC routers. To solve this problem, this paper proposes an overheadefficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits the novel numerical system that not only completely removes TODs but also, is applicable to a wide range of NoC channel widths. The PS-Fibo coding mechanism is evaluated using BookSim-2 and VHDL-based simulations in the terms of codec efficiency on the crosstalk fault reduction, codec power consumption, codec area occupation and network performance. Evaluation results, carried out for a wide range of NoC channel widths indicate that PS-Fibo can improve power consumption and area occupations of codec and NoC performance with respect to the other state-of-the-art coding mechanisms.

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Received Received in revised form Accepted Available on wire

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Article history:

ABSTRACT

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 2017 Elsevier Ltd. All rights reserved.

1. Introduction

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Parallel and adjacent wires between Processing Elements (PEs) in Network on Chips (NoCs) [1][2] are seriously prone to coupling capacitances between them [3]. This causes the signal of each wire to mutually affect the transmitted signal of adjacent wires and generate crosstalk faults [3][4]. Crosstalk fault can lead to unwanted voltage glitches and rising/falling delay or/and rising/falling speed up of transitions on the center wire called Victim Wire [3]-[7]. These effects increase due to the advances of fabrication process in Nano-meter regime and may seriously threaten the reliability, power consumption and performance of NoCs [8]. The severity of crosstalk fault effects depends on transition patterns appearing on NoC wires [7][8][9]. In this content, symbols „ ‟, „ ‟ and „-‟ are used to represent transitions (0 → 1), (1 → 0) and no transitions, respectively [9]. Considering this definition, for example, in a 3-wire NoC communication channel, „ ‟ and „ ‟ transition patterns called Triplet Opposite Direction (TOD) impose the worst crosstalk effects whereas, „- ‟, „- ‟, „ -‟, and „ -‟ transition patterns are the weakest transition patterns to cause crosstalk fault. To alleviate crosstalk fault, mechanisms such as wire spacing [10], shielding [11] and repeater insertion [12] at physical level and intentional timing skewing [13] at transistor can be used. However, these mechanisms impose high overheads to NoC-based systems [14]. In recent years, the Register Transfer Level (RTL) mechanisms such as coding have attracted a great deal of interests [13][14].Crosstalk Avoidance Codes (CACs) [8][15]-[20] are among the most efficient types of coding mechanisms. CACs prevent crosstalk fault in the wires of NoCs by preventing the specific transition patterns to occur. According to the impact of CACs on the delay reduction of wires, they are categorized into One Lambda Codes (OLCs) [8][15], Forbidden Transition Codes (FTCs) [16][17][18], Forbidden Pattern Codes (FPFs) [15][19][20] and Forbidden Overlapped Codes (FOCs) [15][18][21]. Among these CACs, FPFs are efficient types that omit TODs and reduce the worst effects of crosstalk faults. Nevertheless, FPFs require additional logic for the encoders and decoders (codecs) to generate code words by applying mapping algorithm on the data words. Although, the state-of-the-art FPF CACs [15][19][20] can omit TODs completely, they suffer from two drawbacks. The first drawback is the ambiguity of mapping algorithm in the proposed FPF CACs in the literature [19]; this ambiguity leads to generating more than one code word for some input data words and impose additional wires to NoC-bases system in order to represent the whole required code words. The second drawback is the overheads of codes in terms of code area occupation, codec power consumption and performance of NoCs. An effective solution to reduce overheads of the codec modules in high width channels is using numerical systems [14]. A numeral system is a mathematical notation for representing data words

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in a consistent manner. Using numerical systems, a coding mechanism can be extended to any arbitrary channel widths of NoCs [14]. In this paper, we propose a novel coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to solve the drawbacks of the state-of-the-art FPF CACs. By applying PS-Fibo coding algorithm, the whole code space is used, and there is not any ambiguity in the representation input data words and there is only one representation for each code word. In other words, PS-Fibo coding algorithm has the best of both worlds' benefits: removing 100% of TODs as well as be extended to any arbitrary channel width of NoCs. To this end, PS-Fibo is evaluated in detailed with respect to state-of-the-art FPF CACs. These evaluations are done by VHDL-based and Booksim-2 [23] simulations for different channel widths. The evaluation results confirm that the proposed coding mechanism improves the reliability of NoC with lower codec overheads compared to other state-of-the-art FPF CACs. The main contributions of this paper are as follows: 1. A numerical system called Penultimate-Subtracted Fibonacci (PS-Fibo) is proposed. Experimental results show that PSFibo outperforms other state-of-the-art FPF CACs with respect to power consumption of codec, area occupation of codec, power consumption of wires and performance of NoC. 2. The mapping algorithm for PS-Fibo coding mechanism is proposed that does not have any ambiguity in generating code words. The rest of this paper is organized as follows: an overview of crosstalk fault and its effects is presented in Section 2. Section 3 reviews the related work, and Section 4 introduces FPF CACs and their properties. In Section 5, the proposed coding mechanism is proposed, and evaluated in Section 6. Finally, conclusion remarks are given in Section 7.

2. Crosstalk Fault in NoCs

T=

[(1 + 2λ)Δ − λΔ (Δ

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During the flit traversal in the communication channels of NoCs, the appearance of specific transition patterns on wires may inadvertently affect signals of the adjacent wires in the channel. This phenomenon, which is referred to as crosstalk fault, is among serious reliability challenges in NoCs. According to Maximum Aggressor Fault (MAF) model [24], all of the wires of communication channels in NoCs affect the center wire called Victim Wire. The main effects of crosstalk fault on the victim wire are: 1) Unwanted voltage glitches including positive and negative glitches, 2) delay in rising/falling transitions, and, 3) speed up in rising/falling transitions [3]-[7]. These effects can degrade performance, power consumption and reliability of NoC-based systems. According to International Technology Roadmap for Semiconductors (ITRS), the delay of wire is increasing in coming years. It is predicted that delay of global wires would 85581 ps in 2026 [25]. According to [27] the delay T of wire l of NoC communication channel (1 < 𝑙 < 𝑘) can be given by (1): )]

(1)

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Where is the delay of ideal channel without crosstalk effect, λ is the ratio of coupling capacitance to bulk capacitance on the wirel and Δ equals to 1 for 0 → 1 (or ), and -1 for 1 → 0 (or ), transitions, respectively. Transition patterns are classified according to their delays into five classes, including 0C, 1C, 2C, 3C, and 4C [26]. These classifications of transition patterns and their delays are shown in Table 1. According to Table 1, the appearances of transition patterns „- ‟, „- ‟, „ -‟, and „ -‟ impose the minimum delay while, transition patterns „ ‟ and „ ‟ Triplet Opposite Direction (TOD) impose the maximum rise/fall delay to the victim wire. With technology scaling, the capacitance between the wires and the ground (𝐶 ) decreases, but the coupling capacitance between adjacent wires (𝐶

) increases. When the latter exceeds the former, the effects of a crosstalk fault on

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wires may be several times more than a single wire [7]. This is mainly due to the electrical parameters of the wires including the length (l ), wire width (𝑤), wire thickness (𝑡), and wire distance from the ground layer (ℎ). Investigations show that with scaling down into nanometer regime, t increases with a lower rate than other spacing factors and this increases the coupling capacitances between wires [7]. With respect to this fact that wires are power hungry and 20%–36% [8] of total NoC power consumption is dissipated in its channels, crosstalk tackling can reduce the power consumption of wires, and thus the whole power consumption of NoC-based system.

3. Related Work

There have been evolving efforts in presenting mechanisms to reduce crosstalk fault in the literature. These mechanisms are proposed at physical level, transistor level, and Register Transfer Level (RTL) of design abstraction. At physical level, specialized routing strategies [28], sizing wire width and spacing [10], adding shielding wires [11], and repeater insertion [12][32] are among the mechanisms that address the delay of crosstalk fault. Reducing the capacitance by shielding each wire is the simplest mechanism that addresses the crosstalk fault. In the active shielding mechanism [32]; shield wires have the same switching behavior as the signal wire, whereas, in passive shielding, the shield wires, which are statically connected to power or ground, are placed on either sides of the signal wire. The area overhead of these mechanisms is their main drawback that makes them not to be desired by manufactures. Increasing the space and width of wires which results in changing the physical dimension of wires are the other mechanisms proposed at physical level to

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reduce the crosstalk fault. In repeater insertion, using inverting or non-inverting buffers in each segment of wires can also reduce the crosstalk fault. However, besides the area redundancy of repeater insertion, timing adjustment and requiring exact placement of repeaters make repeaters not to be favored by NoC designers. At transistor level, eliminating the opposite simultaneous rise and fall transitions by inserting different time shifts in the repeater-inserted channel with the aim of applying intentionally timing skewing can also reduce the crosstalk fault [13]. Timing concerns between the sender and receiver and the area overhead are the main drawbacks of this mechanism. As it was mentioned, the main problem with most of the crosstalk mitigation mechanisms at the physical and the transistor levels is their high overheads, especially the area overhead that they impose on NoC-based systems. At RTL level, using Crosstalk Avoidance Codes (CAC) mechanisms can efficiently reduce the crosstalk fault with much lower area overhead than abovementioned mechanisms. Low power consumption and technology-independence are among the main features that have made CACs attractive and popular for designers in recent years. In order to practically applying CACs, efficient codec designs are necessary. CAC's encoder and decoder (codec) impose overheads to the routers of NoCs. Channel partitioning [22] and using numerical systems [14] are two proposed mechanisms to reduce the overhead of codec. The basic idea behind channel partitioning is to divide the wires of channel into some groups and encode each of them separately with the aim of reducing overheads. This improves the performance and overheads of codecs by using small size codecs in each group [14]. The “group complement” [14] and “bit overlapping” [14] are two mechanisms based on the idea of channel partitioning. However, the problem arises with merging all the groups into a single channel; the reason is the transition patterns of classes that can occur between adjacent channels. The other mechanism for codec design is the use of numerical systems [14]. A numeral system is a mathematical notation for representing data words in a consistent manner. Each numerical system is composed of vector of bases that each base is considered as a weight for binary representing the code words. Based on transition classes that are omitted by CACs, different numerical-based CACs are proposed. According to the impact on reducing the delay of wires, CACs can be categorized into One Lambda Codes (OLCs) [8][15], Forbidden Transition Codes (FTCs) [16][17][18], Forbidden Pattern Codes (FPFs) [15][19][20] and Forbidden Overlapped Codes (FOCs) [15][18][21]. Since the aim of this paper is to omit TODs, FPFs are discussed further in the next section.

4. Forbidden Pattern Free CACs

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Triplet Opposite Direction (TOD) transitions impose the worst crosstalk effects on NoC-based systems. This is due to the appearance of „010‟ and „101‟ transition patterns during the flit traversal on wires . One efficient mechanism that reduces crosstalk faults is the omission of TODs in generated code words. This is done in generating type of memoryless CACs called Forbidden Pattern Free (FPF) codes. Avoiding TODs in FPF CACs reduce the delay of 4C to 2C [14]. One cost-efficient mechanism to generate FPFs is to use numerical systems. A numeral system is consisting of notation for representing data word in the form of FPFs code word . Each numerical system is composed of vector of bases of that each base for 1 ≤ ≤ 𝑘 is considered as a weight for binary representing the code words so that =∑ . It is shown in [19] that the maximum code space size called cardinality in FPF numerical system

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is 2 𝐹 where 𝑘 is NoC channel width, and 𝐹 is the (𝑘 + 1)′th sentence of Fibonacci sequence. In other words, with k wires, the FPF coding mechanism can have 2 𝐹 representations. For example in 6 bit NoC communication channel, there are 2 𝐹7 = 2 13 = 26 code words. Numerical system with the following properties can generate FPF code words [14]: Complete: the numerical system is complete if any data word has at least one representation using the numerical system. In other words, for if =1, for all amounts of we have ≤ 1 + ∑ where is used as the base in the numerical

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system. Generating FPF code words: the numerical system should be able to encode data words to FPF code words. In order to use numerical-based FPFs practically, efficient codec designs including encoder and decoder are necessary. In wide channels, numerical systems can efficiently overcome the complexity of FPFs [15] in terms of power consumption, area overhead and performance of codec. There have been proposed Fibonacci-based [19] and non-Fibonacci-based [15][20] numerical systems to generate FPF CACs in the literature. One of the Fibonacci-based numerical systems is Fibonacci numerical system (referred as Fibo-CAC hereafter) [19]. Fibo-CAC uses Fibonacci sequences as the bases to generate FPF codes, e. g. for 6 bit space, and the bases are: 1 1 2 3 5 8. Fibo-CAC uses the iterative algorithm to replace the „011‟ by „100‟ and vice versa. However, Fibo-CAC has ambiguity in generating code words; this means that for some input data words, more than one code word representations is generated by Fibo-CAC. Table 2 shows 6 bit codebooks generated by Fibo-CAC [19]. As shown in this table, Fibo-CAC generates two code words presentations for data words 9-12. This ambiguity wastes the coding space and requires additional wires to show all the data words. The other Fibonacci-based numerical system that is proposed recently is an improved Fibonacci coding mechanism (referred as Improved-Fibo-CAC hereafter) [15]. Improved-Fibo-CAC uses the same bases of Fibonacci sequence but the only difference is in the penultimate bit position of bases that is duplicated in comparison with Fibo-CAC numerical system. For example in 6 bit space, the bases used in Improved Fibo-CAC are 1 1 2 3 5 13 and the code word with the value of 12 is coded by the Improved-Fibo-CAC numerical system to 1 1 1 1 1 0. Table 2 also shows the 6 bit

ACCEPTED MANUSCRIPT code words generated by Improved-Fibo-CAC numerical system. As it is shown in this table, Improved-Fibo-CAC unlike Fibo-CAC has not ambiguity in representing code words. Summation-based-Subtracted-Added-Penultimate (S2AP) is the other numerical-based CAC that uses non-Fibonacci based numerical systems to generate FPF CACs [15][20]. For example in 6 bit space, the bases used in Improved-Fibo-CAC are 2 2 4 7 9 1 and the code word with the value of 12 is coded to 1 0 0 0 1 1. Although, Improved-Fibo-CAC and S2AP has not ambiguity in generating code words, they impose overheads in the terms of power consumption, area overhead and performance to NoC-based system. Table 2 shows the 6 bit code words generated by S2AP numerical system. To generate overhead-efficient code words using numerical system‟s bases, the mapping algorithm is required. The mapping algorithm has direct effects on the codec overheads including power consumption, area overhead and performance. In this paper, we propose Fibonacci-based numerical system that not only has no ambiguity in generating code words, but also has fewer amounts of codec overheads in the terms of power consumption, area overhead and performance of codec, in comparison to the other state of the art Fibonacci-based and non-Fibonacci-based numerical-based FPFs.

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5. Proposed Numerical Systems

In this section, the proposed numerical system, the mapping algorithm and the implementation of hardware architecture of the proposed codec are explained in more details.

5.1 PS-Fibo Coding Mechanism

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As the overhead of codec modules including power consumption, area occupations and performance of NoC depends on the numerical system, using an efficient numerical system plays an important role in designing proper codec for FPFs. To meet this aim, a novel FPF coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) is proposed in this paper. This numerical system, unlike Fibo-CAC, does not have any ambiguity and uses all of the code space capacity and meets the maximum FPF cardinality. PS-Fibo can be applied to any arbitrary channel width of NoCs. Considering that (𝑘) denotes the numerical system with the bases of: (𝑘) =

− 𝐹

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𝐹 𝐹 ={ 𝐹 𝐹

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Where, in (2) 𝑘 is the NoC channel width. PS-Fibo uses numerical system with the base of as (3):

(2)

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In (3), is the i'th base of numerical system, and 𝐹 is k'th sentence of Fibonacci sequence. According to this definition, PS-Fibo uses (k-1)'th sentence of Fibonacci sequence as a penultimate and also MSB base of numerical system. Also, PS-Fibo subtracts the (k-3)'th sequence of Fibonacci sequence from the (k+1)'th of Fibonacci sequence and uses it as (k-2)'th base of numerical system. For example, in 6 bit space, the PS-Fibo uses 5 5 11 2 1 1 numerical system and maps 12 data word to 110011 code word. Table 3 shows all of the 6 bit FPF code words using PS-Fibo numerical system. PS-Fibo can be applied for any arbitrary channel widths of NoC. Also, PS-Fibo coding mechanism meets the maximum cardinality of FPF codes. As Table 3 states, unlike the Fibo-CAC coding mechanism, PS-Fibo coding mechanism does not have ambiguity, and there is unique code word representation for each of data words. This causes PS-Fibo coding mechanism to be optimized with respect to Fibo-CAC in the number of represented code words and meeting the maximum cardinality of FPF codes. One of the main features of PS-Fibo coding mechanism is that, it is optimized with respect to Fibo-CAC coding mechanism in the number of represented code words. In Fibo-CAC coding mechanism, data words in the range of 𝐹 − 1 can be represented [19]. In PS-Fibo, the ability of coding representations is increased to the 2𝐹 − 1 . In other words, as there is not ambiguity in code words, PS-Fibo coding mechanism can represent 2𝐹 −𝐹 =𝐹 more code words than Fibo-CAC coding mechanism and thus can use the whole FPF coding space [19]. Table 3 shows that for all of the 26 data words that use the PS-Fibo numerical system, there exists code words, while Fibo-CAC coding mechanism due to its ambiguity, wastes the code space and does not have any representations for 21-25 data words. In the rest of this section, it is proved that PS-Fibo coding mechanism meets the required condition to be used as FPF coding. As mentioned in the previous section, FPF numerical system should be complete. As PS-Fibo numerical system satisfies ≤ 1 + ∑ , it is complete. Also, PS-Fibo coding mechanism has the following features: Feature1: under the PS-Fibo numerical system, 1 1 vectors are equal. Proof: according to definition in (3) = and it is clear that the two most significant bases are interchangeable.

ACCEPTED MANUSCRIPT Feature 2: in k-bit vector in PS-Fibo numerical system, if three tandem bits have „100‟ values, this pattern can be replaced by „110‟ without changing the value. Proof: this Feature can simply be obtained from the definition of PS-Fibo numerical system in (3). Feature 3: in k-bit vector using PS-Fibo numerical system, all bit patterns, except the first two bits, i.e.; „0010‟,...‟1010‟ can be replaced by patterns „1111‟… „1100‟. Proof: replacing „110‟ with „001‟ from left to right recursively, the Feature 3 is proved. Feature 4: in k-bit vectors using PS-Fibo numerical system, all bit patterns, except first two bits, i.e.; „1101‟...‟0101‟ can be replaced by patterns „0000‟, …, „0011‟, „0011‟. Proof: replacing „110‟ with „001‟ from left to right recursively, the Feature 4 is proved. As PS-Fibo numerical system is complete, it can be argued that for each data word , 2𝐹 − 1 there exists at least one FPF code word in PS-Fibo coding mechanism.

5.2 Mapping Algorithm and Hardware Architecture of PS-Fibo Coding Mechanism

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The PS-Fibo coding mechanism uses an iterative algorithm to map input data word , to an equivalent FPF code word . In this way, the PS-Fibo codec can simply be extended for any width of NoC channel. In this algorithm, FPF code words are generated after 𝑘 iterations, where 𝑘 is the width of NoC channel. The mapping algorithm of PS-Fibo is shown in Fig. 1. In each stage of the algorithm, and values are determined, where is the ′th bit of the FPF code word, and is the remainder of the input value to the next stage. In the mapping algorithm of PS-Fibo, calculation of the LSB, 𝑘 − 2,𝑘 − 1 and MSB bits of the code word are different from other bits of the PS-Fibo code word. Fig. 2 shows the hardware architecture of the PS-Fibo encoder and decoder for 𝑘-bit channel. As can be seen, according to the PS-Fibo coding mechanism, the value of ′th bit in the FPF binary code word i.e., , as well as the remainder of the ′th stage i. e., is calculated by the proposed architecture. Each processing module includes subtractor, comparator, and multiplexer modules. Subtractor calculates the remainders which are used in the next stages while comparator and multiplexer modules together implement the if-then-else commands in the algorithm. Since and have different calculation rules, in the proposed architecture, the first and the last three stages have different hardware architectures while other stages have the same architectures. Hardware architecture modules of processing modules used in the encoder of the PS-Fibo coding mechanism are shown in Fig. 3. Module (A) calculates and , module (B) calculates and , and module (C) is repeated for rest of encoder to calculate and , for ′th stage. To decode FPF code words , the PS-Fibo decoder calculates = ∑ where is defined according to the PS-Fibo numeral system for a k-bit channel. According to this algorithm, the 6 bit FPF code word 011100 coded by the PS-Fibo coding mechanism means 0×5+1×5+1×11+1×2+0×1+0×1=18

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6. Experimental Results

In this section, the impact of inserting the codec of PS-Fibo into the architecture of NoC is evaluated. To meet this aim, exhaustive simulations are carried out in the terms of efficiency of PS-Fibo coding mechanism on the crosstalk fault reduction; wires power consumption, codec power consumption, codec area occupation and performance of NoCs. In this

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regard, first the environment and evaluation mechanisms are introduced and then the experimental results are presented.

6.1 Simulation Environment

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The efficiency of PS-Fibo coding mechanism on the crosstalk fault reduction is evaluated on different video benchmarks. In order to verify compliance with reality, H. 264 codec [29] is used to generate video benchmarks. In order to evaluate the PS-Fibo coding mechanism in terms of codec overheads including power consumption and area occupation, codec of the PSFibo is implemented using VHDL-based simulations. Then, the codec blocks are synthesized by the Design Compiler tool in TSMC 45 nm technology. For the power consumption of wires, SPICE simulations are carried out to study the effect of the PS-Fibo on power consumption of wires. To study the effect of the PS-Fibo coding mechanism on the performance of the NoC, we evaluated the average packet latency of NoC in the present of PS-Fibo coding mechanism using BookSim-2, a simulator for interconnection networks. The network is composed of 64 PEs arranged as 8×8 mesh. Network uses dimension order X-Y routing algorithm and the wormhole switching mechanism in 128 flit widths of NoC channel. Also, in our simulations, injection and ejection channels have 2 and 4 virtual channels per physical channel. To have fair comparisons, the same experiments are carried out for Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms.

6.2 Efficiency of the PS-Fibo Coding Mechanism on the Crosstalk Fault Reduction To evaluate the efficiency of PS-Fibo coding mechanism on the crosstalk fault reduction, simulations are carried out by applying PS-Fibo on the video bit stream benchmarks. Using the JM 15.1 simulator [29] three standard video bit stream benchmarks including: Football, Mobile, and Foreman are generated using the H. 264 codec to obtain realistic traffic patterns. These video bit streams are tested for different flit widths, varying from 32 to128. The parameters for these three standard video bit stream benchmarks are shown in Table 4. The results are extracted and reported in Table 5 for 32, 64,

ACCEPTED MANUSCRIPT and 128 channel widths using Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms. The percentage reduction of 4C, 3C, 2C, and 1C transition patterns with respect to the NoC channel without using any coding mechanism are included in the reported results. As mentioned in Section 4, we expect that PS-Fibo omits all of the 4C transitions, so that the results meet our expectations. Fibo-CAC, Improved-Fibo-CAC and S2AP have 100% reduction not only in 4C but also in 3C. However, in 2C, PS-Fibo coding mechanism outperforms Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms.

6.3 Power Consumption Analysis

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For power consumption analysis in the presence of PS-Fibo coding mechanism, power consumption of codec and power consumption of wires are estimated. To have fair comparisons, the same experiments are carried out for Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms. Dynamic power consumption and leakage power consumption of codecs of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms in different flit widths are reported in Fig. 4 and Fig. 5, respectively. Also, amounts of dynamic power consumption and leakage power consumption of codecs of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms are shown in Table 6 and Table 7, respectively. As it is shown in these tables, due to the efficiency of mapping algorithm of PS-Fibo coding mechanism, dynamic power consumption and leakage power consumption of PS-Fibo codec outperform Fibo-CAC, Improved-Fibo-CAC and S2AP codecs. Besides the codec, total capacitances of the wires between PEs have a decisive role in power consumption of NoCs. As PS-Fibo coding mechanism omits TODs completely, it can efficiently reduce coupling capacitance and the load capacitance of wires. To examine the effect of PS-Fibo coding mechanism on a power consumption of given wire geometry; the power consumption of wires in the presence of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms for different wire length is examined using SPICE simulations. As it was mentioned previously, the FPFs impose redundant wires. For fair comparison, these redundant wires should also be taken into considering in calculations of wires power consumption. In these simulations, power consumption of NoC channel without using any coding mechanism has been extracted and compared with that of a PS-Fibo-enabled and Fibo-CAC-enabled, Improved-Fibo-CAC-enabled and S2AP-enabled NoC channel. Predictive Interconnect Model (PIM) [30] is used to model the wires of between PEs. In this model, each wire of the channel includes capacitance of 𝐶 , resistance of , and inductance of Also, 𝐶 and are considered to model the coupling capacitanceand coupling inductance between adjacent wires

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wires , , and . The results of power consumption of wires using different benchmarks and wire lengths in 45 nm technology size are reported in Fig. 6 and Table 8. These results confirm that by applying the PS-Fibo coding mechanism, power consumption of wires is reduced. The power consumption of wires is improved with respect to NoC without using any coding mechanism even with adding redundant wires.

6.4 Area Overhead

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For the sake of fair comparisons, as PS-Fibo coding mechanism adds codec modules to NoC routers; the extra area occupations that the codec blocks add to the NoC router is estimated. To meet this aim, we used VHDL-based simulations and synthesized the codec of PF-Fibo. Percentage of area occupation improvement of PS-Fibo with respect to Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms is reported in Fig. 7. Also, amounts of area occupation of codec in different flit widths are reported in Table 9. Comparisons show that PS-Fibo coding mechanism has less area occupation overhead compared to Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms. Router implementations of a speculative router presented in [31] using VHDL and a comparison of the overhead of codec show that in 128, 64 and 32 flit widths, codecs occupy up to 19%, 9% and 3% of the overall router area, respectively.

6.5 Average Packet Latency

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To estimate the average packet latency of NoC in the presence of proposed coding mechanism, the codec of PS-Fibo is implemented in BookSim-2 simulator. Adding the PS-Fibo coding mechanism, encoder and decoder blocks of this coding mechanism is added to the routers of NoCs. The encoder and decoder of Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanism are also implemented in BookSim-2 simulator. Fig. 8 shows the average packet latency in 128 channel widths with 4 virtual channels and also Fig. 9 shows the average packet latency in 128 channel widths with 2 virtual channels. The results of average packet latency are reported in the NoC without using any coding mechanism and also by applying PSFibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms. Our results show that PS-Fibo coding mechanism outperforms Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms in the terms of the average packet latency.

7. Conclusion Crosstalk faults in the wires of NoC channels can seriously threaten the reliability of data transfer. The severity of crosstalk faults in NoC wires depends on the tandem transitions appearing on the wires of NoC channel. Among these transitions, TODs impose the worst crosstalk effects on the wires of NoCs. FPF codes can reduce the worst crosstalk effects by omitting TODs. To apply FPF coding mechanisms, numerical systems are among the overhead-efficient mechanisms. The algorithm of numerical system plays an important role in the imposed overhead of codec to NoC routers. This paper presents

ACCEPTED MANUSCRIPT an overhead-efficient FPF coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo). Also, the mapping algorithm for PS-Fibo coding mechanism is proposed that does not have any ambiguity in generating code words. PS-Fibo coding mechanism is inspected in more details from crosstalk efficiency, wire power consumption, codec overheads and NoC performance perspectives. The experimental results indicate that PS-Fibo improves power consumption, area occupation and NoC performance with respect to state-of-the-art FPF CACs including Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms.

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[11] J. Zhang, G. E. Friedman, Effect of shield insertion on reducing crosstalk noise between coupled interconnects. in: Proceedings of the ISCAS Conference, May 2004, pp 529–532.

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[12] H. Kaul, J. S. Seo, M. Anders, D. Sylvester, R. Krishnamurthy, A robust alternate repeater technique for high performance busses in the multi-core era, in: Proceedings of the ISCAS Conference, May 2008, pp. 372–375. [13] K. Nose, T. Sakurai, Two schemes to reduce interconnect delay in bi-directional and uni-directional buses. In: Proceedings of VLSI Symposium, 2001, pp. 193–194

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[14] C. Duan, B. J. LaMeres, S. P. Khatri, On and off-chip crosstalk avoidance in VLSI design, Springer Publishing, 2010. [15] X. Wu, Z. Yan, Efficient CODEC designs for crosstalk avoidance codes based on numeral systems, IEEE Trans. Very Large Scale Integ. (VLSI) 19 (April(4)) (2011) 548–558.

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[16] C. Duan, A. Tirumala, S. P. Khatri, Analysis and avoidance of crosstalk in on-chip buses, in: Proceedings of the Hot Interconnects Conferense, August 2001, pp. 133–138. [17] B. Victor, K. Keutzer, Bus encoding to prevent crosstalk delay, in: Proceedings of the Computer Aided Design (ICCAD), November 2001, pp. 4–8 [18] C. S. Chang, J. Cheng, T. K. Huang, D. S. Lee, Constructions of memoryless crosstalk avoidance codes via-C transform, IEEE Trans. Very Large Scale Integ. (VLSI) 22 (September(9)) (2014) 2030–2033. [19] C. Duan, V. H. C. Calle, S. P. Khatri, Efficient on-chip crosstalk avoidance codec design, IEEE Trans. Very Large Scale Integ. (VLSI) 17 (February(4)) (2009) 551–560. [20] Z. Shirmohammadi, S. G. Miremadi, On designing an efficient numerical-based forbidden pattern free crosstalk avoidance codec for reliable data transfer of NoCs, Micro. Reliability Jour. 63 (August) (2016) 304–313.

ACCEPTED MANUSCRIPT [21] C. S. Chang, J. Cheng, T. K. Huang, D. S. Lee, Coding rate analysis of forbidden overlap codes in high speed buses, ACM Trans. 1 (June(2)) (2016), 8:2–24. [22] B. Halak, Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation, Jour. IET Comput. & Digital Tech. 8 (March(2)) (2014) 97–107. [23] BookSim-2: A Cycle-Accurate bin/trac.cgi/wiki/Resources/BookSim

Interconnection

Network

simulator:

http://nocs.stanford.edu/cgi-

[24] X. Bai, S. Dey, High-level crosstalk defect simulation for system-on-chip interconnects, in: Proceedings of Test Symp. (VTS), April 2001, pp. 169–175. [25] International Technology Roadmap for Semiconductors (ITRS), Technical Report, 2012, [Online] Available: http://public.itrs.net

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[26] P. P. Sotiriadis, A. P. Chandrakasan, A bus energy model for deep submicron technology, IEEE Trans. Very Large Scale Integ. (VLSI) 10 (June (3)) (2002) 341–350. [27] P. P. Sotiriadis, Interconnect modeling and optimization in deep submicron technologies, Ph.D. Dissertation, Massachusetts Institute of Technology, 2002. [28] T. Gao, C. L. Liu, Minimum crosstalk channel routing, in: Proceedings of the ICCAD Conference, November 1999, pp. 692–696. [29] H264/AVC JM Refrence, [Online] Avalable: http://iphome.hhi.de/suehring/tml/.

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[30] Predictive Technology Model, Arizona State Univ., [Online] Available: http://ptm.asu.edu/.

[31] W. J. Dally, B. Towles, Principles and practices of interconnection networks, Book. Morgan Kaufmann Publishers, San Francisco, CA, USA, 2004.

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[32] C. J. Akl, M. A. Bayoumi, Reducing interconnect delay uncertainty via hybrid polarity repeater Insertion, IEEE Trans. VLSI 16 (September (9)) (2008) 1230–1239.

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Zahra Shirmohammadi received M.Sc. degree in information technology from International branch, Sharif University of Technology in 2011 where she is currently pursuing the Ph.D. degree with the Department of Computer Engineering. Her current research interests include dependability of System-on-Chip (SoC) and Network-on-Chip (NoC) design and highperformance computer architecture.

Fereshte Mozafari received B.Sc. and M.Sc. degrees in Computer Engineering both from Sharif University of Technology in 2013 and 2015, respectively. Her current research interests include System-on-Chip (SoC), Storage System Design, Network-on-Chip (NoC) and High-Performance Computer Architecture.

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Seyed Ghassem Miremadi is a Professor of Computer Engineering at Sharif University of Technology. As fault-tolerant computing is his specialty, he initiated the "Dependable Systems Laboratory" at Sharif University in 1996 and has chaired the Laboratory since then. The research laboratory has participated in several research projects which have led to several scientific articles and conference papers. Dr. Miremadi and his group have done research in Physical, SimulationBased and Software-Implemented Fault Injection, Dependability Evaluation Using HDL Models, Fault-Tolerant Embedded Systems, Fault-Tolerant NoCs, Fault-Tolerant Real-Time Systems, and Fault-Tolerant Storage Systems. He was the Education Director (1997-1998), the Head (19982002), the Research Director (2002-2006), and the Director of the Hardware Group (2009-2010) of Computer Engineering Department at Sharif University. During 2003 to 2010, he was the Director of the Information Technology Program at Sharif International Campus in Kish Island. From 2010 to 2012, Dr. Miremadi was the Vice-President of Academic Affairs (VPAA) of Sharif University. Since 2014, he is VPAA of Sharif University. He served as the general co-chair of the 13th Int'l CSI Computer Conference (CSICC 2008), the executive chair of the 2013 Int'l Conference on Engineering Education, and the general co-chair of the 2015 Int'l CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST 2015). He is currently the Editor of the Scientia Transactions on Computer Science and Engineering. Dr. Miremadi got his M.Sc. in Applied Physics and Electrical Engineering from Linköping Institute of Technology and his Ph.D. in Computer Engineering from Chalmers University of Technology, Sweden. He is a senior member of the IEEE Computer Society and IEEE Reliability Society.

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Output: 𝑑𝑘 𝑑𝑘

𝑑 =𝑟 ; 𝑑

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Fig. 1. PS-Fibo Mapping Algorithm

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\\LSB Stage

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Input: code length, data word v \\k-2 Stage if 𝑣 ≥ 𝐹𝑘 then 𝑑𝑘 = 1; else 𝑑𝑘 = ; 𝑟𝑘 = 𝑣 − (𝐹𝑘 − 𝐹𝑘 )𝑑𝑘 end if \\k-1 Stage if 𝑟𝑘 > 𝐹𝑘 then 𝑑𝑘 = 1; if 𝑟𝑘 < 𝐹𝑘 𝑑𝑘 = ; else if 𝑟𝑘 ≥ 𝐹𝑘 𝑑𝑘 = 𝑑𝑘 ; 𝑟𝑘 = 𝑟𝑘 − 𝐹𝑘 𝑑𝑘 ; end if \\ MSB Stage if 𝑟𝑘 ≥ 𝐹𝑘 𝑑𝑘 = 1; else 𝑑𝑘 = ; 𝑟𝑘 = 𝑟𝑘 − 𝐹𝑘 𝑑𝑘 ; end if \\ Other Stages for n=k-3 to 2 do if ≥ 𝐹𝑛 𝑑𝑛 = 1; else if < 𝐹𝑛 𝑑𝑛 = ; else 𝑑𝑛 = 𝑑𝑛 ; 𝑟𝑛 = 𝑟𝑛 − 𝐹𝑛 𝑑𝑛 ; end if end for

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Fig. 2. The Architecture of PS-Fibo A) Encoder and B) Decoder used in a k-bit Channel

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Fig. 3. Hardware architecture of processing modules used in the encoder of the PS -Fibo coding mechanism. Module (A) calculates 𝑑 and 𝑟 , module (B) calculates 𝑑 and 𝑟 , and module (C) is repeated for the rest of encoder to calculate 𝑑𝑖 and 𝑟𝑖 , for th stage.

Fig. 4. Dynamic power consumption of PS-Fibo codec with respect to Fibo-CAC, Improved-Fibo-CAC and S2AP Codecs

Fig. 5. Leakage power consumption of PS-Fibo codec with respect to Fibo-CAC, Improved-Fibo-CAC and S2AP Codecs

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Fig. 6. Power consumption of wires in the present of PS-Fibo coding mechanism with respect to Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms

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Fig. 7. Percentage of area occupation improvement of PS-Fibo with respect to Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms

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ACCEPTED MANUSCRIPT Table 1 Transition class‟s patterns and delays [26] Transition Class

Patterns

Delay

𝜋 (1 + 𝜆)𝜋 (1 + 2𝜆)𝜋 (1 + 3𝜆)𝜋 (1 + 4𝜆)𝜋

0C 1C

-

-

2C

- -

3C

-

-

- -

-

-

Table 2 6 bit code words generated by Fibo-CAC [19], Improved-Fibo-CAC [15] and S2AP [20] Numerical System

Numerical System

Improved-Fibo-CAC 𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

112358 Code Word

1 1 2 3 5 13 Code Word

2 2 4 7 9 1 Code Word

0 1 2 3 4 5

000000 100000 110000 011000 111000 001100

000000 100000 110000 011000 111000 001100

0 0 1 1 1 1

6 7

011100 111100 000110 000001 100110 100001 110001 001110 011110 011001 111110 111001

011100 111100

0 1100 0 1 1000 1

000110

10 11 12

Fibo-CAC

Improved-Fibo-CAC 𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

112358 Code Word

1 1 2 3 5 13 Code Word

2 2 4 7 9 1 Code Word

13 14 15 16 17 18

000011 100011 110011 000111 100111 001111

000000 100001 110001 011001 111001 000011

01 11 11 00 00 10

19 20

011111 111111

100011 110011

10 0 1 1 1 00 1 1 1 0

1 1100 0

21

-------

000111

00 1 1 1 1

100110

1 1100 1

22

-------

100111

01 1 1 1 0

011100

0 0001 1

23

-------

001111

01 1 1 1 1

0 0110 0

24

-------

011111

1 1 1 1 1 0

1 0001 1

25

-------

111111

1 1 1 1 1 1

011110 111110

𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

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0000 0000 0000 0000 1000 1000

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Data Word

Fibo-CAC

𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇

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Table 3 6 bit FPF code words generated by PS-Fibo coding mechanism Numerical System PS-Fibo Data word 𝜇6 𝜇5 𝜇 𝜇 𝜇 𝜇 5 5 11 2 1 1 Code Word 0 0 0 0 0 0 0 1 0 0 0 0 0 1 2 0 0 0 0 1 1 3 0 0 0 1 1 0 4 0 0 0 1 1 1 5 0 0 0 0 0 1 6 1 0 0 0 0 1 7 1 0 0 0 1 1 8 1 0 0 1 1 0 9 1 0 0 1 1 1 10 1 1 0 0 0 0 11 1 1 0 0 0 1 12 1 1 0 0 1 1

Data word

13 14 15 16 17 18 19 20 21 22 23 24 25

Numerical System PS-Fibo 𝜇6 𝜇 5 𝜇 𝜇 𝜇 𝜇 5 5 11 2 1 1 Code Word 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1

S2AP

1 0 1 0 0 0

1 0 1 1 1 1

0 1 0 1 1 1

0 1 0 0 1 1

ACCEPTED MANUSCRIPT Table 4 Parameters of tested video bit streams benchmarks [29] Video benchmark Football Mobile Foreman

Format CIF 328×228 SIF 352×240 SIF 352×240

Bus width 32,64,128 32,64,128 32,64,128

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Table 5 Reduction percentage of different crosstalk-induced transition patterns with respect to different coding mechanisms Streams Football Mobile Foreman Channel ImprovedImprovedImproved Width Coding PS-Fibo S2AP Fibo-CAC PS-Fibo S2AP Fibo-CAC PS-Fibo S2AP Fibo-CAC Fibo-CAC Fibo-CAC Fibo-CAC 1C -27 -3 -35 -25 -43 2 -56 -46 -18 3 -32 -3 2C 90 64 89 70 87 52 89 60 58 58 30 33 128 Bits 3C 100 100 100 100 100 100 100 100 100 100 100 100 4C 100 100 100 100 100 100 100 100 100 100 100 100 1C -34 -2 -44 -40 -26 -2 -33 -30 32 6 -30 -12 2C 97 60 -0.7 40 97 60 27 20 99 62 47 50 64 Bits 3C 100 100 100 100 100 100 100 100 100 100 100 100 4C 100 100 100 100 100 100 100 100 93 100 100 100 1C -53 7 -60 6 -70 10 -71 -60 -30 9 -34 -34 2C 77 45 83 60 70 35 78 68 47 48 28 33 32 Bits 3C 100 100 100 100 100 100 100 8 100 100 100 100 4C 100 100 100 100 100 100 100 100 100 100 100 100

Table 6 Dynamic power consumption of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP codecs (W)

8

679.05

16

3410.10

32

15473.70

64

100834.20

128

280298.80

Fibo-CAC

S2AP

PS-Fibo

647.73

600.00

353.80

3298.60

1475.40

1050.00

10968.60

900.00

M

Improved-Fibo-CAC

15475.00 98527.80

22511.80

6260.00

270000.00

234863.50

23190.00

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Table 7 Leakage power consumption of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP codecs (W)

Improved-Fibo-CAC

Fibo-CAC

S2AP

PS-Fibo

11.34

12.60

10.20

9.80

43.99

44.70

42.80

39.50

32

227.10

239.10

212.80

209.90

64

1303.01

1400.00

1230.00

1000.00

128

4599.23

4609.00

4320.08

4200.00

8

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Table 8 Power consumption of wires in the present of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms (W)

Wire Length

0.1 mm

0.2 mm

0.3 mm

Improved-Fibo-CAC

0.030

0.200

0.201

Fibo-CAC

0.040

0.120

0.129

S2AP

0.270

0.350

0.359

PS-Fibo

0.258

0.175

0.155

Improved-Fibo-CAC

0.100

0.180

0.189

Fibo-CAC

0.150

0.230

0.239

S2AP

0.230

0.310

0.319

PS-Fibo

0.076

0.045

Improved-Fibo-CAC

0.060

0.140

S2AP

0.280

0.360

Fibo-CAC

0.060

0.140

PS-Fibo

0.040

0.120

Football

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0.108 0.149 0.369 0.149 0.129

Table 9 Area occupation of PS-Fibo, Fibo-CAC, Improved-Fibo-CAC and S2AP coding mechanisms (𝜇𝑚 )

Improved-Fibo-CAC

Fibo-CAC

S2AP

PS-Fibo

16

2406.49

2414.74

2153.71

2008.82

32

10527.50

10529.61

9664.85

9397.11

64

48493.84

48968.97

48430.31

48337.63

128

140107.72

140735.40

139823.90

135184.97

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