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An enhancement of via profile using MLR mask
Microelectronic Engineering 88 (2011) 2604–2607
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
An enhancement of via profile using MLR mask Kang-Jin Kim a,b,⇑, Jong-Jin Park a, Sang-Hun Lee a, Sung-Il Kim a, Young-Wook Park a, Chil-Gee Lee b a b
System LSI Division, Samsung Electronics Co. Ltd, San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do 449-711, South Korea Sungkyunkwan University, Suwon 440-746, Gyeonggi-Do, South Korea
a r t i c l e
i n f o
Article history: Available online 12 February 2011 Keywords: Multi-layer resist (MLR) Striation Open defect
a b s t r a c t The fabrication process of semiconductor is more and more difficult as scaling down. Especially, the via profile formation is one of the main challenges which is suffering from making stable device process because ArF photo resist (PR) itself can not provide proper etch selectivity to sub-layers. Recently, many researches have been studied for the via process in terms of photo property, etch property and process compatibility using bi-layer resist process (BLR), tri-layer resist process (TLR), and multilayer resist (MLR) process. In this paper, we proposed and demonstrated for beyond 90 nm scaled logic via process consisting of high-k inter metal dielectric (IMD) using multi-layer resist (MLR) organic hard mask. Based on the test results described in this paper, the results show the higher etching selectivity to each layer and also helped to easily control the anisotropic profiles. Ó 2011 Published by Elsevier B.V.
1. Introduction The via profile formation is one of the main challenges which is suffering from making stable device process because ArF photo resist (PR) itself cannot provide proper etch selectivity to sub-layers. This via process consisting of high-k, F-TEOS (fluorine-doped TetraEthOxySilane) IMD film is demanded as the high aspect ratio etching process. High-k IMD film has a strength about aspect of hardness in contrast with low-k IMD film. The widespread use of high-k material began because of CMP dishing defects and enhanced pattern profiles as IMD. This device uses PR mask process (ArF PR/Bottom Anti-Reflective Coating (BARC)/FTEOS/Middle nitride dehydrated silicon nitride (DsiN)/Fluorosilicate Glass(FSG)/ Bottom nitride) structure for enhanced hardness as shown in Fig. 1a. In this stack, the BARC layer is used not only as an antireflective layer but also as an intermediate layer to keep compatibility between the ArF PR and the FTEOS film. In addition, this process has to contain photo resist (PR) of a hard mask with high selectivity. Although this process has attractive advantages in terms of device integration and productivity, this process has remarkably two demerits for the process using high-k IMD. One is the via striation defect [1]. The via etching process mainly uses a high bias power and a high source power to etch via hole. The high bias power is usually associated with the high energy bombardment that can expedite PR consumption. When PR is consumed completely
before full etching process ends, the ions of plasma will bombard to capping layer and high-k dielectrics directly. This results in abnormal pattern as shown in Fig. 2. In addition, the gap between via and metal is getting narrower than that of normal via pattern profile as shown in Fig. 3. It could affect the fixed pattern noise (FPN) fail [2]. It is caused by abnormal via pattern profile. The other is via open defect by un-etching. The main reason for above two defects is due to the low etching selectivity to PR mask. Therefore, the high etching selectivity is eventually needed to improve accuracy of etching process. The MLR mask is one of the useful methods to solve the problems. In this paper, we describe MLR mask process which shows good photo performance in ArF lithography. 2. Experiments 2.1. Materials design In order to investigate the effects of MLR mask process for the via etching process, we processed the experiment of via hole with MLR mask. We added planarizing low temperature oxide (LTO)/ Near Frictionless Carbon (NFC) film layers to a traditional film layer under ArF PR layer. The MLR mask process scheme is shown in Fig. 4b. 2.2. Pattern transfer process
⇑ Corresponding author. E-mail addresses: [email protected] (K.-J. Kim), [email protected] (C.-G. Lee). 0167-9317/$ - see front matter Ó 2011 Published by Elsevier B.V. doi:10.1016/j.mee.2011.02.057
All lithographic experiments were performed using a 193 nm ASML scanner interfaced with a track. ARC and ArF PR were succes-
K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
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Fig. 1. (a) Schematic diagram of PR mask process: ArF PR/BARC/FTEOS/DSiN/FSG stacks. (b) After etch process scheme.
Fig. 4. (a) Schematic diagrams of PR mask process: ArF PR/BARC/FTEOS/DSiN/FSG stacks and (b) LTO/NFC film layers are added to a traditional PR mask: PR/ARC/LTO/ NFC/IMD/SiO2 layers.
Fig. 2. Top view images of via profile shows via striation.
the masking protection technique using polymer rich gas (CH3F, CH2F2) to increase etching selectivity to PR. In addition, the transfers etch process of PR layer into the bottom layer utilizes such as O2 gas. The patterns after development and dry-etching were observed by critical dimensional scanning electron microscope image (CDSEM), and cross-section SEM. 2.3. MLR mask process scheme Optimized via etch recipe of MLR mask process is like below: PR/ARC/LTO/NFC/IMD/SiO2 layers ARC: CF4/CH3F LTO: CF4/H2 NFC: Ar/O2 Metal Etch (ME): O2/CH2F2/Ar Oxide Etch (OE): O2/CO/Ar.
2.4. Measurement
Fig. 3. Vertical microscope image of via profile with FPN fail resulting from low PR selectivity. The gap between via and metal is getting narrower than that of normal via pattern profile.
sively coated and baked on the stack substrate to the appropriate thickness from the simulated reflectivity curve. Pattern transfers to the substrates were conducted using various process conditions with an etch process. Layer by layer etching, namely, the transfer oxide etch of the imaging layer into middle layer like a LTO and an IMD film use standard gases like CF4/ CH3F/Ar. The FTEOS IMD uses CF4 gas heavily for etching, because the film surface of FTEOS has chemical property of getting hardener as time passes. Furthermore, we proposed and demonstrated
To determine characteristics of via process which are integrated by this method, some measurements are introduced such as the items below . (1) Confirmation of top view image. (2) Cross-sectional image by vertical SEM. (3) Confirmation of after clean inspection critical dimension (ACI CD). 3. Results and discussion 3.1. Pattern transfer performances Through the transfer performance using MLR mask process, LTO and NFC can function as a protection step of IMD. In addition, the oxide recess and PR or polymer thickness are correlated on the
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K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
Fig. 5. Enhanced via top profile due to MLR mask process.
Fig. 6. Improved via profile due to the MLR mask process.
mask protection. This means MLR mask process have very high selectivity to PR mask. It is well known that the addition of either hydro-fluorocarbon such as CH3F or CH2F2 or fluorocarbon gases with high Carbon and Fluorine ratio to a background CF4 plasma is an effective way of providing precursors which form a polymeric film on the wafer which then protects the surface from ion bombardment. As a result, the MLR mask process system has the higher etching selectivity to each layer and also helps to easily control the anisotropic profiles as shown in Figs. 5 and 6. 3.2. ACI CD trend Out-put data using MLR mask process showed enhanced CD uniformity as shown in Fig. 5. In addition, the result showed that
there is no significant difference between the two production methods. It proved that MLR mask process is positively effective for enhanced via profile of high-k IMD layers (Fig. 7). 4. Conclusion In this paper, we proposed conventional PR mask process and MLR mask process for cross-sectional images and electric characteristics. The narrowed gap between via and metal could affect the FPN fail. It was caused by striation via pattern. The narrowed gap was improved by MLR mask process. The optimized MLR mask process would be more effective method to well-defined via profile. The results showed superior
Fig. 7. (a) CD trend using of traditional PR mask layers. (b) CD trend using MLR mask layers. It shows MLR mask is positively effective for enhanced via profile of high-k IMD layers.
K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
PR etching selectivity to achieve good via profile CD, post etch profile and good clean efficiency of deposited polymer around bottom of via profile and side wall. Continuously, the optimized process has been studied in real product application. This technique will be one of the promising candidates to overcome the difficulties of deep and small via process beyond 90 nm technology in the future.
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References [1] Wu Sun⁄, Man-Hua Shen, Xin-Peng Wang, Mechanism of Via Etch Striation and Its Impact on Contact Resistance & Breakdown Voltage in 65 nm Co low-k interconnects, in: Solid-State and Integrated-Circuit Technology, ICSICT (2008), pp. 1235–1237. [2] Fry, Noble, Rycroft’. P. Fry, P. Noble, R. Rycroft, Fixed pattern noise inphotomatrices, IEEE J. Solid-state Circuits, vol. SC-5(5), 1970, pp. 250–254.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
An enhancement of via profile using MLR mask Kang-Jin Kim a,b,⇑, Jong-Jin Park a, Sang-Hun Lee a, Sung-Il Kim a, Young-Wook Park a, Chil-Gee Lee b a b
System LSI Division, Samsung Electronics Co. Ltd, San #24, Nongseo-Dong, Giheung-Gu, Yongin-City, Gyeonggi-Do 449-711, South Korea Sungkyunkwan University, Suwon 440-746, Gyeonggi-Do, South Korea
a r t i c l e
i n f o
Article history: Available online 12 February 2011 Keywords: Multi-layer resist (MLR) Striation Open defect
a b s t r a c t The fabrication process of semiconductor is more and more difficult as scaling down. Especially, the via profile formation is one of the main challenges which is suffering from making stable device process because ArF photo resist (PR) itself can not provide proper etch selectivity to sub-layers. Recently, many researches have been studied for the via process in terms of photo property, etch property and process compatibility using bi-layer resist process (BLR), tri-layer resist process (TLR), and multilayer resist (MLR) process. In this paper, we proposed and demonstrated for beyond 90 nm scaled logic via process consisting of high-k inter metal dielectric (IMD) using multi-layer resist (MLR) organic hard mask. Based on the test results described in this paper, the results show the higher etching selectivity to each layer and also helped to easily control the anisotropic profiles. Ó 2011 Published by Elsevier B.V.
1. Introduction The via profile formation is one of the main challenges which is suffering from making stable device process because ArF photo resist (PR) itself cannot provide proper etch selectivity to sub-layers. This via process consisting of high-k, F-TEOS (fluorine-doped TetraEthOxySilane) IMD film is demanded as the high aspect ratio etching process. High-k IMD film has a strength about aspect of hardness in contrast with low-k IMD film. The widespread use of high-k material began because of CMP dishing defects and enhanced pattern profiles as IMD. This device uses PR mask process (ArF PR/Bottom Anti-Reflective Coating (BARC)/FTEOS/Middle nitride dehydrated silicon nitride (DsiN)/Fluorosilicate Glass(FSG)/ Bottom nitride) structure for enhanced hardness as shown in Fig. 1a. In this stack, the BARC layer is used not only as an antireflective layer but also as an intermediate layer to keep compatibility between the ArF PR and the FTEOS film. In addition, this process has to contain photo resist (PR) of a hard mask with high selectivity. Although this process has attractive advantages in terms of device integration and productivity, this process has remarkably two demerits for the process using high-k IMD. One is the via striation defect [1]. The via etching process mainly uses a high bias power and a high source power to etch via hole. The high bias power is usually associated with the high energy bombardment that can expedite PR consumption. When PR is consumed completely
before full etching process ends, the ions of plasma will bombard to capping layer and high-k dielectrics directly. This results in abnormal pattern as shown in Fig. 2. In addition, the gap between via and metal is getting narrower than that of normal via pattern profile as shown in Fig. 3. It could affect the fixed pattern noise (FPN) fail [2]. It is caused by abnormal via pattern profile. The other is via open defect by un-etching. The main reason for above two defects is due to the low etching selectivity to PR mask. Therefore, the high etching selectivity is eventually needed to improve accuracy of etching process. The MLR mask is one of the useful methods to solve the problems. In this paper, we describe MLR mask process which shows good photo performance in ArF lithography. 2. Experiments 2.1. Materials design In order to investigate the effects of MLR mask process for the via etching process, we processed the experiment of via hole with MLR mask. We added planarizing low temperature oxide (LTO)/ Near Frictionless Carbon (NFC) film layers to a traditional film layer under ArF PR layer. The MLR mask process scheme is shown in Fig. 4b. 2.2. Pattern transfer process
⇑ Corresponding author. E-mail addresses: [email protected] (K.-J. Kim), [email protected] (C.-G. Lee). 0167-9317/$ - see front matter Ó 2011 Published by Elsevier B.V. doi:10.1016/j.mee.2011.02.057
All lithographic experiments were performed using a 193 nm ASML scanner interfaced with a track. ARC and ArF PR were succes-
K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
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Fig. 1. (a) Schematic diagram of PR mask process: ArF PR/BARC/FTEOS/DSiN/FSG stacks. (b) After etch process scheme.
Fig. 4. (a) Schematic diagrams of PR mask process: ArF PR/BARC/FTEOS/DSiN/FSG stacks and (b) LTO/NFC film layers are added to a traditional PR mask: PR/ARC/LTO/ NFC/IMD/SiO2 layers.
Fig. 2. Top view images of via profile shows via striation.
the masking protection technique using polymer rich gas (CH3F, CH2F2) to increase etching selectivity to PR. In addition, the transfers etch process of PR layer into the bottom layer utilizes such as O2 gas. The patterns after development and dry-etching were observed by critical dimensional scanning electron microscope image (CDSEM), and cross-section SEM. 2.3. MLR mask process scheme Optimized via etch recipe of MLR mask process is like below: PR/ARC/LTO/NFC/IMD/SiO2 layers ARC: CF4/CH3F LTO: CF4/H2 NFC: Ar/O2 Metal Etch (ME): O2/CH2F2/Ar Oxide Etch (OE): O2/CO/Ar.
2.4. Measurement
Fig. 3. Vertical microscope image of via profile with FPN fail resulting from low PR selectivity. The gap between via and metal is getting narrower than that of normal via pattern profile.
sively coated and baked on the stack substrate to the appropriate thickness from the simulated reflectivity curve. Pattern transfers to the substrates were conducted using various process conditions with an etch process. Layer by layer etching, namely, the transfer oxide etch of the imaging layer into middle layer like a LTO and an IMD film use standard gases like CF4/ CH3F/Ar. The FTEOS IMD uses CF4 gas heavily for etching, because the film surface of FTEOS has chemical property of getting hardener as time passes. Furthermore, we proposed and demonstrated
To determine characteristics of via process which are integrated by this method, some measurements are introduced such as the items below . (1) Confirmation of top view image. (2) Cross-sectional image by vertical SEM. (3) Confirmation of after clean inspection critical dimension (ACI CD). 3. Results and discussion 3.1. Pattern transfer performances Through the transfer performance using MLR mask process, LTO and NFC can function as a protection step of IMD. In addition, the oxide recess and PR or polymer thickness are correlated on the
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K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
Fig. 5. Enhanced via top profile due to MLR mask process.
Fig. 6. Improved via profile due to the MLR mask process.
mask protection. This means MLR mask process have very high selectivity to PR mask. It is well known that the addition of either hydro-fluorocarbon such as CH3F or CH2F2 or fluorocarbon gases with high Carbon and Fluorine ratio to a background CF4 plasma is an effective way of providing precursors which form a polymeric film on the wafer which then protects the surface from ion bombardment. As a result, the MLR mask process system has the higher etching selectivity to each layer and also helps to easily control the anisotropic profiles as shown in Figs. 5 and 6. 3.2. ACI CD trend Out-put data using MLR mask process showed enhanced CD uniformity as shown in Fig. 5. In addition, the result showed that
there is no significant difference between the two production methods. It proved that MLR mask process is positively effective for enhanced via profile of high-k IMD layers (Fig. 7). 4. Conclusion In this paper, we proposed conventional PR mask process and MLR mask process for cross-sectional images and electric characteristics. The narrowed gap between via and metal could affect the FPN fail. It was caused by striation via pattern. The narrowed gap was improved by MLR mask process. The optimized MLR mask process would be more effective method to well-defined via profile. The results showed superior
Fig. 7. (a) CD trend using of traditional PR mask layers. (b) CD trend using MLR mask layers. It shows MLR mask is positively effective for enhanced via profile of high-k IMD layers.
K.-J. Kim et al. / Microelectronic Engineering 88 (2011) 2604–2607
PR etching selectivity to achieve good via profile CD, post etch profile and good clean efficiency of deposited polymer around bottom of via profile and side wall. Continuously, the optimized process has been studied in real product application. This technique will be one of the promising candidates to overcome the difficulties of deep and small via process beyond 90 nm technology in the future.
2607
References [1] Wu Sun⁄, Man-Hua Shen, Xin-Peng Wang, Mechanism of Via Etch Striation and Its Impact on Contact Resistance & Breakdown Voltage in 65 nm Co low-k interconnects, in: Solid-State and Integrated-Circuit Technology, ICSICT (2008), pp. 1235–1237. [2] Fry, Noble, Rycroft’. P. Fry, P. Noble, R. Rycroft, Fixed pattern noise inphotomatrices, IEEE J. Solid-state Circuits, vol. SC-5(5), 1970, pp. 250–254.