An instrumental solution to the phenomenon of negative capacitances in semiconductors

Solid-Stare Electronics Vol. 39, No. 3, pp. 333-336, 1996 Copyright 0 1996 Elsevicr Science Ltd 0038-1101(95)00143-3 Printed in Great Britain. All rights reserwd 0038-1101/96 $15.00+0.00

Pergamon

AN INSTRUMENTAL SOLUTION OF NEGATIVE CAPACITANCES

TO THE PHENOMENON IN SEMICONDUCTORS

K. S. A. BUTCHER’, T. L. TANSLEY’ and D. ALEXIEV’ Science and Technology Laboratories, Physics Department, Macquarie University, NSW 2109 and 2Australian Nuclear Science and Technology Organisation, Menai, NSW 2232, Australia ‘Semiconductor

(Received

IO June 1995)

Abstract-A number of authors make reference to “negative capacitances” observed during impedance measurements of metal-semiconductor and other semiconductor device structures at sufficiently low frequencies for parasitic inductances to be assumed negligible. Often, these negative capacitances are attributed to physical phenomena associated with the devices being measured. It is demonstrated in this paper that many such interpretations incorrectly neglect the importance of parasitic series inductances at low frequencies when device conductance is large, as in a forward biased Schottky barrier, or when large device leakage currents are present. Simulations of experimental data for a Schottky diode show that typical values of probe lead and other instrumental inductance may be sufficient to provide an instrumental explanation for the apparent effect.

NOTATION

c

cm

G G, i L R w

device capacitance (F) measured capacitance (F) device conductance (S) measured conductance (S) imaginary number parasitic series inductance (H) parasitic series resistance (52) angular frequency (radians SC’) 1. INTRODUCUON

Metal-semiconductor (MS) devices are amongst the most simply constructed of rectifying barriers; they have been studied for well over fifty years, with the 1938 theories of Mott[l] and Schottky[2] forming the basis for our present understanding of these structures. Despite its apparent simplicity, the MS or Schottky barrier is a rich source of physical phenomena which has yet to be fully understood. For instance, the measurement of interface state densities, long thought to be the cause of Fermi level pinning for some III-V semiconductors, is not carried out by any standardized admittance based techniques. This is in contrast to the case for metal-insulator-semiconductor (MIS) structures for which capacitance and conductance techniques are now well established for determining the density and energy distribution of interface states. For MS devices, the intimacy of the metal contact with the interface states of the semiconductor and the inability to sweep the Fermi level of a pinned surface lead to practical difficulties in implementing meaningful admittance based measurements for

the same purpose[3]. An added problem for admittance measurements with MS structures is the influence of external factors, such as parasitic series resistances and series inductances, which have a much more pronounced influence on the extraction of device related parameters than for MIS structures. Goodman[4] has already examined the effect of parasitic series resistances during capacitance and conductance measurements of MS devices. Equations were presented showing the relationship between measured values of conductance and capacitance and the parasitic series resistance[rl]. Similarly, in this paper we have calculated related equations involving corrections for both parasitic series inductance and series resistance for the accurate determination of device parameters. The important result of this analysis was found at low frequencies and is therefore relevant to observations of so-called “negative capacitances”. Normally inductive effects associated with the contacts and leads of a measurement system are observed only at very high frequencies in and beyond the MHz range, so the observation of “negative capacitances” at frequencies as low as 32 Hz[S] has led to the general belief that the inductive contribution of the measurement system is negligible, and that some new charge storage mechanism is at work within the semiconductor itself. More than thirty reports of “negative capacitance” have appeared in the literature with various, sometimes elaborate, explanations offered for the exact form of the semiconductor charge mechanism at work[5-361. Despite the many attempts that have been made to explain low frequency “negative 333

K. S. A. Butcher et al.

334

capacitances”, largely intuitive arguments (and some erroneous attempts at circuit replacement) have been used to refute the argument that parasitic series inductances of probes and leads used in measurement systems can explain the phenomenon. In this report, we show that inductive effects can be important at low frequency if a high device conductance is present. The analysis concentrates on Schottky diodes for the specific purpose of showing where “negative capacitance” can originate in low frequency C-V measurements. The analysis can, however, be applied to other device structures and is indeed embedded in standard network parameter packages, where it is of most significance in bipolar emitter circuits.

1 L

4 R

Gr?l C

G

w

(4

Fig. 1. (a) Measured components of capacitance (C,,,) and conductance (G,) found in parallel measurement mode; (b) 2. NEGATIVE

equivalent circuit showing required values of capacitance (C) and conductance (G) in the presence of parasitic series resistance (R) and inductance (f,).

CAPACITANCES

Most impedance measurement systems used for semiconductor devices measure an equivalent conductance, G,, and parallel capacitance, C,,,, from which meaningful data can be derived. The following analysis discusses the case of a Schottky diode measured in this way. The equivalent circuit, shown in Fig. l(a), indicates the values of capacitance, C,, and conductance, G,, measured in the parallel mode, while Fig. I(b) shows a realistic equivalent circuit with parallel components of junction capacitance, C, and conductance, G, with parasitic series inductance, L, and series resistance, R. As mentioned above, Goodman[4] has treated the case of parasitic series resistance, included here for complete-

ness. The values of C and G which are of interest can be found from the measured C,,, and G, by equating the total impedance of the two circuits of Fig. 1 at angular frequency w : 1 1 =----+iioL+R. G, + iwC,,, G + ioC

Real and imaginary parts are readily compared to give the diode parameters as functions of their measured equivalents:

Cl G=

-R

G; + (WC,)*

Cl

&II

(2)

2’

(3)

Clll +L G; + (WC,)’ Gill

@Cm

G; + (UC,)* The complementary

2’

+wL. Gf, + (WC,,,)*

G; + (oC,,,)~

C=

(1)

G; + (oC,)’

+oL.

equations for G, and C, are: G

+R

G2 + (WC)*

G,=

cdC cm=

G* + (coC)~ G G* + (cd)*

WC

2’

(4)

G2 + (WC)’

-L

oL-

(5)

Negative capacitances in semiconductors Equation (5) shows the circumstances in which apparent “negative capacitances” may arise, that is when L > C/[G* + (WC)‘]. While G remains small, in a reverse biased Schottky diode, for example, the inequality is met only at frequencies above the MHz range in a typical device, tending to the limit UC,,, = - l/oL at very high frequencies. This is the intuitively obvious case of series inductance and capacitance being dominated by the impedance of the former at high frequency, and is taken into account by most investigators. Less obvious is the case in which G is large, in a forward biased Schottky diode, for example, compared with WC. Since the latter is always small at sufficiently low frequencies, “negative capacitance” is recorded whenever G* > C/L and is, furthermore, independent of frequency. This relationship is important because G increases exponentially with forward bias, while C increases more slowly. Unfortunately, past researchers of the so-called “negative capacitance” phenomenon have not carried out the above elementary analysis and, in fact, the values of parasitic inductance and resistance present for their experiments are usually left unreported. Similarly, only a handful of reports present any conductance data with their observations of negative capacitance. It therefore appears that the reports of apparent “negative capacitance” so far published must be regarded with some scepticism, since they have failed to demonstrate that they adequately accounted for the instrumental effects of parasitic inductance, as outlined above. To demonstrate the strength of the parasitic inductance component, eqn (3) can be simplified for the case where C,,, = 0, so that it becomes: C=

L

(6)

For this particular case, eqn (6) is also equal to C,,, - C, since C, = 0. Figure 2 shows values of C, - C calculated with eqn (6) (at a frequency of 100 Hz using R = 10 a) for a range of G,,, values and for various values of parasitic inductance. The parasitic inductances shown in the figure were chosen such that they span a wide range of values likely to be encountered in most experimental apparatus. At high values of G,, Fig. 2 shows that the disparity between the measured value of C,,, and the device capacitance C becomes quite significant, especially for higher parasitic inductances. The figure also demonstrates that so-called “negative capacitances” can be observed in the presence of what is actually a large C value. As G, approaches the limiting value of R, the value of C or (C - C,,,) increases more sharply, eventually being limited to the value l/(co*L), potentially a very large “negative capacitance” indeed. This leads us to conclude that the observed “negative capacitance” phenomenon may be readily accounted for by typical instrumental factors extrinsic to the device under test. The dis-

335

i

10

-16

1 10-6

I 10-S

10-4

10-S

10-Z

10-l

100

G,,,6% Fig. 2. Simulations of actual capacitance (and in this case the difference between actual capacitance and measured capacitance) vs measured conductance G,,, for R = 10R, C, = 0 and a frequency of 100Hz.

parity between C,,, and C (and the corresponding disparity which exists between G, and G) demonstrates why past attempts at circuit replacement have been poor indicators of the origin of negative capacitance; the temptation being to use passive components related to G, and C,,,, rather than C, G and R, to help determine when the value of L is significant . Given the above results, it must again be emphasized that a full analysis of any experimental data relating to the phenomenon of “negative capacitance” requires measurements of both C, and G, to be available, and also a knowledge of the parasitic series inductance L and series resistance R. Most reported observations of “negative capacitance” include only C,,, data, so that the values of C, G, R and L, necessary to accurately assess the phenomenon, cannot be deduced. It is clearly necessary for impedance measurements of Schottky barriers, or other devices where large conductances may coincide with small capacitances, to include both the reactive and conductive components even at low frequencies, where inductive contributions are usually ignored. Measured values of L should also be included in many instances. Ambiguities arising from misunderstood phenomena, such as negative capacitances, thus may be avoided. We believe that a proper understanding of Schottky barrier interface states has been hampered by analyses of impedance data which have not appreciated the interdependence of the reactive and conductive impedance components. 3. CONCLUSION

Although familiar in emitter circuit design in high speed bipolar technology, small series inductances are generally assumed not to significantly affect the outcome of complex impedance measurements made on

K. S. A. Butcher et al.

336

metal-semiconductor devices at low frequencies. Proper analysis reveals, however, that dominant effects occur as the value of the parasitic inductance L becomes comparable with, or greater than, the ratio C/G*, where C and G are the device capacitance and conductance, respectively. This phenomenon is substantially independent of frequency. An extreme example is the appearance of “negative capacitance”, reported by a number of workers and described in terms of a range of proposed trapping/ detrapping mechanisms, for which other support is scant. A simulation of a number of possible experimental conditions has shown that many, if not all, past occurrences of “negative capacitance” fall within a range readily ascribed to the presence of parasitic series inductance of magnitudes compatible with probe lead and other instrumental inductances. We strongly caution against invoking intrinsic semiconductor phenomena to explain experimental results which may be well accounted for by properties of the instrumentation. Accordingly, we would encourage the use of a more rigorous measurement regime, to include measurements of the capacitance and conductance components of the device under test and also the parasitic resistances and inductances, in order to provide an accurate assessment of the phenomena of “negative capacitance”. Acknowledgements-K. S. A. Butcher would like to acknowledge the support of a Macquarie University Postgraduate Research Award during the writing and formulation of this work. We would also like to thank Dr Xin Li for aid in the plotting of one of the attached figures.

REFERENCES 1. N. F. Mott, Proc. Camb. Philos. Sot. 34, 568 (1938). 2. W. Schottky, Naturwissenschaften 26, 843 (1938). 3. E. H. -Rhoderick and- R. H. Wihiams, Me@-Semiconductor Contacts. 2nd Edn. DD.155-157. Clarendon Press, Oxford (1988). -n 4. A. M. Goodman, J. appl. Phys. 34, 329 (1963). 5. J. Werner, A. F. J. Levi, R. T. Tung, M. Anzlowar and M. Pinto, Phys. Rev. Lett. 60, 53 (1988). 6. Y. Kanai, J. Phys. Sot. Japan 10, 718 (1955). 7. T. Misawa, J. Phys. Sot. Japan 12, 882 (1957).

8. 0. J. Marsh and C. R. Viswanathan, J. appl. __ Phys. 38, 3135 (1967).

9. R. F. Kararinov. V. I. Stafeev and R. A. Suris. Sov. Phys. Semicond. i, 1084 (1967). 10. R. Vogel and P. J. Walsh, Appl. Phys. Lerr. 14, 216

(1969). H. K. Rockstad, J. appl. Phy.s. 42, 1159 (1971). 12. S. A. Altunyan, V. S. Minaev, V. I. Stafeev, L. S. Gasanov. A. S. Deshevoi and B. K. Skachkov. Sov. II.

Phys. Sekicond.

5, 427 (1971).

13. W. W. Sheng and C. R. Westgate, Solid St. Commun. 9, 387 (1971).

14. J. Allison and V. R. Dawe, Electron. L.etf. 7,706 (1971). 15. A. A. Sukhanov, Sov. Phys. Semicond. 5, 1160 (1972). 16. V. A. Brodovoi and N. Z. Deirkot, Sov. Phys. Semicond. 7, 459 (1973).

17. B. T. Kolomiets, A. Ya. Karachentsev

and V. V. Spevak, Sov. Phys. Semicond. 7, 872 (1974). 18. G. C. Vezzoli, P. J. Walsh and L. W. Doremus, J. Non-Crystalline Solids 18, 333 (1975). 19. G. A. Egiazaryan and V. I. Stafeev, Sov. Phys. Semicond. 9, 334 (1975).

20. V. N. Dul’dier, Yu. D. Dumarevskii, A. S. Deshevoi, A. A. Lavernov, V. A. Petrusevich and A. I. Polovyanyuk, Sov. Phys. Semicond. 10, 253 (1976). 21. A. S. Deshevoi and L. S. Gasanov, Sov. Phys. Semicond. 11, 1168 (1977). 22. T. Noguchi, M. Kitagawa and I. Taniguchi, Japan J. Appl. Phys. 19, 1423 (1980). 23 G. SNadkarni, N. Sankarraman and S. Radhakrishnan. J. Phvs. D.: Aool. Phvs. 16. 897 (1983). 24 V. N. Alimpiev andi. R. Gural’nik. S&J. dhys. Semicond. 18, 420 (1984). 1c L,. J. Millan, V. Villaronga, J. R. Morante, F. Serra-Meatres and A. Herms, Physica B 129,351 (1985). 26. G. Blatter and F. Greuter, Phys. Rev. B 34,8555 (1986). 27. A. K. Jonscher, C. Pickup and S. H. Zaidi, Semicond. Sci. Technol. 1, 71 (1986). 28, S.-T. Fu and M. B. Das, IEEE Trans. Electron Devices ED34, 1245 (1987). 29. A. K. Jonscher and M. N. Robinson, Solid-St. Electron. 31, 1277 (1988). 30. X. Wu and E. S. Yang, J. appl. Phys. 65, 3560 (1989). 31. C. H. Champness and W. R. Clark, Appl. Phys. Lett. 56, 1104 (1990). 32. X. Wu, E. S. Yang and H. L. Evans, J. appl. Phys. 68, 2845 (1990). 33. W. R. Clark and C. H. Champness, Can. J. Phys. 69, 311 (1991). 34. J. H. Werner, J. appl. Phys. 70, 1087 (1991).

35. P. Muret, D. Elguennouni, M. Missous and E. H. Rhoderick, Appl. Phvs. Lert. 58, 155 (1991). 36. X. Wu, H. L.*Evans-and E. S. Yang, j. ap$ Phys. 70, 1089 (1991).