- Email: [email protected]
An integrated approach to routing and via minimization
Information Processing Letters 39 (1991) 257-263 North-Holland
13 September 1991
Department of Electrical and Computer Engineering, University of CalijG~nia, Irvine, CA 92717, USA
John D. Provence Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75275, USA Communicated by D.A. Plaisted Received 6 September 1990 Revised 18 June 1991
Keywords: Computational
geometry, VLSI routing, rectilinear Steiner trees, via minimization
1. Introduction Routing is the phase of IC layout which involves interconnecting a large number of circuit elements on the chip by means of metal or polysilicon wires. Circuit interconnections are known to occupy nearly 70% of the area on a typical IC. With shrinking device sizes, interconnection wires could therefore become a major bottleneck in the drive towards miniaturization. There is hence a great need to minimize the cost associated with routing, both in terms of the area on silicon and also the design time. In view of such enormous importance, VLSI routing has been extensively studied in literature. Normally, VLSI routing is done in Manhattan metric, in which the wires are restricted to run either in the horizontal or in vertical directions. In most technologies, two layers on the chip are available for routing. As a convention, all horizontal wires are confined to one layer while all vertical wires are kept in another. In most practical cases, it becomes necessary for any single interconnecting wire to have both vertical and horizontal parts. This implies that every wire would be present partly in one layer and partly in 0020-0190/91/$03.50
another, and provision will have to be made to interconnect two such parts at some lwation on the layout. These designated points which serve to provide physical contact between wires in different layers are called Gas, and are simply holes made through the insulating oxide layer that separates the two layers of interconnections. For several reasons, vias are generally considered undesirable features on a silicon chip. For one, they reduce the yield of the chip; for another, they result in higher resistance and capacitance which leads to degraded circuit performance. In addition, they pose problems in the fabrication process, and are more likely to fail than other features of layout. Therefore, it is important to reduce the number of vias in a layout. A variety of algorithms have been developed for this problem of via minimization, see, for example, [5,10]. It is worth mentioning that although the problems of routing and via minimization are so closely related, there have not been many efforts aimed at evolving a global or integrated approach to these two problems. This communication is devoted to the development of one such approach. Since the routing domain can be mapped on to
0 1991 - Elsevier Science Publishers B.V All rights reserved
257
Volume 39, Number 5
a graph, and since the problem of interconnecting the pins is the same as constructing a spanning tree on these points, minimal spanning tree alpen extensively studied as solugorithms have be,*. tions to the routing problem. Some researchers have also proposed optimal Steiner trees as a possible way of obtaining lesser total wire lengths. Steiner trees achieve this reduction in wire length by utilizing some additional points apart from those in the given set. These extra points are referred to as Steiner points. We propose here that these Steiner points can be mapped on to vias in a layout, and by identifying certain properties of optimal Steiner trees, we can minimize the number of vias used. Another important contribution of this communication is the identification of the fact wire takes a that whenever an intercolmection bend, it changes its layer, implying that a via needs to be placed at that point. On the Steiner tree, these bends, or corner points, can also be minimized by techniques similar to the ones used for minimizing the number of Steiner points.
arks Most practical routing is done in the Manhattan, or rectilinear metric, in which the distance between two points i and j whose coordinates are (x,9 ~1) and ( x2, y2) is given by $=
I~2--%I+IY2-Yd~
The routing problem can be formally stated as: “Given a routing region R OFa set of modules ( M, >, i = 1,-**, m placed within it; given a set of terminals (T,), j= I,..., n, find * a set of nets interconnecting the specified terminals, along with a set V of vias.” The optimal routing problem seeks to minimize the total length of these nets. As mentioned earlier, vias are undesirable elements in circuit layouts and need to be minimized. We will now give a brief overview of Steiner trees and their application to routing. Since routing is to be performed in the rectilinear metric, we will emphasize rectilinear Steiner trees (MT) in this discussion. RST’s have wide ranging applications in WSI physical design. In fact, the con258
13 September 1991
INFORMATION PROCESSING LETTERS
a
8 (Steiner Pt)
c (Comer Pt) Fig. 1. An example Steiner tree.
struction of a minimal RST was first studied by Hanan in relation to wiring problems in PCB’s [4]. The rectilinear Steiner problem consists of finding a spanning tree of optimal length on a set A = 0 I,.... cl,,} of given points, using an additional set P= {p,,..., p,,, } of Steiner points. We denote the set A u P as V, and state the problem formally as follows: “Among all possible trees in the graph G( k’, A ), where B is the set of edges connecting adjacent nodes in V, find the one with minimum total length (of its edges) containing all the members of the set A = (a,, . . . , a,, 1.” With reference to rectilinear metric, the set P is the set of intersection points produced by passing horizontal and vertical grid lines through the given n points. It has been proven that there exists a minimal RST in which all the Steiner points belong to this set of intersection points [4]. An example RST is shown in Fig. 1, along with the Steiner and corner points formed. Some known necessary conditions for a minimal rectilinear Steiner tree are summarized in the following three equations. Here d(q;) denotes the degree of a vertex q,. d(p,)
=3 or4,
d(a,)<4,
i=l,2
,..,,
m,
.i=1,2
,...,
n,
OQm
Volume 39, Number 5
INFORMATION
PROCESSING
with an optimal YST compared to an RMST. Although there is no lower bound on the wire length savings, the optimal RST turns out to be shorter in most cases than the RMST. In addition, in the case of VLSI routing that we are looking at, the Steiner points neatly map on to the vias, and hence the via minimization problem can be incorporated in routing. Unlike the deceptively similar minimal spanning tree problem, the rectilinear Steiner tree problem is NP-complete [2]. In view of this, a large number of suboptimal RST algorithms have been developed. Hanan [3] suggested an 0( n’ ) heuristic which can be regarded as a generalization of Prim’s minimal spanning tree algorithm. Some recently developed algorithms include the 0( n*) heuristic proposed by Lee et al. [9], Hwang’s O(n log n) modification for the same [7], etc. A general review of the various Steiner problems can be found in 1111.
3. An algorithm for rectilinear Steiner trees We propose in this section an integrated approach to routing and via minimization. We do this by identifying certain distinctive properties of the Steiner tree, specially those that concern the Steiner points and the corner points of the tree. In essence, our approach can be described as follows: we adopt the O(n log n) suboptimal RST algorithm of Hwang [7], and propose that certain unique properties of RST’s can be incorporated into the algorithm, resulting in a reduction of the number of Steiner points and corner points, and hence the number of Gas. While trying to reduce the number of Gas, the algorithm has built-in checks to ensure that the length of the resulting tree never exceeds that of the minimal spanning tree. In the next subsection, we put forward certhat identify the reduction tain propositions criteria, and provide proofs where appropriate. Simple proofs are omitted. Such reduction methods have been studied earlier with regard to generalized Steiner networks in [l], and we adopt some of our propositions from their comprehensive discussion by modifijing them for Steiner trees in rectilinear metric.
LETTERS
33 September 1991
3. I. Reduction procedures Some definitions and terminologies used in the following propositions are first given. In Section 2, we defined A as the set of given points and P as the set of Steiner points. We define an A-A edge as the edge between two given points, an A-P edge as the edge between a given point and a Steiner point, and so on. We also define C as the set of corner points. We denote the rectilinear minimal spanning tree on the set of points A as T(A) and the rectilinear minimal Steiner tree as ST(A). We first state some obvious local properties that could lead to reduction in the size of the problem: (A) If there is a P-vertex whose degree is 1, then the vertex and the edge incident on it can be removed. (B) If a P-vertex has degree 2, then it can be replaced by a C-vertex. More generally, any Pvertex of degree less than 3 can be eliminated. (C) If an edge (i. j) is such that its length c,, is greater than the minimum length path d,,, then (i, j) can be removed. (ID) Further, if there are two adjacent Avertices i and j, and there is a third A-vertex k such that c,, > d,, and c,, > d+ then (i, j) can be removed. The main propositions that form the core of our reduction procedures are now presented. The proofs are mostly based on geometrical representations, and we make use of the following operations in giving the proofs: Shifting a line means moving it between two parallel lines until it is
A
(4
(b)
Fig. 2. (a) Shifting; and (b) Flipping operations. 259
Volume 39. Number 5
INFORMATION
PROCESSING LETTERS
incident to a certain specified point. Flipping a comer CI between two specified points x and y adjacent to the comer means moving X(Ytowards y (along Y(Y)and ya towards x (along xa) (see Fig. 2). It is clear that after shiftings and flippings, the resultant graph is still a tree, and of the same length. oposition 1 [l]. Zf there is an A -A edge in T( A), then it must belong to ST(A) as well. Propdim 2 [l]. ST( A) will contain an A-P edge (i, j), where i E P and j E A only if this edge belongs to T( A U ( i 1). reposition 3 [l]. ST( A) will contain a P-P edge (i, j) for any i, jE P only if T(A U (i, j>) contains this edge. Corollary. ST(A) will contain a C-P edge (i, j) with i E C andj E P iff T(A U (i, j>) contains this edge. Proposition 4. Zf two vertices i and j (belonging either to A or P) are connected by two straight lines resulting in a corner point c, then there cannot exist another lme lying on the same side of ic (jc) as j (i). oof. Consider the case as shown in Fig. 3(a). If the dotted line exists, then we can flip the comer c between i and j and cause cj to overlap with the dotted line. Alternately, ci could be moved towards j. Either way, flipping operation would eliminate the dotted line. 0
13 September 1991
Imposition 5. At most one edge incident on a Steiner point can have a corner vertex as its other end. roof. There are two possible cases in which this can happen: (a) the Steiner point connects two noncollinear comer vertices; (b) the two comer points are collinear on either side of the Steiner point (Figs. 3(b) and 3(c)). (a) cannot exist because in that case we can always shift one of the corner points to coincide with the Steiner point and save. (We can move cs down.) (b) cannot exist because a Steiner point should have its degree greater than or equal to 3, and if it does have another line passing through it, then one of the comers can be eliminated by shifting the comer line to coincide with the line at the Steiner point. (We can move cd down, eliminating either c or d.) Thus there cannot be two corner vertices adjacent to a Steiner point. Cl Proposition 6. Consider two vertices i and j, one belonging to A and another to P. Zfj has a collinear vertex k, then the straight line from i in the same direction as jk must (a) be shorter than jk if it terminates on a corner point; and (b) turn away from jk. oof. The situation we are referring to is depicted in Fig. 3(d). Clearly, the vertical line at c cannot turn towards jk, because then we could extend it and make it meet jk. Also, if c were a corner point with ic longer than jk, then we could shift ij to ik, eliminating the Steiner point, and saving on length. q
i
k
(4
(b) Fig. 3. Figures for (a) Proposition 4; (b), (c) Proposition 5; and (d) Proposition 5.
260
(4
Volume 39, Number 5
INFORMATION
PROCESSING
roposition 7. There cannot be more than one corner vertex with the same x or y coordinates. roof. If the above case occurs, it is apparent that one of the corner points can be eliminated by the shifting operation which makes it coincide with the other. i7 [6]. No Steiner point can be adjacent to more than two Steiner points. 3.2. The algorithm As mentioned earlier, the proposed algorithm is essentially a modification of the O(n log IZ) algorithm suggested by Hwang [7] which itself is an extension of the O(n2) heuristic of Lee, Bose and Hwang [9]. We incorporate the above enumerated reduction procedures in the Hwang’s algorithm, making sure that the enumeration scheme never takes more than O(n log n) time and the output tree is not longer than the input rectilinear minimal spanning tree. We assume that a rectilinear minimal spanning tree over the set A is available. We use the 0( n log n) algorithm suggested in [8] for this purpose. We denote this tree by T and proceed as detailed below: Step 1: Given a rectilinear minimal spanning tree T, relabel its vertices as follows: Select the
LETTERS
13 September 1991
shortest edge in T, say (i, j). Select the second shortest edge tn cident on either i or j. Let (i, k ) be such an edge. Then relabel vertex j as 1, vertex i as 2 and vertex k as 3. Recursively scan the RMST in a depth-first manner, each time selecting the current shortest edge of a not yet re’iabcl’led vertex. Vertices are relabelled 4, 5,. . . , n in the same order as they are scanned. Step 2: Construct a minimal rectilinear Steiner tree on the three points 1, 2 and 3. We make use of the fact that the Steiner point of a set of three points is located at the median of these three points. Step 3: The tree is enlarged by sequentially adding vertices 4, 5 and so on. Let us define p, to be a point such that [p,, i] is in the given RMST, and pi is labelled before. Let us also identifv two vertices s and t such that s is a vertex of degree 2 2, and is adjacent to a certain p, as defined above; and t is a vertex adjacent to s. Given that the ith point has already been included in the tree, the (i + 1)th point is added by constructing a minimal Steiner tree on the three points i + 1, s and t. This tree then replaces the edge (s, t ). In choosing the vertices to be included, we apply the above enumerated reduction procedures so that no vertex that violates them is included. The labeling procedure of Step 1 ensures that the length of the output tree never exceeds the input RMST. Each vertex that is added to the tree is also checked for possible violations of the given rules. Thus the
pm,
... ..
c I.....
. .
.
.
.
.
mm=...
F
Fig. 4. (a) Rectilinear tree, length = 4, five Steiner points. (b) Reduced rectilinear Steiner tree, length = 14. one Steiner point, two corner points. The squares are the Steiner poin!s and the circles are the comer pints. 261
Volume
INFORMATION
39. Number 5
PROCESSING
LE
13 September 1991
Table 1 Performance of the Steiner tree reduction pro&we
sub-optimal tree is output the nodes in the given set.
upon inclu&on of al
case WCobtained a ts a
iscussio
We present in this section some results of a preliminary implementation of the algori ed in C on VAX II algorithm :xras ce evaluation, it w ease of perfoduced by passing horizontal and ough all given poi division on the gn this assumption only simplifies ev not in any way hinder the gene
run on examples with example, we randomly chose a set and constructed the rectilinear Stei
eferences 111A. Bs!akris and N.R. Patek Problem reduction methods and a generation algorithm for the Steiner network problem. Neruv& 17 (1987) 65-85. [2] M.R. Garey and D.S. Johnson, The rectilinear Steiner lete. SIAM J. Appi. Math. 32 (1977) 826-834. anan, Net wiring for large scale integrated circuits. IBM Res. Kept. RC 1375. 1965. [4] M. Hanan, On Steine problem with rectilinear distance. SIAM J. Appl. Math. (1966) 255-265. [5] C.-P. Hsu, Minimllm ___...via topoiogical routing. IEEE CA D-ICAS 2 (1983) 235-24.6.
Trans.
[6] F.K. Hwang, On Steiner minimal trees with rectilinear distance, SIAM J. Appl. Math. 30 (1976) 104-114. 262
Volume 39, Number S
INFORMATION
[7] F.K. Hwang, An O(n log n) algorithm for suboptimal rectilinear Steiner trees, IEEE Trans. Circuits and Systems (1979) 75-77. [8) F.K. Hwang, An O(n log n) algorithm for rectilinear minimal spanning trees, J. ACM 26 (1979) 177-182. 9) J.H. Lee, N.K. Bose and F.K. Hwang, Use of Steiner’s problem in suboptimal routing in rectilinear metric, IEEE Trans. Circuits and Systems 23 (1976) 470-476.
PROCESSING
LETTERS
13 September 1991
[lo] M. Sarrafzadeh and D.T. Lee, A r.ew approach to top logical via minimisation, IEEE Trans. CAD-KCAS 890-900. [ll] P. Winter, Steiner problem in networks: A survey, ‘Vetworks 17 (1987) 129-167.
263
13 September 1991
Department of Electrical and Computer Engineering, University of CalijG~nia, Irvine, CA 92717, USA
John D. Provence Department of Electrical Engineering, Southern Methodist University, Dallas, TX 75275, USA Communicated by D.A. Plaisted Received 6 September 1990 Revised 18 June 1991
Keywords: Computational
geometry, VLSI routing, rectilinear Steiner trees, via minimization
1. Introduction Routing is the phase of IC layout which involves interconnecting a large number of circuit elements on the chip by means of metal or polysilicon wires. Circuit interconnections are known to occupy nearly 70% of the area on a typical IC. With shrinking device sizes, interconnection wires could therefore become a major bottleneck in the drive towards miniaturization. There is hence a great need to minimize the cost associated with routing, both in terms of the area on silicon and also the design time. In view of such enormous importance, VLSI routing has been extensively studied in literature. Normally, VLSI routing is done in Manhattan metric, in which the wires are restricted to run either in the horizontal or in vertical directions. In most technologies, two layers on the chip are available for routing. As a convention, all horizontal wires are confined to one layer while all vertical wires are kept in another. In most practical cases, it becomes necessary for any single interconnecting wire to have both vertical and horizontal parts. This implies that every wire would be present partly in one layer and partly in 0020-0190/91/$03.50
another, and provision will have to be made to interconnect two such parts at some lwation on the layout. These designated points which serve to provide physical contact between wires in different layers are called Gas, and are simply holes made through the insulating oxide layer that separates the two layers of interconnections. For several reasons, vias are generally considered undesirable features on a silicon chip. For one, they reduce the yield of the chip; for another, they result in higher resistance and capacitance which leads to degraded circuit performance. In addition, they pose problems in the fabrication process, and are more likely to fail than other features of layout. Therefore, it is important to reduce the number of vias in a layout. A variety of algorithms have been developed for this problem of via minimization, see, for example, [5,10]. It is worth mentioning that although the problems of routing and via minimization are so closely related, there have not been many efforts aimed at evolving a global or integrated approach to these two problems. This communication is devoted to the development of one such approach. Since the routing domain can be mapped on to
0 1991 - Elsevier Science Publishers B.V All rights reserved
257
Volume 39, Number 5
a graph, and since the problem of interconnecting the pins is the same as constructing a spanning tree on these points, minimal spanning tree alpen extensively studied as solugorithms have be,*. tions to the routing problem. Some researchers have also proposed optimal Steiner trees as a possible way of obtaining lesser total wire lengths. Steiner trees achieve this reduction in wire length by utilizing some additional points apart from those in the given set. These extra points are referred to as Steiner points. We propose here that these Steiner points can be mapped on to vias in a layout, and by identifying certain properties of optimal Steiner trees, we can minimize the number of vias used. Another important contribution of this communication is the identification of the fact wire takes a that whenever an intercolmection bend, it changes its layer, implying that a via needs to be placed at that point. On the Steiner tree, these bends, or corner points, can also be minimized by techniques similar to the ones used for minimizing the number of Steiner points.
arks Most practical routing is done in the Manhattan, or rectilinear metric, in which the distance between two points i and j whose coordinates are (x,9 ~1) and ( x2, y2) is given by $=
I~2--%I+IY2-Yd~
The routing problem can be formally stated as: “Given a routing region R OFa set of modules ( M, >, i = 1,-**, m placed within it; given a set of terminals (T,), j= I,..., n, find * a set of nets interconnecting the specified terminals, along with a set V of vias.” The optimal routing problem seeks to minimize the total length of these nets. As mentioned earlier, vias are undesirable elements in circuit layouts and need to be minimized. We will now give a brief overview of Steiner trees and their application to routing. Since routing is to be performed in the rectilinear metric, we will emphasize rectilinear Steiner trees (MT) in this discussion. RST’s have wide ranging applications in WSI physical design. In fact, the con258
13 September 1991
INFORMATION PROCESSING LETTERS
a
8 (Steiner Pt)
c (Comer Pt) Fig. 1. An example Steiner tree.
struction of a minimal RST was first studied by Hanan in relation to wiring problems in PCB’s [4]. The rectilinear Steiner problem consists of finding a spanning tree of optimal length on a set A = 0 I,.... cl,,} of given points, using an additional set P= {p,,..., p,,, } of Steiner points. We denote the set A u P as V, and state the problem formally as follows: “Among all possible trees in the graph G( k’, A ), where B is the set of edges connecting adjacent nodes in V, find the one with minimum total length (of its edges) containing all the members of the set A = (a,, . . . , a,, 1.” With reference to rectilinear metric, the set P is the set of intersection points produced by passing horizontal and vertical grid lines through the given n points. It has been proven that there exists a minimal RST in which all the Steiner points belong to this set of intersection points [4]. An example RST is shown in Fig. 1, along with the Steiner and corner points formed. Some known necessary conditions for a minimal rectilinear Steiner tree are summarized in the following three equations. Here d(q;) denotes the degree of a vertex q,. d(p,)
=3 or4,
d(a,)<4,
i=l,2
,..,,
m,
.i=1,2
,...,
n,
OQm
Volume 39, Number 5
INFORMATION
PROCESSING
with an optimal YST compared to an RMST. Although there is no lower bound on the wire length savings, the optimal RST turns out to be shorter in most cases than the RMST. In addition, in the case of VLSI routing that we are looking at, the Steiner points neatly map on to the vias, and hence the via minimization problem can be incorporated in routing. Unlike the deceptively similar minimal spanning tree problem, the rectilinear Steiner tree problem is NP-complete [2]. In view of this, a large number of suboptimal RST algorithms have been developed. Hanan [3] suggested an 0( n’ ) heuristic which can be regarded as a generalization of Prim’s minimal spanning tree algorithm. Some recently developed algorithms include the 0( n*) heuristic proposed by Lee et al. [9], Hwang’s O(n log n) modification for the same [7], etc. A general review of the various Steiner problems can be found in 1111.
3. An algorithm for rectilinear Steiner trees We propose in this section an integrated approach to routing and via minimization. We do this by identifying certain distinctive properties of the Steiner tree, specially those that concern the Steiner points and the corner points of the tree. In essence, our approach can be described as follows: we adopt the O(n log n) suboptimal RST algorithm of Hwang [7], and propose that certain unique properties of RST’s can be incorporated into the algorithm, resulting in a reduction of the number of Steiner points and corner points, and hence the number of Gas. While trying to reduce the number of Gas, the algorithm has built-in checks to ensure that the length of the resulting tree never exceeds that of the minimal spanning tree. In the next subsection, we put forward certhat identify the reduction tain propositions criteria, and provide proofs where appropriate. Simple proofs are omitted. Such reduction methods have been studied earlier with regard to generalized Steiner networks in [l], and we adopt some of our propositions from their comprehensive discussion by modifijing them for Steiner trees in rectilinear metric.
LETTERS
33 September 1991
3. I. Reduction procedures Some definitions and terminologies used in the following propositions are first given. In Section 2, we defined A as the set of given points and P as the set of Steiner points. We define an A-A edge as the edge between two given points, an A-P edge as the edge between a given point and a Steiner point, and so on. We also define C as the set of corner points. We denote the rectilinear minimal spanning tree on the set of points A as T(A) and the rectilinear minimal Steiner tree as ST(A). We first state some obvious local properties that could lead to reduction in the size of the problem: (A) If there is a P-vertex whose degree is 1, then the vertex and the edge incident on it can be removed. (B) If a P-vertex has degree 2, then it can be replaced by a C-vertex. More generally, any Pvertex of degree less than 3 can be eliminated. (C) If an edge (i. j) is such that its length c,, is greater than the minimum length path d,,, then (i, j) can be removed. (ID) Further, if there are two adjacent Avertices i and j, and there is a third A-vertex k such that c,, > d,, and c,, > d+ then (i, j) can be removed. The main propositions that form the core of our reduction procedures are now presented. The proofs are mostly based on geometrical representations, and we make use of the following operations in giving the proofs: Shifting a line means moving it between two parallel lines until it is
A
(4
(b)
Fig. 2. (a) Shifting; and (b) Flipping operations. 259
Volume 39. Number 5
INFORMATION
PROCESSING LETTERS
incident to a certain specified point. Flipping a comer CI between two specified points x and y adjacent to the comer means moving X(Ytowards y (along Y(Y)and ya towards x (along xa) (see Fig. 2). It is clear that after shiftings and flippings, the resultant graph is still a tree, and of the same length. oposition 1 [l]. Zf there is an A -A edge in T( A), then it must belong to ST(A) as well. Propdim 2 [l]. ST( A) will contain an A-P edge (i, j), where i E P and j E A only if this edge belongs to T( A U ( i 1). reposition 3 [l]. ST( A) will contain a P-P edge (i, j) for any i, jE P only if T(A U (i, j>) contains this edge. Corollary. ST(A) will contain a C-P edge (i, j) with i E C andj E P iff T(A U (i, j>) contains this edge. Proposition 4. Zf two vertices i and j (belonging either to A or P) are connected by two straight lines resulting in a corner point c, then there cannot exist another lme lying on the same side of ic (jc) as j (i). oof. Consider the case as shown in Fig. 3(a). If the dotted line exists, then we can flip the comer c between i and j and cause cj to overlap with the dotted line. Alternately, ci could be moved towards j. Either way, flipping operation would eliminate the dotted line. 0
13 September 1991
Imposition 5. At most one edge incident on a Steiner point can have a corner vertex as its other end. roof. There are two possible cases in which this can happen: (a) the Steiner point connects two noncollinear comer vertices; (b) the two comer points are collinear on either side of the Steiner point (Figs. 3(b) and 3(c)). (a) cannot exist because in that case we can always shift one of the corner points to coincide with the Steiner point and save. (We can move cs down.) (b) cannot exist because a Steiner point should have its degree greater than or equal to 3, and if it does have another line passing through it, then one of the comers can be eliminated by shifting the comer line to coincide with the line at the Steiner point. (We can move cd down, eliminating either c or d.) Thus there cannot be two corner vertices adjacent to a Steiner point. Cl Proposition 6. Consider two vertices i and j, one belonging to A and another to P. Zfj has a collinear vertex k, then the straight line from i in the same direction as jk must (a) be shorter than jk if it terminates on a corner point; and (b) turn away from jk. oof. The situation we are referring to is depicted in Fig. 3(d). Clearly, the vertical line at c cannot turn towards jk, because then we could extend it and make it meet jk. Also, if c were a corner point with ic longer than jk, then we could shift ij to ik, eliminating the Steiner point, and saving on length. q
i
k
(4
(b) Fig. 3. Figures for (a) Proposition 4; (b), (c) Proposition 5; and (d) Proposition 5.
260
(4
Volume 39, Number 5
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PROCESSING
roposition 7. There cannot be more than one corner vertex with the same x or y coordinates. roof. If the above case occurs, it is apparent that one of the corner points can be eliminated by the shifting operation which makes it coincide with the other. i7 [6]. No Steiner point can be adjacent to more than two Steiner points. 3.2. The algorithm As mentioned earlier, the proposed algorithm is essentially a modification of the O(n log IZ) algorithm suggested by Hwang [7] which itself is an extension of the O(n2) heuristic of Lee, Bose and Hwang [9]. We incorporate the above enumerated reduction procedures in the Hwang’s algorithm, making sure that the enumeration scheme never takes more than O(n log n) time and the output tree is not longer than the input rectilinear minimal spanning tree. We assume that a rectilinear minimal spanning tree over the set A is available. We use the 0( n log n) algorithm suggested in [8] for this purpose. We denote this tree by T and proceed as detailed below: Step 1: Given a rectilinear minimal spanning tree T, relabel its vertices as follows: Select the
LETTERS
13 September 1991
shortest edge in T, say (i, j). Select the second shortest edge tn cident on either i or j. Let (i, k ) be such an edge. Then relabel vertex j as 1, vertex i as 2 and vertex k as 3. Recursively scan the RMST in a depth-first manner, each time selecting the current shortest edge of a not yet re’iabcl’led vertex. Vertices are relabelled 4, 5,. . . , n in the same order as they are scanned. Step 2: Construct a minimal rectilinear Steiner tree on the three points 1, 2 and 3. We make use of the fact that the Steiner point of a set of three points is located at the median of these three points. Step 3: The tree is enlarged by sequentially adding vertices 4, 5 and so on. Let us define p, to be a point such that [p,, i] is in the given RMST, and pi is labelled before. Let us also identifv two vertices s and t such that s is a vertex of degree 2 2, and is adjacent to a certain p, as defined above; and t is a vertex adjacent to s. Given that the ith point has already been included in the tree, the (i + 1)th point is added by constructing a minimal Steiner tree on the three points i + 1, s and t. This tree then replaces the edge (s, t ). In choosing the vertices to be included, we apply the above enumerated reduction procedures so that no vertex that violates them is included. The labeling procedure of Step 1 ensures that the length of the output tree never exceeds the input RMST. Each vertex that is added to the tree is also checked for possible violations of the given rules. Thus the
pm,
... ..
c I.....
. .
.
.
.
.
mm=...
F
Fig. 4. (a) Rectilinear tree, length = 4, five Steiner points. (b) Reduced rectilinear Steiner tree, length = 14. one Steiner point, two corner points. The squares are the Steiner poin!s and the circles are the comer pints. 261
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INFORMATION
39. Number 5
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13 September 1991
Table 1 Performance of the Steiner tree reduction pro&we
sub-optimal tree is output the nodes in the given set.
upon inclu&on of al
case WCobtained a ts a
iscussio
We present in this section some results of a preliminary implementation of the algori ed in C on VAX II algorithm :xras ce evaluation, it w ease of perfoduced by passing horizontal and ough all given poi division on the gn this assumption only simplifies ev not in any way hinder the gene
run on examples with example, we randomly chose a set and constructed the rectilinear Stei
eferences 111A. Bs!akris and N.R. Patek Problem reduction methods and a generation algorithm for the Steiner network problem. Neruv& 17 (1987) 65-85. [2] M.R. Garey and D.S. Johnson, The rectilinear Steiner lete. SIAM J. Appi. Math. 32 (1977) 826-834. anan, Net wiring for large scale integrated circuits. IBM Res. Kept. RC 1375. 1965. [4] M. Hanan, On Steine problem with rectilinear distance. SIAM J. Appl. Math. (1966) 255-265. [5] C.-P. Hsu, Minimllm ___...via topoiogical routing. IEEE CA D-ICAS 2 (1983) 235-24.6.
Trans.
[6] F.K. Hwang, On Steiner minimal trees with rectilinear distance, SIAM J. Appl. Math. 30 (1976) 104-114. 262
Volume 39, Number S
INFORMATION
[7] F.K. Hwang, An O(n log n) algorithm for suboptimal rectilinear Steiner trees, IEEE Trans. Circuits and Systems (1979) 75-77. [8) F.K. Hwang, An O(n log n) algorithm for rectilinear minimal spanning trees, J. ACM 26 (1979) 177-182. 9) J.H. Lee, N.K. Bose and F.K. Hwang, Use of Steiner’s problem in suboptimal routing in rectilinear metric, IEEE Trans. Circuits and Systems 23 (1976) 470-476.
PROCESSING
LETTERS
13 September 1991
[lo] M. Sarrafzadeh and D.T. Lee, A r.ew approach to top logical via minimisation, IEEE Trans. CAD-KCAS 890-900. [ll] P. Winter, Steiner problem in networks: A survey, ‘Vetworks 17 (1987) 129-167.
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