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An investigation of the interface state density in metal-silicon nitride-silicon structures
detected and 90% of all failures be isolated to one pluggablc assembly. The procedures defined in this paper were employed and contributed significantly to the achievement of these requirements. Cost effective semiconductor memory testing R. W. STEVENS andJ. R. BRAILSFORD
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Pubbl. 178, 82. The computer industry has been quick to exploit the availability of LSI memories; magnetic core storage now only being used where nonvolatility is significant. This revolution has brought a major testing problem to those using semiconductor memories in volume. The introduction, at the beginning of this decade, of 1K. P-channel MOS RANIs presented a testing problem to an industry ill-equipped to deal with it. As storage capacities have increased so the techniques used for testing have become more refined; only in this way can our tests remain cost effective. This paper deals with the problems experienced by ICL with LSI RANIs and the evolution of our te~t strategy. Emphasis is placed on functional testing and pattern sensitivities, since it is these areas in which the greater pitfalls exist. The information presented is most applicable to MOS dynamic devices, but is largely relevant to all RAMs. It is hoped to show the importance of test optimisation, but that a general approach to test generation can be made without full circuit design information. The performance of plastlc-encapsulated CMOS microcircuits in a humid environment P. W. PETERSON IEEE Trans. Components, ttybrids Mfg Technology. CHMT-2 (4), 422 (December 1979). The major portion of this investigation is devoted to accelerated testing of plastic CMOS microcircuits under conditions of high humidity. The test results revealed a high failure rate in sharp contrast to the results of a similar investigation performed on plastic TTL ICs. The program also investigates the effects of coating devices with a common PC card conformal coating and the effects of operation at various bias levels. A comparison is made between the results of short term pressure cooker testing and long term moisture bias life testing. The results of testing over 1300 devices, representing the product of five (5) manufacturers are discussed. Findings of the investigation reveal a higher failure rate for plastic CMOS than plastic T r L . Conforming coating proved to be an insignificant moisture deterrent. The results of 15PSIG, 127"C, 48-h testing were obsen'ed to correlate with 85"C, 85% relative humidity (RH), 1000-h results. Also observed was the improved performance of CMOS B series devices in moisture compared to the A series. Removal of moisture from the ambient significantly improved the failure rate indicating that moisture was the prime failure cause. The steady-state distribution of signal charge in charge-coupled devices S. OPALSKI and M. SYRZYCKI Electron TechnoL 12(2), 3 (1979). The paper presents a simultaneous calculation method of surface potential and signal carriers steady-state profiles in surface-channel CCD structure. The results obtained make it possible to calculate the maximum signal charge which can be stored in the structure. Advances in CCD scanners with on-chip signal processing for electronic imaging S. G. CHAMBERLAIN Radio Electron. Engr. 50(5), 249 (May 1980). The paper deals briefly with a few widely-used image signal processing algorithms and discusses how these can be incorporated on the same silicon chip as that of the CCD scanner. Recent work on CCD scanners is reviewed and solid-state scanners which include on-chip signal processing functions are described. Future trends are towards 'smart' scanners; these are scanners with on-chip real-time processing functions, such as analogue-to-digital conversion, thresholding, data compaction, edge enhancement and other real-time image processing functions. Built-in test for complex digital integrated circuits B. KONEMANN, J. MUCHA and G. Z W I E H O F F
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Pubhl. 178, 89. A method for testing the logic function of complex digital integrated circuits is presented. The method is based on built-in test. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g. latches). The feasibility of the proposed method is demonstrated by results from both hardware and logic simulation.
Experimental investigation of mounting thermal resistance of flatpacks on circuit boards T. F. MOVILIS, I. R. JONES and J. M. KALLIS IEEE Trans. Components, tlybrids Mfg Technology. CllMT-2 (4). 512 (December 1979). Thermal tests were performed on radar digital module circuit boards to measure the thermal effect of various size gaps between the circuit board and the flatpack integrated circuit (IC) case anti also the thermal resistance of the circuit board. These ICs are cooled by conduction through the circuit board to an air-cooled heat exchanger. The thermal effect of the gap filled with air, and also filled with an adhesive, was measured. The temperature differences between pairs of locations on the flatpack IC case, particularly between the top and the bottom centre, also were measured. These tests are described; the test results are presented, discussed, and compared with analytical predictions; and conclusions are given. The key conclusions are that the filler is quite effective in lowering the IC junction temperatures and, in fact, has a larger thermal effect than the gap size. For example, filling a 5-mil (1.27x 10-~m) gap reduces the junction temperature by 12°C, whereas reducing the gap from 5 mils (I.27× 10-~m) to (I reduces it by only 3°C. The combined thermal resistance of the gap and the circuit board is a linear function of the gap. Distributed computer network takes charge in IC facility D. P. CLEMENS and G. L. CASTLEMAN
Electronics. 151 (5 June 1980). Computers at the helm of MOS chip production line manage fabrication and testing of wafers, data collection, and generation of test reports. An investigation of the interface state density in metal-silicon nitride-silicon structures J. P. B I G O R G N E , M. FAVRE, G. SALACE andJ. DESPUJOLS Solid-St. Electron. 23, 243 0950). MNS capacitors were submitted to a series of alternating voltage pulses, and measurements were performed at different stages of this cycling. The interface state parameters at the Si-Si:~N4 interface were evaluated using the conductance method; the surface potential ~ was obtained from a measurement of the high-frequency capacitance. Experimental results are explained by the formation, during cycling, of new fast surface states located at the Si-Si:~N~interface. Microcrack detection in silicon crystals with an ultrasonic sonoprobe D. C. GUIDICI Microelectronics Journal 1! (1), 1980. Detecting microcracks in silicon wafers is important because of yield losses which might occur during crystal slicing or thermal processing. Although this paper discusses a non-destructive testing (NDT) method which can be used to detect microcracks in 3-inch diameter silicon crystals, the technique and the following ASTM definitions are also applicable to silicon wafers.. Avalanche injection in MNOS gate controlled diodes P. R U T T E R Solid St. Electron. 23,441 (1980). Avalanche injection into a dielectric due to hot electrons produced by breakdown in a depletion region is investigated in a simplified manner. A closed form solution for the field distribution at breakdown is presented which provides an insight into the injection properties under varying physical conditions. The model presented describes the junction breakdown characteristics of a Metal-Nitride-Oxide-Silicon gated diode. This device is capable of being written and erased into various charge states thus varying the break-down properties of the junction. This is analysed in detail were the major parameters are considered to be (i) junction 'walk-out' distance, (ii) depletion width, (iii) applied junction bias, (iv) applied gate bias. Properties of plasma enhanced CVD silicon nitride: measurements and interpretations K. M. MAR and G. M. SAMUELSON SolidSt. Technol. 137 (April 1980). The measurement techniques and the interpretations of the properties of plasma enhanced CVD silicon nitride are discussed.- These properties include structure (Si-H, N-H, and Si-N), composition (Si/N), physical (uv absorption edge, index of refraction, mechanical stress. and density), and electrical (dielectric, d.c. conductivity and CV). IR 43
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Pubbl. 178, 82. The computer industry has been quick to exploit the availability of LSI memories; magnetic core storage now only being used where nonvolatility is significant. This revolution has brought a major testing problem to those using semiconductor memories in volume. The introduction, at the beginning of this decade, of 1K. P-channel MOS RANIs presented a testing problem to an industry ill-equipped to deal with it. As storage capacities have increased so the techniques used for testing have become more refined; only in this way can our tests remain cost effective. This paper deals with the problems experienced by ICL with LSI RANIs and the evolution of our te~t strategy. Emphasis is placed on functional testing and pattern sensitivities, since it is these areas in which the greater pitfalls exist. The information presented is most applicable to MOS dynamic devices, but is largely relevant to all RAMs. It is hoped to show the importance of test optimisation, but that a general approach to test generation can be made without full circuit design information. The performance of plastlc-encapsulated CMOS microcircuits in a humid environment P. W. PETERSON IEEE Trans. Components, ttybrids Mfg Technology. CHMT-2 (4), 422 (December 1979). The major portion of this investigation is devoted to accelerated testing of plastic CMOS microcircuits under conditions of high humidity. The test results revealed a high failure rate in sharp contrast to the results of a similar investigation performed on plastic TTL ICs. The program also investigates the effects of coating devices with a common PC card conformal coating and the effects of operation at various bias levels. A comparison is made between the results of short term pressure cooker testing and long term moisture bias life testing. The results of testing over 1300 devices, representing the product of five (5) manufacturers are discussed. Findings of the investigation reveal a higher failure rate for plastic CMOS than plastic T r L . Conforming coating proved to be an insignificant moisture deterrent. The results of 15PSIG, 127"C, 48-h testing were obsen'ed to correlate with 85"C, 85% relative humidity (RH), 1000-h results. Also observed was the improved performance of CMOS B series devices in moisture compared to the A series. Removal of moisture from the ambient significantly improved the failure rate indicating that moisture was the prime failure cause. The steady-state distribution of signal charge in charge-coupled devices S. OPALSKI and M. SYRZYCKI Electron TechnoL 12(2), 3 (1979). The paper presents a simultaneous calculation method of surface potential and signal carriers steady-state profiles in surface-channel CCD structure. The results obtained make it possible to calculate the maximum signal charge which can be stored in the structure. Advances in CCD scanners with on-chip signal processing for electronic imaging S. G. CHAMBERLAIN Radio Electron. Engr. 50(5), 249 (May 1980). The paper deals briefly with a few widely-used image signal processing algorithms and discusses how these can be incorporated on the same silicon chip as that of the CCD scanner. Recent work on CCD scanners is reviewed and solid-state scanners which include on-chip signal processing functions are described. Future trends are towards 'smart' scanners; these are scanners with on-chip real-time processing functions, such as analogue-to-digital conversion, thresholding, data compaction, edge enhancement and other real-time image processing functions. Built-in test for complex digital integrated circuits B. KONEMANN, J. MUCHA and G. Z W I E H O F F
Fifth Solid State Circuits Conference- ESSCIRC 79, lEE Pubhl. 178, 89. A method for testing the logic function of complex digital integrated circuits is presented. The method is based on built-in test. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g. latches). The feasibility of the proposed method is demonstrated by results from both hardware and logic simulation.
Experimental investigation of mounting thermal resistance of flatpacks on circuit boards T. F. MOVILIS, I. R. JONES and J. M. KALLIS IEEE Trans. Components, tlybrids Mfg Technology. CllMT-2 (4). 512 (December 1979). Thermal tests were performed on radar digital module circuit boards to measure the thermal effect of various size gaps between the circuit board and the flatpack integrated circuit (IC) case anti also the thermal resistance of the circuit board. These ICs are cooled by conduction through the circuit board to an air-cooled heat exchanger. The thermal effect of the gap filled with air, and also filled with an adhesive, was measured. The temperature differences between pairs of locations on the flatpack IC case, particularly between the top and the bottom centre, also were measured. These tests are described; the test results are presented, discussed, and compared with analytical predictions; and conclusions are given. The key conclusions are that the filler is quite effective in lowering the IC junction temperatures and, in fact, has a larger thermal effect than the gap size. For example, filling a 5-mil (1.27x 10-~m) gap reduces the junction temperature by 12°C, whereas reducing the gap from 5 mils (I.27× 10-~m) to (I reduces it by only 3°C. The combined thermal resistance of the gap and the circuit board is a linear function of the gap. Distributed computer network takes charge in IC facility D. P. CLEMENS and G. L. CASTLEMAN
Electronics. 151 (5 June 1980). Computers at the helm of MOS chip production line manage fabrication and testing of wafers, data collection, and generation of test reports. An investigation of the interface state density in metal-silicon nitride-silicon structures J. P. B I G O R G N E , M. FAVRE, G. SALACE andJ. DESPUJOLS Solid-St. Electron. 23, 243 0950). MNS capacitors were submitted to a series of alternating voltage pulses, and measurements were performed at different stages of this cycling. The interface state parameters at the Si-Si:~N4 interface were evaluated using the conductance method; the surface potential ~ was obtained from a measurement of the high-frequency capacitance. Experimental results are explained by the formation, during cycling, of new fast surface states located at the Si-Si:~N~interface. Microcrack detection in silicon crystals with an ultrasonic sonoprobe D. C. GUIDICI Microelectronics Journal 1! (1), 1980. Detecting microcracks in silicon wafers is important because of yield losses which might occur during crystal slicing or thermal processing. Although this paper discusses a non-destructive testing (NDT) method which can be used to detect microcracks in 3-inch diameter silicon crystals, the technique and the following ASTM definitions are also applicable to silicon wafers.. Avalanche injection in MNOS gate controlled diodes P. R U T T E R Solid St. Electron. 23,441 (1980). Avalanche injection into a dielectric due to hot electrons produced by breakdown in a depletion region is investigated in a simplified manner. A closed form solution for the field distribution at breakdown is presented which provides an insight into the injection properties under varying physical conditions. The model presented describes the junction breakdown characteristics of a Metal-Nitride-Oxide-Silicon gated diode. This device is capable of being written and erased into various charge states thus varying the break-down properties of the junction. This is analysed in detail were the major parameters are considered to be (i) junction 'walk-out' distance, (ii) depletion width, (iii) applied junction bias, (iv) applied gate bias. Properties of plasma enhanced CVD silicon nitride: measurements and interpretations K. M. MAR and G. M. SAMUELSON SolidSt. Technol. 137 (April 1980). The measurement techniques and the interpretations of the properties of plasma enhanced CVD silicon nitride are discussed.- These properties include structure (Si-H, N-H, and Si-N), composition (Si/N), physical (uv absorption edge, index of refraction, mechanical stress. and density), and electrical (dielectric, d.c. conductivity and CV). IR 43