An operational amplifier model for evaluating test strategies at behavioural level

ARTICLE IN PRESS

Microelectronics Journal 38 (2007) 1082–1094 www.elsevier.com/locate/mejo

An operational amplifier model for evaluating test strategies at behavioural level Eduardo Romeroa,b,, Gabriela Perettia, Carlos Marque´sb a

Electronics and Control Research Group, Facultad Regional Villa Marı´a, Universidad Tecnolo´gica Nacional, Avda Universidad 450, 5900 Villa Marı´a, Argentina b Electronics and Instrumentation Development Group, Facultad de Matema´tica, Astronomı´a y Fı´sica, Universidad Nacional de Co´rdoba, Medina Allende y Haya de Torre, 5000 Co´rdoba, Argentina Received 18 May 2006; received in revised form 29 August 2007; accepted 30 August 2007 Available online 10 October 2007

Abstract This paper proposes a new operational amplifier model for evaluating test strategies at behavioural level. Major modifications on a previously reported model for improving its performance and for allowing reliable fault simulations are presented here. The new model presents a set of very appealing characteristics for behavioural-level fault injection and simulation. The matching between the behavioural-level model and a transistor-level one is evaluated for validating the model. We suggest the use of the model early in the design process, when the schematic of the circuit is not available for the test engineer and only the specifications are given. The model is also useful for evaluating different test alternatives for commercial operational amplifiers or standard cells designed by others vendors. The paper addresses two application examples and shows the usefulness of the model for evaluating test strategies when only the specifications of the circuit are available. r 2007 Elsevier Ltd. All rights reserved. Keywords: Behavioural analogue modelling; Operational amplifiers; Fault simulation; Testing

1. Introduction The rapid development of integration technologies has allowed the implementation of analogue and digital functions in mixed-signal integrated circuits. Usually, the analogue sections require a small area, but are hard to test due to the frequently low observability of the internal nodes and the complex nature of the involved signals [1]. This produces an increased impact on the overall cost of the circuits. It is accepted by the test community that the test plan must be considered early in the design cycle for avoiding costly and tedious modifications in later design stages. However, the traditional test evaluations based on structural fault injection are difficult to perform as the circuit schematic is usually not available early in the Corresponding author. Tel.: +54 353 4537500; fax: +54 353 4535498.

E-mail addresses: [email protected] (E. Romero), [email protected] (C. Marque´s). 0026-2692/$ - see front matter r 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2007.08.006

developing process. A similar situation arises (from the test viewpoint) in systems requiring off-the-shelf integrated circuits or standard cells designed by third part vendors. For these cases, the implementation of alternative methods for evaluating and comparing different test strategies becomes necessary. A way for performing these evaluations is to adopt a behavioural-level model for the Circuit under Test (CUT) and a fault model compatible with this abstraction level. By other way, critical applications, such as spatial, military or nuclear, could require in-field periodic testing. These tests are usually oriented to detect deviations in the specifications beyond the acceptable limits imposed by the application. It is well known that circuit parameters exhibit deviations during the operation under chemical, thermal or mechanical stress [2–4]. Ionizing radiation also causes severe changes in the circuit behaviour and a considerable research effort has been devoted to establish the deviations in the specifications versus the severity of the exposition [5,6]. In these cases, the fault mechanisms at transistor level

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are usually unknown or at least are very difficult to establish, preventing traditional test evaluations. However, the variation in the specifications has been determined for a number of commercial circuits. This information can be used with behavioural-level models for evaluating if a given test strategy is able to detect deviations in the circuit specifications that may cause a system failure. In this work, we propose a new behavioural-level operational amplifier (OA) model for evaluating test strategies early in the design process. The model presented here is also useful for the evaluation of test schemes addressing applications based on off-the-shelf components or standard cells. Preliminary results of this research have been presented in [7]. The paper is organized in seven sections. In Section 2, we present a discussion on previous work related to the use of OA behavioural models for fault simulations. In Section 3, we analyse the OA model being the conceptual starting point for the new one discussed in Section 4. The model validation adopting a previously designed CMOS Folded Cascode OA is presented in Section 5. Two application examples illustrate the use of the model for evaluating test strategies in Section 6. Finally, Section 7 concludes the paper.

2. Previous work Several authors propose the use of behavioural-level models for the CUT and a fault model compatible with this abstraction level for evaluating test strategies. Usually, the observed effects of hard faults injected in the schematic are mathematically modelled and included in the behaviourallevel model of the CUT. For implementing these proposals, the schematic of the OA has to be available for generating both the fault model and a convenient CUT model able to support the injection of behavioural faults [8–10]. This becomes the main drawback of this approach because the method is impossible to apply early in the design cycle or when off-the-shelf OAs are used. Additionally, these models are frequently restricted to AC [11] or DC simulations [12], or valid for a few closed-loop configurations [13]. This fact complicates the test generation and evaluation for cases requiring transient analysis or other configurations. The complexity of the OA models required for fault simulations at behavioural level can be considerably reduced if the fault effects are grouped. The author of [14] presents three groups of faults for OAs embedded in sample-and-hold circuits: faults affecting input impedances, differential gain and output impedance. A different approach is proposed by Huang et al. in [15]. They use an OA model described at Laplace transfer-function level and a fault model based on the consideration that faults at structural level will produce deviations in the transferfunction coefficients. The main limitation of the model is its restriction to small signal simulations.

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Structural macromodels [16–18] could be used for injecting faults at behavioural level by means of deviations in the parameters of the model components. The main drawbacks of this approach are that many important characteristics of real OAs are neglected and that there is no straightforward relation between the specifications and model parameters. In [19], Maxim et al. present a model that overcomes the above-appointed drawbacks, but the discussion of this model is postponed to the next section. The authors of [20] propose the use of a simple two-stage structural OA macromodel and a fault model for generating input vectors for a given test scheme. For fault injection, they suggest to introduce single deviations in the OA specifications, previously to the model generation. However, the methodology presents the above-mentioned drawbacks related to the use of macromodels. Additionally, the model has to be recalculated for each injected fault and it cannot be easily simplified if the test engineer needs to model only a subset of the OA characteristics. 3. Model analysis In this section, we analyse the behavioural-level OA model proposed by Maxim et al. [19] because it is the conceptual starting point for the one suggested here. The Maxim’s model is based upon the analogue behavioural modelling (ABM) library available in modern SPICE simulators. A simplified version of this model is depicted in Fig. 1. In this figure, the block SUM adds the effects of the differential gain (ADIFF), the common-mode gain (ACOM), and the positive and negative power supply rejection ratios (PSRR+ and PSRR). The offset voltage (VOFF) is referred to the input. The blocks composed by HDIF-EDIF and HCOMECOM model the effects of the common-mode and differential-mode input impedances. In the same way, HROUT and EROUT model the output impedance. Laplace blocks available in the ABM library allow modelling these impedances in the frequency domain. The SRL block models the slew-rate limitation effects and ESAT take into account the output saturation effects. Other characteristics included in the original model, such as thermal effects and noise, are not shown here in order to obtain clear explanations. This model presents very appealing characteristics for fault injection and simulation at behavioural level. Among others, the model is fully behavioural and includes some real OAs characteristics neglected in other models. By other way, it only needs the OA specifications, which exhibit a straightforward relation with the model parameters. The model topology also allows injecting deviations (faults) in a functional parameter (FP) without the need of reformulating the whole model. Finally, the modularity of the model lets to simplify it in an easy way, if the test engineer is interested only in a subset of characteristics.

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PSRR+ + -

VDD

R+

EDIFF + -

HDIFF

Vi+

SUM

ADIFF

IN1 IN2

IN OUT

OUT

EDIFF + -

R-

IN3 IN4

VOFF

ViHCOM

ECOM + -

ACOM IN+ IN-

OUT+ OUT-

PSRR+ -

VSS

DIFF

+SLEWMAX

INTEG

SRL INPUT

SRL OPUTPUT d/dt

ESAT IN+ IN-

HROUT OUT+ OUT-

EROUT + -

Vout

-SLEWMAX

SRL BLOCK

Fig. 1. Simplified version of Maxim’s OA model.

Voltage (V)

4.0

0

-4.0 0 Vin

50u Vout

100u

150u

200u

250u

300u

Time (sec)

Fig. 2. Output response of the original OA model under saturation condition.

3.1. Detected problems and drawbacks Despite the above-appointed appealing characteristics for fault injection and simulation, the model exhibits the following problems. 3.1.1. DC behaviour The normal operation of the block SRL eliminates the DC signals present at the input of this block because it has a differentiator in the signal path (DIFF in Fig. 1). Consequently, the model does not reproduce the DC behaviour of real OAs. The offset voltage is also not observable at the output. For evidencing these problems, we configure the model as voltage follower obtaining an

offset voltage of 700 nV for grounded input (expected value: 50 mV). For the same configuration, an output voltage of 14 mV is obtained when the input is fixed to 1 V (expected value: 1 V).

3.1.2. Saturation effects Under saturation conditions, the block ESAT limits the output signal and the differential voltage at the model input grows up rapidly. The block ADIFF amplifies this signal, normally by a factor higher than 1000 for general purpose OAs. When this signal is limited at the saturation limits, the output strongly departs from the behaviour of real OAs. In Fig. 2, we show the output of the model under

ARTICLE IN PRESS E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094

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(-260.000m, 2.2798)

Output voltage (v)

2.0

(-256.522m, 1.7149)

0 Model

-2.0 Transistor

-300m

-200m

Transistor

Model

-100m

0

100m

200m

300m

Input voltage (v)

Fig. 3. Output dynamic range for a real OA and for the original model.

saturation conditions. For this evaluation, the OA is configured as inverter with unity gain. 3.1.3. Output dynamic range The output dynamic range of the model is considerably lower than the real OAs, particularly when high output resistance OAs are being modelled. For these cases, when the saturation limits are reached the voltage drop in the output resistance causes this divergence. The problem is depicted in Fig. 3. For this evaluation, the OA is configured as inverter with gain equal to 10. 3.1.4. Input and output impedance networks The differential- and common-mode input impedances and the output impedance are modelled at Laplace transfer-function level. This complicates the model and increments the simulation time. Additionally, this modelling style makes difficult the translation from specifications to model parameters. 4. New behavioural model In order to overcome the above-appointed problems, we propose a set of major changes in the model. As a result, a new behavioural-level OA model, depicted in Fig. 4, is obtained. RCOM1, RCOM2, CCOM1, CCOM2, RDIF and CDIF model the input differential- and common-mode impedances. In this way, the complexity of the original model is reduced. We also solve some convergence problems observed in our experiments with the original model, related to the use of Laplace blocks. The differential-mode signal is obtained from the input voltages by SUB1 and then is processed by ADIFF, which represents the differential-mode frequency response of the OA. ADIFF is implemented using a Laplace block and (for most of the internally compensated OAs) it can be adequately modelled by the following transfer function: ADIFFðsÞ ¼

ADIFF0 ½1 þ s=ð2pf 1 Þ½1 þ s=ð2pf 2 Þ

(1)

In this expression, ADIFF0 is the DC differential gain, f1 is the frequency of the dominant pole, f2 is the frequency of the second pole and s denotes the Laplace variable. The data required for implementing ADIFF are obtained from the manufacturer data sheet (for off-the-shelf integrated circuits), by simulations (if the structural-level model is available) or by means of experimental procedures if necessary. The parameters are easily loaded in the model using the graphical interfaces available in modern SPICE simulators. More complex frequency responses can be reproduced by adding zeroes and high-frequency poles to (1). In order to obtain the common-mode signal, the input voltages are added by SUM1 and then are processed by the ACOM block, which represents the common-mode frequency response. Since SUM1 performs only the addition of the two input voltages, the output signal of this block is divided by two for obtaining the common-mode signal. In our model, this operation is implemented by adjusting the DC gain of ACOM. The common-mode gain transferfunction ACOM(s) can be obtained from the following relation: ACOMðsÞ ¼

ADIFFðsÞ . CMRRðsÞ

(2)

In (2), CMRR(s) is the common-mode rejection ratio transfer function, which can be obtained from the OA data sheet, frequently in the form of Bode plots. From these plots, CMRR(s) can be synthesized in a very straightforward way. Frequently, CMRR(s) can be adequately modelled as a transfer function with a DC gain (CMRR0) and a pole (f3) located at higher frequency than the first pole of ADIFF(s): CMRRðsÞ ¼

CMRR0 . ½1 þ s=ð2pf 3 Þ

(3)

As a consequence, ACOM(s) adopts the following form: ACOMðsÞ ¼

ACOMo ½1 þ ðs=2pf 3 Þ . ½1 þ s=ð2pf 1 Þ½1 þ s=ð2pf 2 Þ

(4)

The effects of differential gain, common-mode gain, positive and negative power supply rejection ratios

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VDD

PSRR+

SUB2 CCOM1

INPUT(+)

VOFFSET

INPUT(-)

CDIF

ADIFF

RCOM1

SUB1

SUM4

SUM2 SUM3

RDIF

TABLE CCOM2

RCOM2

IFP

SUM1 ACOM

VSS

PSRR-

A

B

SUB3

LIMITER SW

D/Dt

D

INTEG

VOUT

ABS

SUM5 C

D/Dt

LIMITER SLEWMAX

INTEG

SRL1

Fig. 4. New behavioural-level OA model.

(PSRR+ and PSRR) are added at the input of the block SRL1. PSRR+ and PSRR are also represented in the frequency domain by using Laplace blocks, employing transfer functions synthesized from the Bode plots reported in the vendor data sheet, obtained by simulations or by experimentation. We propose the use of the block SRL1 for modelling the slew-rate limitation effects. At point A, a DC plus AC signal is observed. The branch composed by the blocks D/Dt (derivative action) and INTEG (integral action) allows obtaining at point B an AC-only signal. The block SUB3 performs the operation SIGNAL (A)SIGNAL (B), obtaining at point D the DC component. The branch composed by the blocks D/Dt, SLEWMAX (LIMITER) and INTEG models the slew-rate limitation effects. An AC-only signal is obtained at point C and SUM5 restores de DC level. The use of the SRL1 block allows reproducing the DC behaviour of real OAs, overcoming the severe problems of the original model. This will be clear in the next section, where we present the model validation.

In order to reproduce the behaviour under saturation conditions, we propose to use the limiter observed at the output of the block SRL1. Nevertheless, the use of this simple block causes the problem already pointed out in this paper (Section 3.1). This drawback has been targeted in [21], but only with a partial solution based on the use of a hyperbolic function. We extensively experimented with this kind of functions and with others presenting smooth characteristics. However, it was not possible to reproduce a right operation under saturation conditions, for all the functions and for our simulation platform (SPICE). This fact motivated the exploration of a more general solution. Our approach for solving this problem is based on the reduction of the differential gain by means of an internal feedback path (IFP). This feedback has to be active only when saturation limits are reached. The non-linear function proposed for implementing IFP is depicted in Fig. 5, where the input to the block (Vin) is taken from the output of SUM5. This function is implemented by means of a table and a multiplier, both available in the ABM library. IFP reduces the differential gain to one when the saturation

ARTICLE IN PRESS E. Romero et al. / Microelectronics Journal 38 (2007) 1082–1094

Vout/vin 1

1

0 Low Sat.

Vin(V) High Sat.

Fig. 5. Non-linear function of IFP.

Table 1 Specifications of the modelled OA circuit Specification

Nominal value

Differential gain (dB) First pole of differential gain (Hz) Second pole of differential gain (MHz) Common mode gain (dB) First pole of common mode gain (Hz) Second pole of common mode gain (MHz) First zero of the common mode gain (kHz) Differential input resistance (GO) Common input resistance (GO) Differential input capacitance (pF) Common input capacitances (pF) Output resistance (kO) Slew rate (V/ms) Offset voltage (input referred) (mV)

80 884 30 38 800 34 5.3 10 10 0.01 0.1 150 10 150

level is reached, and diminishes the effects of the system dynamics under this condition. The modules ABS and SW replace the output impedance network of the original model. When the module of the signal at the output limiter (operation performed by the ABS module) exceeds the saturation limits, the output SW switches on and connects in series its RON resistance; in other case, the series resistance is ROFF. Therefore, the output impedance in normal mode (no saturated) is ROFF. With this output network, we considerably improve the output dynamic range and overcome the problems evidenced by the original model, particularly when high output impedance OAs are modelled.

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For model validation, the responses of transistor and behavioural-level models for different experiments are obtained. For all cases, we superimpose the results for comparative purposes. The frequency responses of differential- and commonmode gain are shown in Figs. 6 and 7, respectively. The common-mode gain has been modelled with a transfer function with one zero and two poles, for adequately reproducing the transistor-level circuit behaviour. The PSRR+ frequency response is depicted in Fig. 8. The observed mismatch could be minimized but have been regarded not relevant for our applications. It should be mentioned at this point that the approximation to the behaviour of a real OA could be improved incrementing the poles and zeroes of the Laplace blocks modelling the behaviours in the frequency domain, but this augments the model complexity and consequently the simulation time. This could be a problem when fault injection and simulation campaigns have to be done for complex circuits. Consequently, the test engineer must adopt a trade-off between the precision of the model responses and the computational cost of behavioural fault simulations. The large-signal response under slew-rate limitation effects is evaluated using 0.7 to 0.7 V step input (Fig. 9). It should be mentioned that the highest mismatch has been obtained for this experiment, but it is considered tolerable. The DC behaviour and the effect of the swing limiter are evident in the DC sweep results depicted in Fig. 10. As can be seen from the figure, the new model overcomes the problems of reduced output dynamic range exhibited by the original model (Fig. 3). The saturation effects for both the transistor-level model and the behavioural one in an inverting configuration (unity gain) are shown in Fig. 11. The severe divergence between the original model and transistor-level one under saturation conditions has been also reduced to a minimum extent. In order to demonstrate the DC response of the model (Fig. 12), we configure the amplifier as unity gain inverter and excite it with a sinusoidal signal with a DC level of 1 V. As can be seen from the simulation results, the new model obtains the expected behaviour and overcomes the limitations of the original model. 6. Application examples

5. Model validation In order to evaluate the matching of the proposed model with a transistor-level one, a previously reported CMOS Folded Cascode OA [22] is adopted. The main specifications of this circuit are shown in Table 1, and are loaded into the behavioural model developed in this work. The main motivations for selecting this OA are its relatively complex frequency response and its high output resistance. These characteristics complicate the behavioural modelling.

As it was mentioned in Section 1, the structural fault injection cannot be implemented when the schematic of the circuit is not available for the test engineer. This situation leads to the adoption of an OA model at an abstraction level different from the structural one, and a compatible fault model. In the following examples, we adopt the OA model presented in this paper and the functional fault modelling (FFM) concept proposed in [20] for performing the evaluations of the addressed test strategies. It should be pointed out that FFM has been reported to the scientific

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Differential gain (dB)

100

50

Transistor 0

Model -50 1.0

100 Transistor

Model

10K

1.0M

100M

Frequency (Hz)

Fig. 6. Differential-mode gain frequency response.

Common-mode gain (dB)

-20

-40

Transistor

-60 Model

-80 10

100 Transistor

1K Model

10K

100K

1.0M

100M

Frequency (Hz)

Fig. 7. Common-mode gain frequency response.

PSRR+ (dB)

80

Transistor 60

Model 40 1.000 Transistor

100.00 Model

10.00K

1.00M

Frequency (Hz)

Fig. 8. Positive PSRR frequency response.

community in the recent past years, and the discussion on the ability of this fault model for taking into account the effects of structural faults is beyond the scope of this paper. The FFM approach defines a functional fault as a deviation in at least one specification of the OA, for instance bandwidth, slew rate and common-mode gain. In

this sense, a faulty instance of an OA has one of its specifications beyond the acceptable limits. For the sake of simplicity, we denominate an OA specification as FP. In the following, we adopt two different approaches for validating the test schemes presented as application examples. In the first one, we formulate an arbitrary fault list to be

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Output voltage (V)

1.0

1089

Transistor

0 Model

-1.0 0 Model

0.2u Transistor

0.4u

0.6u

0.8u

1.0u

Time (sec)

Fig. 9. Step response.

Output voltage (V)

4.0

0 Transistor

Model

-4.0 -1.0

-0.5

0

0.5

1.0

Input voltage (V) Transistor

Model Fig. 10. DC sweep.

Voltage (V)

4.0

Model

0

Transistor

-4.0 0

0.4m Model

Input

0.8m Transistor

1.2m

1.6m

2.0m

Time (sec)

Fig. 11. Behaviour of the new model under saturation conditions.

injected in the OA model, following the procedure suggested in [20]. In this case, the goal is to demonstrate the use of the model and to determine the hard-to-detect faults. In the second one, we relate the deviations in the FPs with the application specification. A deviation in a given FP is considered as a fault

if it produces a shift beyond tolerable limits in at least one of the application specifications. These two different procedures have been adopted in order to give alternative approaches for generating the fault list. A third alternative to these approaches for fault list generation is proposed in [23].

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Voltage (V)

2.0

input

0

output

-2.0 0

0.2m

0.4ms

0.6m

0.8m

1.0m

Time (sec) Fig. 12. Response of the new model configured as unity gain inverter.

C2 1n

R2 100k

N5

R1 1k

N4

C1

N2

-

2n

N3 N1

Vout

+

Fig. 13. Band-pass filter (CUT).

6.1. Using the model for evaluating transient analysis method (TRAM) The model presented in this work is used to evaluate the ability of TRAM for testing a biquadratic filter. This method has been proposed in [24] and it is based on the assumption that a behavioural fault in the filter components will produce deviations in the transient response of the CUT. The test stimuli may be a step, ramp or parabola (regarding the order of the filter transfer function numerator), and the observed parameters are the peak time and the overshoot of the filter output signal. We assume that the ability of TRAM for detecting faults in the passive components of the filter structure is evaluated by means of catastrophic and deviation fault models. The interest here is to determine if the test scheme is able to detect a set of proposed deviations in the FPs of the OA used in the filter. In this way, it is possible to compare different testing alternatives, overcoming the problems derived from the unavailability of the CUT schematic. We chose for comparative purposes the negative feedback biquadratic filter also proposed in [24]. This circuit (Fig. 13) is a band-pass filter tuned in 10.7 kHz when R1 ¼ 1 kO, R2 ¼ 100 kO, C1 ¼ 2 nF and C2 ¼ 1 nF. For

this example, we assume that the OA to be designed later in the development process has to fulfill the specifications depicted in Table 2. The assessment of the behavioural faults (deviations in the FPs) hard to detect by means of TRAM is the main concern in this example. In order to perform this evaluation, we introduce deviations in the model parameters and observe the output signal. A ramp (1000t) was selected as test stimuli to obtain a typical second order transient response. The functional faults to be injected in the OA are obtained from the data summarized in Table 2. In this table, ‘‘x’’ denotes that the faulty FP is obtained doing the product of the nominal FP by the indicated factor. The circuit transient responses for faults in the DC and the first pole of the differential gain are shown in Figs. 14 and 15, respectively, in order to illustrate some of the simulation results obtained in our evaluation. In these figures, the fault-free response and the faulty ones are superimposed for comparative purposes. It is observed that the addressed deviations in the DC differential gain and in the first pole of the differential gain are easily detected using TRAM. By other way, the faults injected in the second pole of the differential gain have to be declared as non-detected because there are no differences between the fault-free and faulty responses. From the simulation results, we preliminary conclude that TRAM presents severe problems for detecting deviations in the parameters related to the common-mode gain frequency response and to the input impedances. Deviations in the second pole of the differential gain are also hard to detect. For all these injected deviations faults, there are almost no differences between the fault-free filter response and the faulty one. 6.2. Using the model for evaluating oscillation-based test (OBT) In the second application example, we address the problem of evaluating an OBT scheme applied to the test of continuous-time nuclear pulse shapers. This kind of

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systems is widely used in the nuclear industry, although the problem of testing them has been recently addressed in [25]. Our interest here is to show the use of the proposed model for evaluating test strategies applied to multiple OAs circuits. We assume, like in the previous example, that the efficiency for detecting catastrophic and deviations faults in the passive components is determined using traditional methods. We adopt as case study a system composed of a differentiator, three integrators and a gain stage (Fig. 16). We use the OPA656 OA for implementing the shaper. The step response of the shaper should approximate a Gaussian shape [26] for optimizing its performance when used in nuclear spectroscopy systems (a common application for

Table 2 Specifications of the OA used in the biquadratic filter and factors used for obtaining the fault list Functional parameter

Nominal value

Factor 1

Factor 2

Differential gain (dB) First pole of differential gain (Hz) Second pole of differential gain (MHz) Common mode gain (dB) First pole of common mode gain (Hz) Second pole of common mode gain (MHz) Differential input resistance (GO) Common input resistance (GO) Differential input capacitance (pF) Common input capacitances (pF) Output resistance (kO) Slew rate (V/ms)

114 10

 0.5  0.1

 0.25  10

10

 0.1

 10

6 10

 10  0.1

 100  10

5

 0.1

 10

10

 0.01

 0.01

10 0.01

 0.01  10

 0.01  100

0.1

 10

 100

1 1

5  0.01

 7.5  0.001

1091

this circuit). This approximation is better if the number of integrators in the circuit increases. For applying OBT, we convert the whole system into an oscillator by adding a non-linear circuit in the feedback loop (Fig. 17). We manipulate only the input and the output for switching the shaper from normal to test mode in order to minimize the level of intrusion in the system. The advantages of the non-linear oscillators have been widely explained in previous work [23,27]. We follow a procedure similar to the one suggested in [23] for designing the oscillator. The OBT scheme could be evaluated by injecting arbitrary deviation faults in the FPs as it was proposed in the previous example. Nevertheless, the negative feedback paths around the OAs produce that relatively wide deviations in the FPs have a minor impact on the shaper performance. We propose a specification-driven fault list generation from the circuit fault-free response. A single deviation in the value of an FP (FFM concept) is considered as a fault if it shifts the shaper response beyond pre-established limits. We define a tolerance band of 5% at both sides of the nominal response (Fig. 18), but this value could be changed depending on the resolution of the overall spectroscopy system. For generating the fault list, we perturb the FPs using the parametric analysis available in SPICE, and select as a fault for the FP under study the value that shifts the shaper step response outside of its specifications. For the sake of simplicity, we report in Table 3 the multiplying factors used for obtaining the faulty FPs. In this table, OA1 to OA5 are the amplifiers observed in Fig. 16. A fault in a given FP is obtained multiplying its nominal value by the factors depicted in this table. As expected, wide deviations in the FPs are required for causing the application go outside of its specification limits. For some FPs, only positive or negative deviations from their nominal values are taken into account. For input resistances, slew rate and second pole of differential gain, only decrements are considered as faults. Similarly, only

Test-mode output voltage (V)

800m

400m

fault-free 0 0

100u

200u Time (sec)

Fig. 14. Faults in the differential gain.

300u

400u

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Test-mode output voltage (V)

800m

fault-free 400m

0 100u

200u Time (sec)

300u

400u

Fig. 15. Faults in the first pole of the differential gain. R2

R1

R6

R9

C2

C1

INPUT

+

-

R4

R3

-

R7

+

OA1

C3

+

OA2

R5

OA3

R8

R11

C4

R10 -

R13 +

+

OUTPUT OA4

R12

R14

OA5 R15

Fig. 16. Three-integrator shaper.

Shaper

+Vref

NL input

Non linear element NL output

NL output

NL Input

-Vref

Fig. 17. (a) Conceptual diagram of OBT implementation. (b) Characteristic of non-linear block.

increments in the common-mode gain and in the input capacitances are considered as faults. Opposite deviations in these FPs present no effects on the shaper performance.

In order to evaluate OBT, the faults to be injected in the OAs are obtained from the data depicted in Table 3. We consider a deviation fault in a given FP as detected when the amplitude and/or frequency of the oscillations departs more than 5% from their fault-free values. The fault simulation results show that OBT is able to detect faults in all the FPs, with the exception of common-mode input resistance in OA3 and OA4. This suggests that OBT could be an attractive option for testing this kind of circuits. By other way, by adopting both the OA model and the FFM concept it is possible to evaluate the test strategy regarding the OA behaviour. This evaluation is traditionally not carried out: it is assumed that the OAs are fault free, and catastrophic and deviation faults are injected only in resistances, capacitors and switches.

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1093

1.2

Step response (sec)

nominal-5%

nominal

nominal+5%

0.8

0.4

0 1.0u

2.0u

3.0u

4.0u

Time (sec)

Fig. 18. Nominal response and tolerance limits of the three-integrator shaper.

Table 3 Multiplication factors used for obtaining the fault list (shaper) Functional parameter

OA1

OA2

OA3

OA4

OA5

Differential gain First pole of differential gain (positive deviation) First pole of differential gain (negative deviation) Second pole of differential gain Common mode gain Slew rate Differential input resistance Differential input capacitance Common input resistance Common input capacitance Offset voltage (positive deviation) Offset voltage (negative deviation)

0.04 10 0.02 0.143 2400 0.1 0.0267 150 1.1e4 600 87 90

0.075 33.33 0.02857 0.05 2500 0.007 0.0266 1900 1.1e4 1.4e4 58 59

0.065 20 0.02 0.033 3000 2.1e3 0.025 1500 1e3 12000 36 40

0.075 20 0.022 0.05 3500 1.15e3 0.04 2000 1.1e4 12000 58 60

0.15 400 0.05 0.025 100 5e3 0.06 100 4e4 500 73 73

7. Conclusions In this work, we present a behavioural-level OA model useful for evaluating test strategies early in the design cycle, when the schematic of the circuit is usually not available for the test engineer. This new model allows considering different alternatives for testing prior schematic or layout generation, avoiding tedious and costly modifications at those levels. Test strategies targeting commercial OAs or standard cells designed by third-part vendors could be also evaluated due to only the specifications are needed for OA modelling. Additionally, it is possible to analyse and compare different alternatives for testing, avoiding the use of structural fault models that require the CUT schematic. The parameters required by the model presented in this paper show a clear relation with the OA specifications, allowing a straightforward translation from functional specifications to model parameters. The model can be easily simplified in order to use only the necessary blocks for processing the test signals and to reduce the computational effort needed for fault simulations in large systems.

The model is validated using a previously designed CMOS OA. The simulation results show that the model presents a good agreement with the transistor-level version of the amplifier. In order to use the model for evaluating test strategies, the concept of FFM is adopted. Fault simulations are easily performed by means of parametric simulations in a SPICE simulator. The two application examples addressed in this work are intended to show the usefulness of the model for evaluating test strategies for single and multiple OAs applications. In our fault simulation experiments, the model showed an excellent stability without convergence problems.

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