An optimized SVPWM switching strategy for three-level NPC VSI and a novel switching strategy for three-level two-quadrant chopper to stabilize the voltage of capacitors

Energy 35 (2010) 4917e4931

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An optimized SVPWM switching strategy for three-level NPC VSI and a novel switching strategy for three-level two-quadrant chopper to stabilize the voltage of capacitors Alizadeh Pahlavani Mohammad Reza a, *, Mohammadpour Hossine Ali b a b

Department of Electrical Engineering, Iran University of Science and Technology (IUST), Tehran, Iran Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208 USA

a r t i c l e i n f o

a b s t r a c t

Article history: Received 22 May 2010 Received in revised form 13 August 2010 Accepted 19 August 2010 Available online 12 October 2010

Voltage source inverter (VSI) can produce single and three-phase (3P) AC voltages from a constant or variable DC voltage. There are many ways to control the VSI output voltage. Each control way produces some harmonics at the VSI output voltage. The space vector pulse width modulation (SVPWM) may be more effective than other modulation methods, e.g. harmonic injection, phase shifting, multi career pulse width modulation, in decreasing the low order harmonics (LOH). Different switching strategies (SSs) of power electronic devices in SVPWM have some specific advantages and disadvantages with regard to one another. In this paper, a comparative study between different SVPWM SSs is carried out by considering some objective functions such as total harmonic distortion (THD), power and switching losses, the ratio of the harmonic components to the fundamental component, distortion factor (DF). It is also shown that by selecting an optimized and appropriate SS for SVPWM, the harmonic orders, which are the multiples of the frequency index (FI), are eliminated. Then, to investigate the impact of variations of the capacitors voltage and switching frequency on power quality criteria, the most appropriate and optimized SS is applied to a 3P three-level (3L) neutral-point-clamped (NPC) VSI to supply a 3P load. This paper also presents a novel and optimized SS and control approach for a 3L two-quadrant (2Q) chopper in NPC VSI superconducting magnetic energy storage (SMES). Using the proposed SS, the voltage of the VSI capacitors in SMES can be independently controlled; also, the minimum power and switching losses - as well as the proper convection - can be achieved using this same strategy. The simulation results indicate that when combined with a proportional-integral (PI) control approach the proposed SS can be easily implemented in the power networks and can balance and stabilize the multi-level VSIs’ capacitor voltage level. The voltage variation of the capacitors in the steady state condition is less than (0.062%) which is 15 times better than the IEEE standard requirement (1%). To investigate the effectiveness and reliability of the proposed approach in stabilizing capacitor voltage, SMES performance using the presented approach is compared with that of SMES when the capacitors of the 3L VSI are replaced with equal and ideal voltage sources. This comparison is carried out from the power quality point of view and it is shown that the proposed SS with a PI controller is highly reliable. Ó 2010 Elsevier Ltd. All rights reserved.

Keywords: Voltage stabilization SVPWM Optimized SS 3L NPC VSI 3L 2Q chopper Power and switching losses

1. Introduction VSIs convert DC sources to regulated frequency/voltage AC sources. One of the main features of VSIs is that they carry out this conversion with low distortion. VSI’s variable AC output voltage is

* Corresponding author. Iran University of Science and Technology (IUST), Heidarkhani St., Narmak, 16844 Tehran, Iran. Tel.: þ98 2123812522, þ98 9123192585; fax: þ98 2177240490. E-mail address: [email protected] (A.P. Mohammad Reza). 0360-5442/$ e see front matter Ó 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.energy.2010.08.033

created from variable DC input by changing VSIs gain. The gain, which is the ratio of the VSI’s AC output voltage to the DC input voltage, is changed using the Pulse Width Modulation (PWM). Among many different PWMs methods, the SVPWM may be more effective in decreasing the THD of the output voltage. Technological developments such as SMES can improve the power quality of the power system and can respond to the everincreasing demand for electrical energy [1e5]. SMES has been used for several years at utility and industrial sites throughout the United States, Japan, Europe, and South Africa to provide both transmission

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A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931 Table 1 Different switching states in 3L NPC VSI.

Fig. 1. The SMES structure.

voltage support and power quality to customers who are vulnerable to fluctuating power quality [6e9]. SMES systems are classified into two groups namely, the VSI and the current source inverter (CSI) SMES [10e12]. The VSI SMES studied in this paper is shown in Fig. 1; as depicted, this type of SMES is composed of a magnetic energy storage coil with various structures [13,14] and power conditioning systems that are also composed of different parts, such as AC/DC filters, a multi-level chopper, a capacitor bank, and a multi-level converter (i.e. an inverter or rectifier). These power conditioning systems are also used in many different sustainable energy systems,

Fig. 2. A. The 3L NPC VSI, B. The power network and the LC Filter.

Ci

Si1

Si2

S0i2

S0i1

1 0 1

1 0 0

1 1 0

0 1 1

0 0 1

such as biofuels, solar power, wind power, wave power, geothermal power, and tidal power [15,16]. The multi-level converter is an interface between the power network and the capacitor bank and controls the electrical energy exchange between them. Also, the multi-level chopper is an interface between the magnetic energy storage coil and the capacitor bank and controls electrical energy exchange between them. To store the electrical energy in the capacitor bank and the magnetic energy storage coil in the range of mega joules, it is necessary to employ the high power rating converters. To overcome the limitations of the current and voltage range of the semiconductors, multi-level converters are used. The advantages of using such converters include reducing voltage on the switches, harmonic order correction, decreasing or eliminating lateral equipment, decreasing switching frequency, decreasing THD, decreasing switching losses, and decreasing the output current ripple. Multi-level converters, on the other hand, have some disadvantages associated with their use such as the complexity of the control systems, increasing the number of power electronic devices, and increasing the asymmetry of the capacitor voltages during charge and discharge [17e21]. However, the trend toward increasing the speed of electronic processors and the steady decrease in the cost of power electronic devices, coupled with the ability to implement advanced modulation methods such as the SVPWM, encourage engineers to ignore the disadvantages of multi-level converters [22e25]. Depending on its application, an SMES device is controlled in two ways [26]: first, the transmitted active and reactive power to the network is controlled using an NPC VSI, and the level of the capacitor voltage is stabilized using a chopper. In the second approach, the NPC VSI controls the transmitted reactive power to the network and also stabilizes the level of the capacitors voltage, and the chopper controls the transmitted active power to the network. It should be noted that if the voltage of the capacitors is stabilized during all switching operations, smaller capacitors can be used in the SMES system resulting in the lower cost of configuration. Also, any imbalance due to the asymmetry in the SMES circuit and its operation can be easily corrected by keeping the voltage of the capacitor at a constant level [26]. The structure of this paper is as follows: In Section 2, the principle operation of SVPWM in 3L NPC VSI is presented. Also, the SSs of SVPWM are presented and studied. In Section 3, the simulation results will be presented showing that utilizing different SSs in SVPWM would provide different behavior to the output voltage from some specific objective function point of view. Comparing these different behaviors can be an appropriate criterion to distinguish the most appropriate and optimized SSs among other strategies. Also, in this section a comparative study between the most optimized SS for the 2L VSI and 3L NPC VSI with different SSs is performed. In Section 4, a novel SS for 3L 2Q chopper is presented. In this SS, several objective functions such as minimizing switching and power losses are satisfied. In Section 5 PI controllers are utilized to determine the real-time duty cycles of the 3L 2Q chopper in different operation modes, and in Section 6 the simulation results are presented.

A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

4919

qaxis V16 (01 − 1)

V23 (−11 − 1)

V22 (11 − 1) Tc

IV V3 (010) Tb V (10 − 1) V2 (110) Ta 15 V17 (−110) V ( −10 − 1) V9 (00 − 1) Tc Vref Tb 10 Tc Tc III II α Ta V0 (000) d axis I Tb T T T V4 (011) V7 (111) a b a V24 (−111) V11 (−100) V14 (−1 − 1 − 1) V21 (1 − 1 − 1) V8 (0 − 1 − 1) V1 (100)

V18 (−101)

V25 ( −1 − 11)

V5 (001) V12 (−1 − 10)

V13 (0 − 10) V6 (101)

V20 (1 − 10)

V26 (1 − 11)

V19 (0 − 11) Fig. 3. The space vector plan.

2. SSs of the 3L NPC VSI Fig. 2 shows a case study in which a 3L NPC VSI supplies the 3P power network. A filter is used between the NPC VSI and the power

Table 2 The SVPWM1.

network to eliminate the high order harmonics; it is noted that some parts of the LOHs are mitigated by applying SVPWM. Different switching states of the 3L NPC VSI are shown in Table 1; 1 and 0 indicate the on/off states of the switches, respectively. As seen in this table, in order to prevent a capacitor leg short circuit, all switches in a leg are never turned on simultaneously.

Vio ¼ Ci Vdc =2

i ¼ a; b; c

(1)

Supposing that the VSI output voltage is balanced and symmetrical:

Vin ¼ Vio  Vno

(2)

Van þ Vbn þ Vcn ¼ 0

(3)

Where Vio and Vin for i ¼ a, b, c are the line voltage to the inverter’s neutral point voltage and the line voltage to load’s neutral point voltage. Then replacing (2) in (3) results:

Vno ¼ ðVao þ Vbo þ Vco Þ=3

(4)

Also, substituting (1) and (4) in (2) gives:

2

3 2 Van 2=3 4 Vbn 5 ¼ 4 1=3 Vcn 1=3

1=3 2=3 1=3

32 3 1=3 Vao 5 4 Vbo 5 1=3 Vco 2=3

(5)

if (wt ¼ 0), Park’s transformation gives:

! V ref ¼ Vd þ jVq ¼

rffiffiffi  2 Van þ aVbn þ a2 Vcn ; a ¼ ej2p=3 3

 ! V  ffiffiffi Ca þ aCb þ a2 Cc V ref ¼ pdc 6

(6)

(7)

Using (7) and the values of (Ca, Cb, Cc) that are given in Table 1, 27 space vectors are obtained; the corresponding space vector plan is shown in Fig. 3 and shows that the vectors V0, V7, and V14 will short circuit the load. In fact, these vectors are zero voltage vectors in the

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Table 3 The SVPWM2.

Table 4 The operation times of the vectors of 4 triangles of the nth sector. Triangles’ number

Ti

I

Ta Tb Tc Ta Tb Tc Ta Tb Tc Ta Tb Tc

II

III

IV

i ¼ a,b,c ¼ Ts p ffiffiffiTb  Tc ¼ 2pffiffiffi 2jVref jTS sinða þ np=3Þ=Vdc ¼ 2 2jVref jTS sinða  ðn  1Þp=3Þ=Vdc ¼ Ts p ffiffiffiTb  Tc ¼ 2pffiffiffi 2jVref jTS sinða þ np=3Þ=Vdc ¼ 2 2jVref jTS sin a=Vdc ¼ Ts  Tb pTffiffiffic ¼ Ts þp 2ffiffiffi 2jVref jTS cosða þ ð1  2nÞp=6Þ=Vdc ¼ Ts  2 2jVref jTS sinða þ np=3Þ=Vdc ¼ Ts p ffiffiffiTb  Tc ¼ 2 2jVrefpjT ffiffiffiS sinða þ np=3Þ=Vdc ¼ Ts þ 2 2jVref jTS sinða  ðn  1Þp=3Þ=Vdc

the large hexagon can be calculated from the vectors V22, V21, and V7,14 as follows:

ZTs

! V ref dt ¼

0

space vector plan; the other space vectors are active vectors. pffiffiffi The active vectors V21 to V26 that have a magnitude of 2Vdc = 6 form a large p hexagon; the active vectors V15 to V20 that have a magnitude ffiffiffi while the active vectors that of Vdc = 2 form a mediumphexagon, ffiffiffi have a magnitude of Vdc = 6 draw a small hexagon in the space vector plan. As seen in Fig. 3, each hexagon is divided into six sectors; moreover, each sector in the large hexagon is divided into four triangles. So there are 24 triangles in the large hexagon. At any ! instant, the vector V ref is located inside one of the 24 triangles. ! Usually, the average value of the output voltage V ref is computed from the linear composition of the vectors of the triangle in which ! is located; therefore, several SSs can be defined to generate V !ref V ref . Depending on the number of space vectors in each sector and ! the operation time of each space vector in generating V ref , these SSs can be presented. In order to minimize THD in the VSI output voltage, it is better to distribute the zero vectors at the beginning, middle, and end of the switching periods in each sector whenever possible. Also, to minimize the switching losses, this distribution should be performed so that the minimum number of displacements in the switching states in each switching period of each sector occurs. In this paper, three SSs are proposed and compared in 3L NPC VSI. ! In the first SS, which is called SVPWM1, V ref is generated by the linear composition of vectors V14, V7, V0 and V21 to V26. For example, ! the average value of the output voltage V ref inside the first sector of

ZT1

! V 21 dt þ

TZ 1 þT2

! V 22 dt þ

! V 7;14 dt

(8)

T1 þT2

T1

0

ZTs

! ! ! Ts V ref ¼ T1 V 21 þ T2 V 22

(9)

The projection of the vectors in (9) on the d, q axis and composing the obtained vectors in each sector of the large hexagon (see in Fig. 3) gives:

T1 ¼

. pffiffiffi !  2Ts  V ref sinða þ np=3Þ Vdc

(10)

pffiffiffi !  2Ts  V ref sinða  ðn  1Þp=3Þ=Vdc (11)   ! 2 ma ¼ j V ref j= pffiffiffiVdc ; T0 ¼ Ts  T2  T1 ; ut ¼ 2pft ¼ a 6 (12) T2 ¼

Where in these equations: ma is the MI, TS is the switching period (the inverse of the switching frequency, fS), f is the frequency of the VSI output voltage, mf ¼ fS/f is FI, and n is the sector number. Note that the operation time of the vectors which are generated by the ! projection of V ref in the ut direction for this SS are T1 and T2, respectively. This SS is given in Table 2. In this SS, the zero vectors are distributed at the beginning, at the middle, and at the end of the switching periods. ! In the second SS, which is called SVPWM2, V ref is generated by the linear composition of vectors V0 to V14. For example, the average ! value of the output voltage V ref inside the first sector of the small hexagon can be calculated from the vectors V1, V2, V8, V9, V0,7,14 as follows:

Z2Ts 0

! V ref dt ¼

Z2T1 0

! V 1;8 dt þ

2TZ 1 þ2T2

! V 2;9 dt þ

2T1

Z2Ts

! V 0;7;14 dt

2T1 þ2T2

(13) ! ! ! 2Ts V ref ¼ 2T1 V 1;8 þ 2T2 V 2;9

(14)

The projection of the vectors in (14) on the d, q axis and composing the obtained vectors in each sector of the small hexagon (see in Fig. 3) gives:

Fig. 4. Operation time calculation of each triangle vector.

pffiffiffi !  T1 ¼ 2 2Ts  V ref sinða þ np=3Þ=Vdc

(15)

A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

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Table 5 The SVPWM3.

pffiffiffi !  T2 ¼ 2 2Ts  V ref sinða  ðn  1Þp=3Þ=Vdc   ! V ffiffiffi ; T0 ¼ Ts  T2  T1 ; ut ¼ 2pft ¼ a ma ¼ j V ref j= pdc 6

(16) (17)

This SS is given in Table 3. As seen in this table, the minimum displacement in switches occurs, and the zero vectors distribution is the same as the pattern given in Table 2. ! In the third SS, which is called SVPWM3, V ref is generated by the linear composition of all 27 vectors. For example, as seen in

4922 Table 5 (continued)

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A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

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Table 6 The SVPWM4.

Fig. 6. The phase and the line voltage THD variation versus MI.

ZTS

! V ref dt ¼

0

ZTa 0

! V a dt þ

TZ a þTb

! V b dt þ

Ta

ZTS

! V c dt

(18)

Ta þTb

! ! ! ! TS V ref ¼ Ta V a þ Tb V b þ Tc V c

(19)

The projection of the vectors in (19) on the deq axis and composing the obtained vectors results in:

!  ! ! !   Ts  V ref cos a ¼ Ta j V a jcos aa þ Tb j V b jcos ab þ Tc j V c jcos ac (20)

! Fig. 4, the average value of the output voltage V ref inside the first sector and the third triangle in the large hexagon can be calculated from the vectors Va, Vb, Vc as follows:

!  ! ! !   Ts  V ref sin a ¼ Ta j V a jsin aa þ Tb j V b jsin ab þ Tc j V c jsin ac (21)   ! 2 ma ¼ j V ref j= pffiffiffiVdc ; Ta þ Tb þ Tc ¼ TS ; 6 ut þ 4inv ¼ 2pft ¼ a (22)

Fig. 5. Fundamental component of the effective phase and line voltage of the VSI output versus MI.

Fig. 7. Power and switching loss variation versus MI.

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Fig. 8. Impact of MI variation on the line and the phase voltage DF.

Where 4inv is the VSI phase. Assuming that the phase, and the ! ! ! ! magnitude of the vectors j V ref j, j V a j; j V b j, and j V c j are known, solving equations (20), (21), and (22) gives Ta, Tb, and Tc. These, which are shown in each triangle in Fig. 3, determine the operation time of the triangle vectors. Note that by knowing the value of ut þ ! 4inv at any time, the number of the space sector in which V ref is located can be determined. The above equations can be extended to all sectors of the large hexagon by changing a to a  ((n  1)p/3) where n ¼ 1,.,6 is the sector number. Table 4 gives the operation times of the vectors of the 4 triangles created in the nth sector. This SS is given in Table 5. As observed in this table, the minimum displacement in switches occurs, but the distribution of the zero vectors is not the same as the previous SSs and it occurs only when it is possible. Note that the operation time of the triangle vectors in this SS is shown inside each triangle as shown in Fig. 3. Also, Caij in this table indicates the switching states in the VSI leg-a at sector i in triangle j. In Table 6, the optimum SS in 2L VSI that is called SVPWM4, which is obtained by eliminating diodes Di ; D0i and continuously connecting the switches Si2 ; S0i1 for i ¼ a, b, c, are given to be compared with aforementioned SSs [10]. In this paper, the SSs in which the switching losses are high or the other similar conditions are occurred are not used.

Fig. 9. Impact of switching frequency variation on the line voltage THD.

Fig. 10. Impact of switching frequency variation on the phase voltage THD.

3. Simulation results and discussion In this section, the simulation results of SSs are presented. Using M-file in MATLAB software, the state equations of the system shown in Fig. 1 were implemented in order to obtain THD and calculate power loss at the upper switch in one leg. The parameters of the studied system used are given in Appendix 1. In the following, the simulation results of the SSs given in Section 2 are presented and compared with each other. Fig. 5 shows the fundamental component of the effective phase and line voltage of the VSI output versus MI. As seen in this figure, the increasing rate of the fundamental component of the VSI output voltage using SVPWM3 and SVPWM4 is linear, and this rate in these SSs is more than the two other SSs (SVPWM1and 2). Fig. 6 shows that for the MIs smaller than 0.4, the minimum THD in the line and phase voltage are obtained when SVPWM3 and SVPWM4 are used, respectively. This is very obvious that if the number of voltage levels is increased when MI is increased, the magnitude of the fundamental component of the output voltage will also be increased. In fact, this is the reason why the THD is decreased as MI is increased. Also, Fig. 6 shows that in both SVPWM2 and SVPWM4, the THD of line voltage is equal. Moreover,

Fig. 11. Impact of switching frequency variation on the power losses.

A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

Fig. 12. Impact of switching frequency variation on the line voltage DF.

4925

Fig. 14. Variations of switching losses versus switching frequency.

from Fig. 6, it is inferred that the THD of phase voltage is equal to the THD of line voltage for the SVPWM1 and SVPWM2, and when the MIs is bigger than 0.6, the phase voltage THD is equal for both SVPWM3 and SVPWM4. From Table 1, it is deduced that when SVPWM1 is used, the 3L VSI is converted to 2L VSI; consequently, among the SSs, the SVPWM1 generates the maximum THD in the VSI output voltage. Fig. 6 shows that the power losses in the SVPWM4 is two times more than the SVPWM1 and SVPWM2, and for the three of them the power losses is approximately independent of the MI. On the other hand, the power loss in the SVPWM3 depends on the MI, and since the conduction times of switches in 3L VSI is lower than 2L VSI, the power loss in SVPWM3 is always lower than in SVPWM4 as seen in Fig. 6. From Fig. 7, it is observed that SVPWM3 has the minimum switching losses for all the MIs, and in the other SSs, switching losses is approximately independent of the MI. Fig. 8 shows that in each SS, the DF of the line and the phase voltage are equal. Also, this figure shows that the minimum DF is obtained when SVPWM4 is used. Moreover, this figure shows that the DF of the line or the phase voltage in all SSs is less than 0.01. Therefore, the DF of voltage has less importance among the other power quality indexes. From

Figs. 9 and 10 it is deduced that the line or the phase voltage THD in all the SSs remains constant by increasing the switching frequency. Also, these figures show that the minimum and the maximum THD are respectively obtained when SVPWM3 and SVPWM1 are used. Fig. 11 shows that switches’ power losses in all the SSs are independent of switching frequency, and the minimum power losses are obtained in the SVPWM1 and the SVPWM2, and the maximum one is obtained by SVPWM4. Comparing Fig. 11 with Fig. 7 shows that the power loss in the SVPWM3 is smaller than the SVPWM4. From Fig. 12, it is deduced that the line voltage DF in all the SSs is decreased by increasing the switching frequency. Also, this figure shows that the damping rate of the line voltage DF in the SVPWM3 is faster and in the SVPWM1 is slower than other SSs. From Fig. 13, it is inferred that the minimum ratio of the line voltage harmonic orders to fundamental component is obtained by the SVPWM3. In other words, the LOH is created in higher frequencies and consequently the size of the inductance of the filter is decreased. In addition, since the number of the line voltage harmonic orders in the SVPWM3 is less than the other SSs, the distortion power losses in this SS will be small. In Fig. 14, the variations of the switching losses in an arbitrary switch in one leg

Fig. 13. Percentage of the line voltage harmonic orders.

Fig. 15. Variations of the line and the phase voltage THD versus switching frequency.

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Fig. 16. Variations of the power losses versus switching frequency.

versus variations of switching frequency are compared for all the SSs. In this figure, the smallest switching loss is obtained by SVPWM3. Also, by increasing the switching frequency, the switching losses are also increased. In practice, the switching losses are reduced by soft switching techniques, and these losses are considered to be as an index to evaluate the efficiency of multi-level VSIs. In the same switching losses for the SSs, the switching frequency of SVPWM3 can be increased up to two times of the other SSs; therefore, assuming the same switching frequency for all the SSs, the energy efficiency using SVPWM3 will be two times more than other SSs confirming the advantage of SVPWM3. From the above discussion it is concluded that SVPWM3 is the most appropriate SS among the other SSs. Thus, this paper concentrates on this SS. In order to select the best and optimum switching frequency and MI, some important criteria such as the power loss, the THD, and the ratio of the harmonic orders to the fundamental component were obtained shown in Figs. 15e17. These figures confirm the results depicted in Figs. 6,7, 9e11, and 14. As seen in these figures, the capacitor’s voltage variation has no impact on these criteria. In Fig. 18, the voltage variation, before and after filtering (the VSI

Fig. 18. The voltage and the current of the VSI and the load.

output voltage and the load voltage, respectively) is shown. This figure also shows that the voltage and the current of the load become completely sinusoidal after 25 ms. Furthermore, in Figs.

Fig. 17. Impact of switching frequency on switching losses.

A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

Fig. 19. The output voltage and the current of VSI in SVPWM1.

19e22, the line and the phase voltage and the VSI output current for the other SSs are shown. These figures show that the most oscillations in the VSI output current occurs by the SVPWM1 and the greatest levels in the line and the phase voltage waveform is obtained by the SVPWM3. 4. A novel SS for the 3L 2Q chopper As was previously discussed, the SMES control methods for stabilizing capacitors voltage depends upon the power networks. In the first control approach, the transmitted active and reactive power to the network is controlled by an NPC VSI, while the capacitors voltage is stabilized using a chopper. This approach is used to investigate the interaction between the SMES and the power networks. This control approach is easily implemented if an optimized and appropriate switching strategy for the chopper is defined; Fig. 23 shows a 3L 2Q chopper that was studied in this work. In Table 7, all possible switching states in the 3L chopper as well as the SMES coil current path are provided. One of the main requirements for the SS of the multi-level choppers is to minimize

Fig. 21. The output voltage and the current of VSI in SVPWM4.

both the switching losses and the frequency in order to eliminate the need for high frequency electronic switches. Moreover, minimization of the power loss is obtained by minimizing the number of on-switches with the minimum on time in each switching period. Therefore, the switching states in which each chopper switching period creates the minimum number of displacements in the switching states are selected as the best states for the SMES coil charge (CM) and discharge (DM) modes. The optimum switching states are highlighted in Table 7; other switching states that do not satisfy the aforementioned conditions were not used. Another requirement in the SS of the multi-level choppers is the independent action of the capacitors voltage controllers. The SS that satisfies the two cited requirements is outlined in Table 8. The CM and DM in Table 8 are obtained from the proper states in Table 7, assuming that the chopper switching period is 2Tch. Note that To and Tu are, respectively, the operation times that the voltage of the upper and lower capacitors are connected to the positive and the negative polarities of the load during the CM and the DM. Also, Tz is the chopper operation time when the load is short circuit; this occurs at both the CM and DM. Hence, the duty cycles of the chopper can be defined as follows:

do ¼ To =2Tch ; du ¼ Tu =2Tch ; To þ Tu þ Tz ¼ 2Tch

Fig. 20. The output voltage and the current of VSI in SVPWM2.

4927

(23)

where do and du indicate, respectively, the time percentage of connecting the upper and the lower capacitor to the load voltage in the chopper switching period, and dz indicates the time percentage in which the load is short circuit. From this equation, it can be seen that do, du, and dz vary within the range [0, 1]. Also, Table 8 shows that in the CM and the DM, do þ du is always less than one, which means that the required time for compensating the capacitor voltage to the reference voltage is less than a single switching period of the chopper. In other words, if do þ du is more than one, the required time for the compensation of the capacitors voltage to the reference voltage will be more than a single switching period of the chopper. In this case, the compensation of the capacitors voltage to the reference voltage should be performed simultaneously. The fast charge and discharge modes (FCM and FDM) have been considered for this case; note that in changing from the FCM to the CM, or from the FDM to the DM and vice versa, the minimum number of switch displacements of each chopper switching period occurs, resulting in a minimum of switching losses presenting an advantage of the proposed SS.

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Fig. 22. The output phase voltage of VSI.

5. 3L 2Q chopper duty cycle controller design In this section, a block diagram for generating the duty cycle of CM and FCM is presented (Fig. 24). To enhance the system dynamic response in balancing the voltage of the capacitors, it is necessary to ensure that the voltages of the capacitors are equal before connecting the VSI to the power network. To achieve this, the voltages of

Table 7 Switching states in a 3L 2Q chopper. Vload

ðSd1 ; Sd2 ; S0d1 ; S0d2 Þ

Current path

Mode

VC1 þ VC2 VC2 0 VC1 eVC1eVC2 eVC2 0 eVC1 0 0 0 0 eVC1 eVC1eVC2 eVC1eVC2 eVC1eVC2 eVC1eVC2

(1111) (0111) (0110) (1110) (0000) (0010) (0110) (0100) (1100) (1101) (1011) (0011) (0101) (1010) (1001) (1000) (0001)

S0d1 ; S0d2 ; Sd1 ; Sd2 S0d1 ; S0d2 ; Dd ; Sd2 S0d1 ; D0d ; Dd ; Sd2 S0d1 ; D0d ; Sd1 ; Sd2 De ; D0e S0d1 ; D0d ; D0e S0d1 ; D0d ; Dd ; Sd2 De,Dd,Sd2 De,Sd1,Sd2 De,Sd1,Sd2 S0d1 ; S0d2 ; D0e S0d1 ; S0d2 ; D0e De,Dd,Sd2 De ; D0e De ; D0e De ; D0e De ; D0e

FCM CM

Table 8 The implemented SS in the 3L 2Q chopper.

Fig. 23. A. The 3L 2Q chopper, B. DC filter and SMES coil.

FDM DM

Unusable

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Fig. 27. The capacitors voltage variation versus MI.

Fig. 24. The chopper duty cycle controller.

inverter to the power network, the PI controllers begin operating and the voltage errors are fed to these controllers. Using the signal holders, the outputs of the PI controllers are sampled every 2Tch period. The signal holders with a 2Tch sampling time are used to avoid abrupt variations in the duty cycles. If the duty cycles vary abruptly, the turn on-off times should be zero, but this is practically impossible. The signal holder outputs are passed through the limiters with [0 1] interval; these limiters can produce both the CM and FCM. With the availability of Tch, do, du, and by using the Embedded MATLAB Functions shown in Fig. 24, the various modes of the chopper (CM, FCM, DM, and FDM) can be determined. Finally using these modes, the corresponding switching strategies are applied to the chopper switches based on Table 8. 6. Simulation results of the SS of the 3L 2Q chopper

Fig. 25. The power network in the islanding operation.

the upper and the lower capacitors are compared with the reference voltage, which is assumed to be 0.5Vdc as seen in Fig. 24. Subsequently, the difference in the voltage is passed through the limiters with [0 0.5] interval. These limiters work so that each capacitor is charged for only 50% of the switching period; in fact, the outputs of these limiters can only produce the CM. After connecting the

In this section, the strategies presented in sections 2 through 4 are simulated using MATLAB software. The power network to which the SMES is connected is shown in Fig. 25 and was modeled using the M-file in MATLAB software. The power network and the SMES parameters are given in Appendix 2. In Fig. 26, the SMES performance using the developed approaches is compared with that of the SMES when the capacitors of the 3L NPC VSI are replaced with equal and ideal voltage sources that can be an

Fig. 26. THD and DF variation of the VSI output line voltage.

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A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

Fig. 28. Variation of the voltage of the capacitors C1 and C2.

ideal battery (SMES with ideal VSI). These comparisons are from the perspective of the THD and the DF of the inverter output line voltage. As seen in this figure, the performance of the SMES using the chopper duty cycle controller is the same as that of the SMES with an ideal VSI. Fig. 27 shows the voltage variation of the capacitors versus the MI; this figure indicates that the proposed schemes are capable of stabilizing the capacitors voltage to the reference voltage (with less than 0.5% error in the worst case). The smallest voltage variation (with 0.0625% error) is obtained when the MI is 0.65, as shown in Fig. 27. This is because PI controllers have been regulated for this MI; in short, the variation of the capacitor voltage depends on both the MI and the parameters of the PI controllers. Therefore, in order to obtain the best results, it is recommended that the parameters of the PI controllers be deregulated for each MI. Fig. 28 shows the voltage variation of the capacitors; the initial voltages of the capacitors C1 and C2 were 9800 [V] and 9500 [V], respectively. As noticed in Fig. 28, the proposed SS properly stabilizes the capacitors voltage before and after connecting the inverter to the power network. In Fig. 28, the voltage variations of the capacitors in the steady state condition, as can be verified in Fig. 27, is less than 6.25 [V] (0.062%). Compared with the values defined in the IEEE standard specifications and obtained in Ref. [13] (i.e. 1%), this value has been reduced approximately 15 times. The parameters of the PI controllers, as seen in Appendix 2, should be independently tuned for the upper and lower capacitors. This is because when using the SVPWM, the upper and the lower capacitors are not discharged at the same rate; consequently, the number of the PI controllers should be equal to that of the level of the inverters, and the parameters of each PI controller should be independently tuned. In fact, using this approach, the voltage of the inverter capacitors can be stabilized even when the power network is asymmetric and unbalanced.

7. Conclusion The selection of the best and the most optimized SS in SVPWM is mandatory in order to prevent from the disadvantages of employing multi-level VSIs. In this paper, the best SS in SVPWM for 3L NPC VSI is presented because this SS [27]:  Minimizes the THD in the line voltage  Has the minimum THD in the phase voltage in 60% of the MI interval

 Creates the minimum number of the harmonic orders in both the line and the phase voltage, resulting in the minimum distortion power losses  Has the minimum ratio of harmonic orders to the fundamental order  Has the minimum switching losses to switching frequency ratio  Has a low dependency of the THD on the high harmonic orders in the high MI.  Reduces the size of the filter inductance (Lf). This is because the order of the LOH increases  Creates the minimum power and switching losses in the 50% and 100% MI interval, respectively  Produces the maximum number of levels in the line or phase voltage  Provides rapid damping of the DF of the line and the phase voltage versus the switching frequency. Because of this rapid damping, DF is independent of the switching frequency  Reduces the transient time for one cycle period to obtain a sinusoidal voltage and load current  The phase and line voltage DF and THD, switching and power losses is independent of the variation of VSI’s capacitor voltage. Then, to meet the power quality requirements, the best SS was applied in the 3L NPC VSI SMES. As a second work, this paper presents a novel and optimized SS and control approach for a 3L 2Q chopper in the 3L NPC VSI SMES. Some advantages of using this SS in this paper include [28]:  Optimizing power quality by implementing a proper SS in SVPWM for VSI SMES  Better stabilization of the capacitors voltage of the VSI SMES than that of the IEEE standard  Implementing the FCM and FDM as opposed to the CM and DM in order to increase the dynamic response time when stabilizing the capacitors voltage of the VSI SMES  Independent control of the capacitors voltage in the VSI SMES for compensating asymmetric and unbalanced loads  Minimizing the switching and power losses, resulting in easy and reliable convection from multi-level converter’s switches  Using the proposed SS, resulting in the power quality becoming equal with the case in which the capacitors of the VSI are replaced with an ideal and equivalent voltage source. This ideal voltage source may be an ideal battery (SMES with ideal VSI)  Effective and highly reliable performance of the presented SS when used with a PI control approach  Compensating capacitors voltage of the VSI SMES prior to connecting the SMES to the power network (stand-by mode). Appendix 1 Specifications of the 3L NPC VSI and ReL load:

IGBT : SEMIKRON; SKM; 50GB123D; Lf ¼ 800 ½mH; Lload ¼ 2 ½mH; Rload Vdc ¼ 400 ½V; f ¼ 50 ½Hz; fs ¼ 3 Cf ¼ 400 ½mF; VFO ¼ 1:1 ½V; PS ¼

RIGBT ¼ 0:75 ½mU ¼ 5 ½U; M ¼ 0:65 ½kHz; 0:05 ½W

Appendix 2 The parameters of the PI controllers:

KPO ¼ 0:1; KIO ¼ 0:1; KPU ¼ 0:04; KIU ¼ 0:03 Specifications of the transmission line:

A.P. Mohammad Reza, M.H. Ali / Energy 35 (2010) 4917e4931

XL1 ¼ 15 ½U; RL1 ¼ 1:5 ½U; XL2 ¼ 15 ½U; RL2 ¼ 1:5 ½U; XL3 ¼ 30 ½U; RL3 ¼ 3 ½U Specifications of the transformers:

XT1 VT1 ST2 RT3

¼ ¼ ¼ ¼

0:1 ½p:u:; RT1 ¼ 0:01 ½p:u:; ST1 ¼ 30 ½MVA; 20=132 ½KV; XT2 ¼ 0:1 ½p:u:; RT2 ¼ 0:01 ½p:u:; 30 ½MVA; VT1 ¼ 132=20 ½KV; XT3 ¼ 0:1 ½p:u:; 0:01 ½p:u:; ST3 ¼ 50 ½MVA; VT3 ¼ 132=13:2 ½KV

Specifications of the ReL loads:

LRL1 VRL1 SRL2 RRL3

¼ ¼ ¼ ¼

2 ½mH; RRL1 ¼ 5 ½U; SRL1 18 ½KV; LRL2 ¼ 0:2 ½mH; 30 ½MVA; VRL2 ¼ 18 ½KV; 0:5 ½U; SRL3 ¼ 50 ½MVA;

¼ 30 ½MVA; RRL2 ¼ 0:5 ½U; LRL3 ¼ 0:2 ½mH; VRL1 ¼ 13:2 ½KV

Specifications of the NPC VSI and the SMES:

IGBT : SEMIKRONSKM; RIGBT ¼ 0:75 ½mU; VFO ¼ 1:1 ½V; PS ¼ 0:05 ½W; Vdc ¼ 20 ½KV; fch ¼ 2 ½KHz; Cf ¼ 400 ½mF Lf ¼ 800 ½mH; Lfdc ¼ 1 ½mH; Rfdc ¼ 20 ½mU; M ¼ 0:65; f ¼ 50 ½Hz; LSMES ¼ 10 ½H; RSMES ¼ 2 ½mU; C2 ¼ 200 ½mF Cfdc ¼ 700 ½mF; rfdc ¼ 2 ½U; fs ¼ 2 ½KHz; C1 ¼ 200 ½mF References [1] Massoud Amin S, ClarkGellings W. “The North American power delivery system: balancing market restructuring and environmental economics with infrastructure security,”. Energy MayeJune 2006;31(6e7):967e99. [2] Xiaoxin Z, Jun Y, Ruihua S, Xiaoyu Y, Yan L, Haiyan T. An overview of power transmission systems in China. Energy 2010;35(11):4302e12. [3] Chao H. Global electricity transformation: the critical need for integrated market design and risk management research. Energy MayeJune 2006;31 (6e7):923e39. [4] Bayod-Rújula AA. Future development of the electricity systems with distributed generation. Energy March 2009;34(3):377e83. [5] Qader MR. Optimal location of advanced static VAR compensator (ASVC) applied to non-linear load model. Energy September 2006;31(12):1761e8. [6] Cambel AB, Koomanoff FA. High-temperature superconductors and CO2 emissions. Energy June 1989;14(6):309e22. [7] Varghese P, Tam K. Structures for superconductive magnetic energy storage. Energy October 1990;15(10):873e84. [8] Alizadeh Pahlavani MR, Mohammadpour HA, Shoulaie A. Voltage stabilization of VSI SMES capacitors and voltage sag compensation by SMES using novel and optimized switching strategies. Energy May. 2010;35:3131e42. Elsevier. [9] Linden Septimus VD. Bulk energy storage potential in the USA, current developments and future prospects. Energy December 2006;31(15):3446e57. [10] Li Hui, Baldwin Thomas L, Luongo Cesar A, Zhang Da. A multilevel power conditioning system for superconductive magnetic energy storage. IEEE Trans Appl Supercond Jun. 2005;15(2). [11] Shi Jing, Tang Yuejin, Ren Li, Li Jingdong, Cheng Shijie. Discretization-based decoupled state-feedback control for current source power conditioning system of SMES. IEEE Trans Power Del Oct. 2008;23(4). [12] Hui Zhang, Jing Ren, Yanru Zhong, Jian Chen. Design and test of controller in power conditioning system for superconducting magnetic energy storage. In: Proc. the 7th International Conference on Power Electronics; Oct. 22-26, 2007/ Exco, Daegu, Korea. [13] Nomura S, Watanabe N, Suzuki C, Ajikawa H, Uyama M, Kajita S, et al. Advanced configuration of superconducting magnetic energy storage. Energy AugusteSeptember 2005;30(11e12):2115e27. [14] Rebut PH. Perspectives on nuclear fusion. Energy October 1993;18(10):1023e31. [15] Boukettaya G, Krichen L, Ouali A. A comparative study of three different sensor less vector control strategies for a Flywheel Energy Storage System. Energy January 2010;35(1):132e9.

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Mohammad Reza Alizadeh Pahlavani was born in Iran in 1974. He received his Ph.D. degree in electrical engineering at the Iran University of Science and Technology (IUST) in 1998, 2002, and 2009, respectively. He is the author of more than fifty journal and conference papers in the field of electromagnetic systems, electrical machines, power electronics, FACTS devices, and pulsed power.

Hossein Ali Mohammadpour was born in Iran in 1982. He received the B.Sc. and M.Sc. degrees from the Iran University of Science and Technology (IUST), Tehran, Iran, in 2006 and 2009, respectively. He is currently a PhD student in the Department of Electrical Engineering, University of South Carolina, Columbia. His current areas of research interests include power systems dynamics and control, power electronics and applications, FACTS devices, and electromagnetic systems.