- Email: [email protected]
An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers
ARTICLE IN PRESS
Microelectronics Journal 37 (2006) 1018–1029 www.elsevier.com/locate/mejo
An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers Bharath Kumar Thandri, Jose Silva-Martinez Department of Electrical Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX 77843, USA Received 11 January 2005; received in revised form 26 December 2005; accepted 15 February 2006 Available online 19 April 2006
Abstract In this paper, feed-forward techniques are revised and used for the design of high-frequency operational transconductance amplifiers (OTA). For the same power consumption and similar transistor dimensions, the two- and three-path folded-cascode OTA’s present both smaller settling error and faster response as compared to the typical folded-cascode topology. Also, a no-capacitor feed-forward (NCFF) compensation which uses a high-frequency pole–zero doublet to obtain high gain, high GBW and a good phase margin is discussed. The settling-time of the NCFF topology can be faster than that of OTA’s with Miller compensation, even if the latter topology uses larger transconductance values. Experimental results for the multi-trajectory OTA’s fabricated in the AMI 0.5 mm CMOS process demonstrate the feasibility of the feed-forward schemes. r 2006 Elsevier Ltd. All rights reserved. Keywords: Operational transconductance amplifiers; Broadband amplifiers; Feed-forward techniques; Phase compensation techniques; Multipath amplifiers; Folded-cascode amplifiers
1. Introduction The increasing need for faster and more accurate IC’s poses challenging design specifications for the amplifiers which are the basic building blocks for many applications such as precise analog filters, A/D and D/A converters. IF switched-capacitor filters and high-resolution data converters with sampling frequencies above 100 MHz require very fast OTAs with settling times below 3–4 ns for good performance [1–24]. It is very difficult to design an amplifier with both high gain and high bandwidth. High gain amplifiers use cascode structures or multi-stage designs with long channel length transistors biased at low current levels. High bandwidth amplifiers use single-stage designs with short channel length transistors biased at high current levels. Since the folded-cascode OTA presents a single parasitic pole and relatively large DC gain, it is commonly used for high-frequency applications [5,7–18]. For such applications, the typical folded-cascode structure presents some Corresponding author. Tel.: +1 979 845 7477; fax: +1 979 845 7167.
E-mail address: [email protected] (J. Silva-Martinez). 0026-2692/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2006.02.003
limitations because P-type cascode transistors determine the parasitic pole if N-drivers are used; the phase margin of the resulting structure is limited. Regulated telescopic structures are becoming more popular due to the power savings, at the expenses of limited signal swing [13–15]. In order to extend the folded cascode frequency bandwidth, several phase compensation schemes have been reported in the literature [8–12]; these techniques are briefly described in the next section. It is shown that multi-path foldedcascode OTA is faster and more accurate than the conventional folded-cascode OTA due to the action of the feed-forward paths. Cascading of individual gain stages gives a high gain amplifier, but each stage introduces a low frequency pole, which produces a negative phase shift and degrades the phase margin. Many phase compensation schemes for multi-stage amplifiers have been reported in literature [6,7,19–24]. All the reported schemes are a variation of the basic Miller compensation scheme for a two-stage amplifier. The dominant pole is pushed to lower frequencies due to Miller effect, resulting in lower bandwidth structures. Also, a right half-plane (RHP) zero is created; hence a nulling resistor is usually used to cancel its effects. Other
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
reported compensation schemes use the positive phase shift of a left half-plane (LHP) zero created by a feed-forward path to improve amplifier’s phase response [22,23]. The NCFF compensation scheme employs a feed-forward path to create LHP zeros, but does not use any miller capacitor [29]. The dominant pole is not pushed to lower frequencies and results in a higher gain-bandwidth product with a fast step response. The theoretical aspects of feed-forward techniques are discussed in Section 2. Section 3 deals with foldedcascode OTAs with feed-forward paths. High gain twostage amplifiers without Miller compensation are considered in Section 4; it is shown that the NCFF technique is robust even if the integrating and load capacitors are varied in a very large fashion. Section 5 describes the circuit simulation and experimental results; the conclusions are drawn in the last section. 2. Settling-time in presence of a pole–zero pair In this section, the speed of a switched-capacitor amplifier in presence of a pole–zero pair is considered. A macromodel of the typical capacitive amplifier used in switched-capacitor circuits is shown in Fig. 1a. By using conventional circuit analysis techniques, the small signal transfer function can be calculated and is given by ! ! C1 2 1 sC v0 ðsÞ gm C2 ffi , (1) 1 þC 3 ÞÞ vi ðsÞ 1 þ bA1 V 1 þ sðC 4 þbðC bg m
where AV ¼ gm =g0 and b ¼ C 2 =ðC 1 þ C 2 þ C 3 Þ are the amplifier open-loop DC gain and the feedback factor, respectively. A typical open- and closed-loop magnitude C2 C1 vin
vx
C3
vo gmvx
g0
1019
response is depicted in Fig. 1b. The ideal closed-loop amplifier gain is given by C1/C2; it can be noticed in (1) that when the steady state is reached, the error in the final value is determined by the factor 1/(bAV). The closed-loop bandwidth is determined by the RHP zero and parasitic pole. The location of the pole is given by oPeff ¼
bgm C4 þ
C 2 ðC 1 þC 3 Þ C 1 þC 2 þC 3
¼
bgm bg ¼ m, C 4 þ bðC 1 þ C 3 Þ CL
(2)
where CL ( ¼ C4+b(C1+C3)) is the effective loading capacitor. It is important to reduce the parasitic capacitor C3 to increase b, especially for high frequency applications. The typical step response of the underdamped capacitive amplifier is shown in Fig. 2. It consists of two phases, initial slew phase (assumed to be linear) and a non-linear settling to a final value. Single-stage OTA slew-rate (SR) is determined by the amount of current that can be delivered or extracted from the output and the effective load capacitor (SR ¼ I/CL); usually class AB amplifiers increase the SR [2]. The nonlinear phase is determined by both the effective pole’s frequency oPeff and phase margin, and in many practical low-voltage cases dominates the overall settling time. If the slew-rate phase and the RHP zero are ignored, the closed-loop pulse response of the amplifier is given by the following equation: ! 1 eoPeff t vo ðtÞ ¼ vo ðt0 Þ (3) avi ðtÞ, 1 þ bA1 V where a ¼ C 1 =C 2 is the ideal amplifier’s gain. A high performance amplifier should have high oPeff for fast settling and high DC gain AV for accurate final value. The analysis of the amplifier impulse response in the presence of a pole–zero doublet is more complex; in [25–27] it was shown that the presence of low-frequency pole–zero pairs may generate slow components that reduces significantly the amplifier’s speed; this is not the case if high-frequency pole–zero doublets are present. In order to consider the effects of high-frequency pole–zero pairs, the overall open-loop transconductance of the
C4
(a)
-vo Open-loop gain
gmr0
GBW limitation Vin
C1/C2
(b)
DC-gain limitation
Closed-loop gain
1/r0CL ω
ωeff Slew rate
Fig. 1. Typical OTA-based capacitor amplifier: (a) schematic and (b) typical open- and closed-loop magnitude response.
Fig. 2. Step response of a unity gain amplifier with enough phase margin.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1020
amplifier can be simplified as ! 1 þ osZ G m ðsÞ ¼ g . 1 þ osP m
(4)
1
1 þ bA1 V
,
ð5Þ
where oPeff ð¼ bgm C L Þ is defined by Eq. (2). It can be easily found that the closed-loop poles are real if the following condition is satisfied: qffiffiffiffiffiffiffi oPeff oP
þ g0o=CP L 1 þ ooPeff Z
1
hðtÞ ¼
If the right-hand side zero gm/C2 is ignored, using Eqs. (1) and (4), the closed-loop transfer function is obtained as 0 1 1 þ osZ v0 ðsÞ A ffi @ 1 1 vi ðsÞ s2 1 þ o1Z þ oPeff þ bgg0oP s þ o1P oPeff m ! C C2
feedback factor is present. The closed-loop amplifier’s impulse response (assuming that oP1 aoP2 ) is given by ! C
o0:5x.
(6)
Due to the presence of the zero and the finite OTA output resistance, the poles might be real even if oP ooPeff . According to Eq. (5), the closed-loop poles are located at g0 1 oP 1 þ ooPeff þ o C Z L P oP1;2 ffi 2 0 1 vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u oPeff u B C oP B 1 u1 4 ð7Þ 2 C t @ A g0 1 1 þ ooPeff þ C L oP Z For real poles, both poles are located above and below to ðoP ð1 þ oPeff =oZ Þ þ g0 =C L Þ=2, respectively. If the poles are complex conjugate, the real part increases above oP due to the effect of both zero and OTA output resistance. Also, both zero and amplifier output resistance reduces the imaginary part of the poles. Fig. 3 shows the typical root locus of a two-pole and 1 zero system. In both cases, the lowest frequency pole is close to the frequency of the zero if enough feedback is used. A common case for the feedforward amplifiers to be discussed in the following sections is shown in Fig. 4; it corresponds to the root-locus shown in Fig. 3a. Both open- and closed-loop gains are depicted. Notice in this figure that closed-loop pole–zero doublet appears close to the open-loop zero’s frequency if enough
C2
1 þ bA1 V
ðoP1 oP2 ÞððoP1 oZ Þ eoP1 t þ ðoZ oP2 Þ eoP2 t Þ . ðoP1 oP2 ÞoZ
ð8Þ Slow output components are avoided if both closed-loop poles oP1 and oP2 are placed at high frequencies; this however is possible if and only if the zero is located at high frequencies. An important observation here is that if the dominant pole is close to the location of the zero, its coefficient (proportional to oP1 oZ ) is reduced then reducing the effect of possible slow components. 3. Feed-forward techniques for folded-cascode OTAs The typical folded-cascode OTA is shown in Fig. 5a [7]; its small-signal transconductance gain is approximately given by the following expression: gm1 Gm ffi , (9) 1 þ s gC P mP
where gm1 is the small-signal transconductance of M1, and CP is the capacitance associated with the source of MP. The transconductance of the cascode transistors (P-transistors) and the equivalent parasitic capacitor CP at that node determine the open-loop pole’s frequency. For wide-band
Open-Loop Gain
Closed-Loop Gain
C1 C2
ωz ωp2 ωp1 ω Fig. 4. Open- and closed-loop transfer function of a second-order system in presence of a zero. The zero is located after the open-loop poles.
Im
Im
S-plane
X ωz ωp2
(a)
S-plane
X ωp1
Re
X ωp2
ωz
X ωp1
Re
(b)
Fig. 3. Typical root locus for a system with two poles and 1 zero: (a) zero is located at high frequencies; and (b) zero located between the poles. In both cases the dominant pole is terminated by the zero.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
applications, large unity gain frequency is needed, therefore the frequency of the parasitic pole oP ( ¼ gmP/CP) must be placed at very high frequencies. If we consider the same gate dimensions and same bias current for transistors M1 and MP then gm14gmP because the mobility of the N-transistors is higher than the mobility of the P-transistors (three times larger for the technology used). If second-order effects such as mobility degradation, it can be found that sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi gmP 1 2mP 1 oP ¼ (10) ffi I B. Y C OX W P L3P CP In this expression, WP and LP are the width and length of the gate of MP, respectively, and IB is the transistor bias current. COX and mP are the oxide capacitance and the mobility of the carriers in the channel, respectively. The parameter Y is a result of the parasitic capacitors at the cascode node, and can be expressed as P Capacitors at source of MP Y¼ 41, (11) C GSP where CGSP is the gate-source capacitance of MP; for practical circuits 2:54Y41. In accordance with Eqs. (10) and (11), a large Y results in a low frequency nondominant pole; hence it is desirable to reduce as much as possible the drain and source areas of critical transistors. Increasing the bias current increases the frequency of the parasitic poles; unfortunately, the DC gain reduces and the power consumption increases. Limiting the width of the cascode transistor increases the frequency of the parasitic pole but this benefit is limited because the saturation voltage must be maintained within the limits dictated by the supply voltages and signal swing, mobility degradation due to vertical electrical field become more critical in that case as well. On the other hand, a reduction in the length of the cascode transistors reduces VDSAT and increases oP; the drawback is the reduction of the OTA dc gain, and transversal electric field may reduce the effective mobility of the carriers. The frequency of the parasitic pole can be increased by a factor O3 if the dual of the circuit shown in Fig. 5a is employed; the N- and P-type transistors are replaced by P- and N-type transistors, respectively. The drawback is that the overall amplifier’s transconductance is reduced due to the reduced mobility of the carriers in the P-drivers. The ideal OTA should use N-type transistors for both differential pair and cascodes, such that their higher mobility increase both the small signal transconductance and phase margin. This is the major advantage of the telescopic structure [13,14] but unfortunately its output swing is limited, especially for lowvoltage applications and if low VT transistors are not available. To overcome some of these tradeoffs, a number of feedforward compensation techniques have been reported
1021
[5,8–12]. The technique proposed in [9] uses RC networks connected to the gate of the cascode transistors, hence a zero is introduced such that the parasitic pole is partially compensated. In the technique proposed in Ref. [10], the low-frequency signal flows throughout the P-type cascode transistors and, by using RC networks, the highfrequency signal flow throughout the N-type cascode transistors. Due to the higher mobility of the N-transistors, better performances can theoretically be achieved. The additional networks increase the capacitance of the parasitic nodes reducing the frequency of the poles and additional silicon area is needed; a low-frequency pole–zero may increase amplifier’s settling time. In Ref. [11], the gate of the cascode transistor is directly connected to the input signals; by using that feed-forward scheme, further improvements in the OTA phase margin are obtained due to the presence of a high frequency zero. A major drawback of this technique is that the gate-drain capacitors of the cascode transistors affect the precision of the system, especially for switched-capacitor circuits. This drawback has been partially solved by using cross-coupled capacitors [12]. Complementary differential pairs have been used for long time for the design of rail to rail amplifiers [16]. They can also be used for fast amplifiers [17], where all cascode transistors can be exploited as shown in Fig. 5b. It can be shown that the small-signal transconductance of the composite OTA is given by g C gm2 þgm1 g mP CN mN P 1 þ s gC P gm1 þgm2 mP ðgm1 þ gm2 Þ, Gm ðsÞ ffi (12) 1 þ s gC P 1 þ s gC N mP
mN
where CP and CN are the parasitic capacitors lumped to the source of transistors MP and MN, respectively. The overall current consumption is 4*IB, same as the folded-cascode OTA previously discussed. The low-frequency small-signal transconductance is given by gm1+gm2. For same overall current and same input capacitance, its small signal transconductance is around 15% less than the one for the typical folded-cascode OTA. For same transconductance and same power, the width of the drivers must be scaled up by 30%; the input capacitance increases by the same factor, this is a major drawback of this topology. The slew-rate, on the other hand, is 33% higher because the sourced/sinked current can be as high as (4/3)IB. Since the P-transistors at the output stage are handling lesser dc current their dimensions can be relaxed, then the parasitic poles can be placed at higher frequencies. From Fig. 5b, the pole lumped at the source of MP is located at lower frequency than this at the source of MN; the phantom zero lies in between. Since the poles are lumped to the cascode nodes and the zero are located at high frequencies, the settling time is not degraded according to the discussion of the previous section. The current-mirror cascode OTA shown in Fig. 6a has a non-dominant pole at gate of M6 in addition to the poles
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1022
dc gain. It should be pointed out that if the phase margin is enough, this structure may settle faster than the foldedcascode OTA because of its enhanced SR and smaller input capacitance (larger b). A three-path OTA built by the combination of the three different OTAs is depicted in Fig. 6b [18]. A folded-cascode OTA is implemented due to the action of M1, M2 and M3, and a current-mirror cascode OTA is composed by transistors M1–M3 and M6. Also, a current-mirror foldedcascode OTA is embedded due to M1, M4, M6 and M7. The OTA input consists of a split differential pair; half of the ac current generated by the input stage is injected to the source of the N-type cascode transistors, providing a fast path for the current. The other part of the current is delivered to the current mirrors. M6 is the basic transistor of the current mirror: one of its copies, M2, is mirrored to the output stage with a gain of N. M7 provides a current gain factor M. The OTA’s dominant pole is determined by the equivalent resistor and capacitor at the OTA output, while the two non-dominant poles are lumped to the cascode transistors M3 and M4, and the gate of M6, respectively. The small-signal transconductance is given as follows:
(a)
Gm ¼
þ s2 ð1þMþN1 ÞoN2 oP1 þ o1N2 þ 1þN oP1 1 þ osN1 1 þ osN2 1 þ osP1
1 1þMþN
M oN1
ðð1 þ M þ NÞgm1 Þ,
(b) Fig. 5. (a) Typical folded-cascode OTA and (b) folded-cascode OTA using complementary differential pairs.
of the cascode transistor. The overall small signal transconductance is given as Gm ¼
Ngm1 1 þ osN1 1 þ osN2
(13)
and oN1 ffi
1þs
gm6 ; C GS6 ð1 þ NÞ
oN2 ffi
gm3 , C GS3 þ C SB3
(14)
where gm3(6) is the transconductance of transistor M3 (M6), and N ¼ gm2/gm6. The current-mirror cascode OTA suffers from a similar limitation as the standard folded-cascode OTA; during negative slewing, only half of the drain current of M2 is employed in discharging the load capacitance because the dc current provided by M5 cancels the other half. However, a larger fraction of the overall current used can be transferred to the load if N41. With a current gain greater than 1 in the current mirror, the size of the input transistors can be reduced for same GBW as the folded-cascode OTA. Although this decreases the input capacitance, the parasitic capacitance at the gate of M6 increases, which pushes the non-dominant pole to lower frequencies. For same power consumption, N41 increases the current levels at the output stage, lowering the OTA’s
gm3 ; C GS3 þ C SB3 gm4 ffi . C GS4 þ C SB4
oN1 ffi oP1
oN2 ffi
ð15Þ gm6 , C GS6 ð1 þ M þ N Þ ð16Þ
oN2 is the most important non-dominant pole and limits the frequency response of the overall amplifier. Transistors M2, M6 and M7 must be optimized for maximum frequency response. Since the frequency of one of the zeros is below the frequency of oN1 and oP1, in an aggressive design oN2 can be selected close to the OTA’s unity gain frequency. As compared with the regular foldedcascode OTA, oN2 is below the frequency of the nondominant pole of the folded-cascode structure; it can be shown that for same VDSAT and same L, the ratio of the non-dominant pole of the two strctures, onon-dominant F-C/ onon-dominant-3-path, is roughly 2/(1+M+N). The three-path OTA has smaller input transistor sizes, leading to reduced input capacitances; as a result, its closed-loop feedback factor increases and the closed-loop response is faster if the phase margin is good enough. For slew, the three-path OTA output current is a greater portion of the total current, as all transistors except M5 adjust dynamically their currents during slewing. On the other hand, this topology is a bit noisier than the folded-cascode OTA and the one using the complementary differential pairs due to the smaller transconductance of the input stage. This is, however, not critical for many SC applications wherein the
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1023
(a)
(b) Fig. 6. (a) Two-current mirror OTA with cascode output stage and (b) three-path operational transconductance amplifier.
most important noise contributions are due to the switch resistance. The four OTAs discussed in this section were compared in a SC fully differential amplifier with input, feedback and loading capacitors of 1 pF each. The OTAs were designed for the same transconductance, same current consumption and same output voltage swing. The three-path OTA was designed with N ¼ 4 and M ¼ 1; for the current mirror cascode OTA we used a current mirror factor of N ¼ 4. The pulse response for these topologies is shown in Fig. 7. Whereas the other OTAs use smaller fraction of the total bias current during the slewing phase, the three-path OTA outperforms the other topologies in this aspect. Although the multi-path OTAs suffer from relatively poor phase margin its settling time is comparable with other topologies. The multiple-path designs achieve a substantial
improvement in both SR and accuracy as compared with the regular folded-cascode OTA. The three-path design achieves the best settling accuracy (settling erroro0.42%). This study suggests that the simple current-mirror cascode OTA, usually not preferred for high-speed applications because of poor phase margin, performs better than the standard folded-cascode OTA. The results are summarized in Table 1. 4. Feed-forward scheme for multi-stage OTAs with no Miller capacitors Amplifiers with cascaded gain stages are very popular for switched-capacitor applications as well [6,19–24]. Several compensation schemes have been reported in literature for multi-stage amplifiers [22,23]; two of them
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1024
0.6 3-path Current mirror 0.4
Complementary
Output voltage (V)
Folded-cascode 0.2
0.505 Current-mirror 0.500
0.0
3-path
0.495 Complementary
-0.2 0.490
-0.4
Folded-cascode 0.485 4
5
6
7
-0.6 0
1
2
3 4 Time (nsecs)
5
6
7
Fig. 7. OTAs ransient response for a differential input step of 500 mV. The pulse is applied at t ¼ 0:25 ns.
Table 1 Comparison of simulation results for four different OTAs Parameter
Folded-cascode
Current-mirror cascade
Complementary diff pairs
Three-path OTA
SR (V/ms) DC gain (dB) Ts (1%) (ns) Ts (0.1%) (ns) Settling error (%) Input noise (109 V/Hz1/2)
392 55.9 4.2 5.3 1.15 1.67
496 55.9 3.7 4.9 0.75 2.4
473 60.6 3.7 4.7 0.95 1.73
555 60.4 3.6 4.2 0.42 2.43
The OTA small signal transconductance is around 4.2 mS for all structures
Cm1 Cm2 -1 gm2
gm1
v0
gm2
vi (a)
Cm1 Cm2 -1 gm1
gm2
gm3
v0
vi
gm4 (b) Fig. 8. Three-stage amplifiers with: (a) nested Miller compensation, and (b) nested Miller compensation with a feed-forward path.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
are shown in Fig. 8. The inverting amplifiers are not needed if differential stages are used. The DC gain for these structures is given by the multiplication of the three-gain stages; hence dc gains of 90–100 dB can easily be achieved. Due to the three high impedance nodes, double miller compensation is required for proper phase margin. The multi-path Miller structure shown in Fig. 8b incorporates a feed-forward path (gm4); this trajectory improves the high frequency response of the structure canceling the righthand zero due to the miller capacitors, but still double miller compensation is needed. The classic two-stage miller compensation scheme is shown in Fig. 9. The open-loop dominant pole, opd ¼ g01 =AV2 C m , is pushed to lower frequency because of the increase in the effective capacitance caused by the compensation capacitor (Cm) and the gain of the second stage. This decreases the open-loop unity gain frequency ou ðgm1 =C m Þ and results in slower settling time. The non-dominant pole is mainly given by gm2 =ðC 01 þ C 02 Þ; unfortunately the load capacitor C02 depends on the application and might be large, hence the speed of the system is limited. For good stability, the condition gm2 =ðC 01 þ C 02 Þ4gm1 =C m must be satisfied; unfortunately high-frequency SC circuits may require large load capacitors that force us to use large gm2 further increasing the power consumption and parasitic capacitances. RHP zero at oZ ¼ gm2 =C m is generated and a nulling resistor must be used to compensate this effect. In some other circuits such as that shown in Fig. 8b a feedforward path (gm4) is used for this purpose. Feed-forward compensation techniques have been used to boost the dc gain of OTAs, especially for low-frequency
Cm
gm1
g01
C01
gm2
Rz
v0 C02
g02
vi
1025
applications [28]. In this design, feed-forward paths are used for the phase compensation of a multi-path OTA [29]. Fig. 10 shows the simplified schematic of the proposed compensation scheme. The NCFF compensation scheme does not employ any compensation capacitor, but uses a Left plane (LHP) zero for obtaining good phase response. LHP zero causes positive phase shift in the phase and it is used to cancel part of the negative phase shift caused by the poles. The concept can be explained if the structure is analyzed. It can be easily found that the overall open-loop small signal transconductance gain is Gm ðsÞ ffi
1 þ gm2 ðAs o gm3
1
1 þ osP
PÞ
ðA1 gm2 þ gm3 Þ ¼
1 þ osZ 1 þ osP
gm ,
(17)
where A1 is the dc gain of the first stage ( ¼ gm1/g01), and the dominant pole of the first stage is located at oP ¼ g01 =C 01 . The dc transconductance is approximately given by gm¼ gm1 gm2 =g01 . By using this OTA in the amplifier configuration shown in Fig. 1, and according to Eqs. (1), (2), (4), (5), (7) and 17 it can be found that the closed-loop zero and poles are located at the following frequencies: gm2 gm1 oZ ffi , (18) gm3 C 01 oP1;2 ffi
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 0 1 ! u u gm3 þ g02 @ g g C L A m1 m2 1 t1 4 . 2C L C 01 ðgm3 þ g02 Þ2
(19) Notice that the real poles can always be obtained if gm3 is further increased, but the frequency of the closed-loop dominant pole and zero decreases, and slow components might appear (see Eq. (8)). The dominant pole and zero are close enough (mismatch lesser than 10%) if ! gm1 gm2 CL 4 o0:25. (20) C 01 ðgm3 þ g0 Þ2 Additional computations show that under this condition, the poles are located at
Fig. 9. Two-stage Miller compensation.
oP1 ffi
bgm1 gm2 , C 01 ðbgm3 þ g0 Þ
(21)
oP2 ffi
bgm3 bgm3 . ¼ CL C 4 þ bðC 1 þ C 3 Þ
(22)
-1 gm1 vi
v0
gm2 g01
g02
C01
C02
gm3
Fig. 10. No capacitor feed-forward (NCFF) compensated two-stage amplifier.
Notice that under these conditions oZ and oP1 are very close to each other regardless (when there is enough feedback) the absolute value of the load capacitors used; the root-locus is similar to the one depicted in Fig. 3. The frequency of both oP1 and oZ increases, increasing the speed, if the parasitic capacitors at the output of the first stage, C01, are reduced; this is a quite important design consideration. If C01 is reduced, then complex poles might appear, but these can be tolerated.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1026
Although some ringing appears in the transient response, fast response results if the real part of the poles is large enough. A switched-capacitor amplifier has been simulated with C1 ¼ C3 ¼ C4 ¼ 0:5 pF, and C 2 ¼ 1 pF (refer to Fig. 1). The transconductances gm1, gm2 and gm3 were set at 1, 4 and 10 mA/V, respectively; the parasitic capacitor at the output of the first stage, C01, was estimated to be around 0.25 pF (see Fig. 10). The amplifier dc gain is around 90 dB, because a telescopic amplifier is used for the first stage; the design details of the amplifier are discussed in the next section. Shown in Fig. 11a is the transient response for the NCFF amplifier under the following cases (C 3 ¼ 0:25 pF and C 4 ¼ 0:5 pF):
(1) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:25 pF (nominal case). (2) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:5 pF (large capacitance at the output of first stage). (3) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:75 pF (largest capacitance at the output of first stage).
(4) C 1 ¼ 1 pF, C 2 ¼ 2 pF and C 01 ¼ 0:25 pF (bigger input and integrating capacitors). As expected, case 3 is the most critical one; larger C01 ( ¼ 0.75 pF) leads to a zero located around 170 MHz only; the closed-loop dominant pole is located around this frequency leading to slow components. This effect is evident in curve 3. Although the variations in parameters are large, the 0.1% settling time is around 3.2 ns for cases 1 and 4. The pulse response is very slow if C01 increases, cases 2 and 3, where 1% settling is 3.3 and 7 ns, respectively. For comparison, a two-stage miller amplifier with large transconductance stages was designed; the transconductances used are gm1 ¼ gm2 ¼ 10 mA=V and a nominal Miller compensating capacitor of 2 pF; a nulling resistor optimized for RHP zero cancellation is used. The amplifier dc gain is set at 90 dB. Three cases are simulated for the miller amplifier: (1) Input and integrating capacitors of 0.5, 1 pF and C miller ¼ 2 pF.
0.6
Vout (Volts)
0.4 3
2
1 4
0.505 0.500
0.2
0.495
Case 1 0.0
0.490
Case 2
0.485
Case 3 0.480 3E-9
-0.2 0E+0
2E-9
4E-9
4E-9 6E-9 Time (Secs)
(a)
5E-9
8E-9
6E-9
1E-8
0.6
3
0.4 Vout (Volts)
1
2
0.515 0.510
0.2
0.505
Case 1
0.500
Case 2 0.0
Case 3 NCFF-1
-0.2 0E+0 (b)
2E-9
0.495 0.490 3.0E-9
4.0E-9
4E-9 6E-9 Time (Secs)
5.0E-9
8E-9
6.0E-9
1E-8
Fig. 11. (a) Pulse response for the NCCF two-stage amplifier and (b) the Miller amplifier.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
(2) Input and integrating capacitors of 1, 2 pF and C miller ¼ 3 pF. (3) Input and integrating capacitors of 1, 2 pF and C miller ¼ 4 pF. Notice that the NCFF approach (nominal case, C 01 ¼ 0:25 pF) can be faster than the Miller amplifier, even if the latter structure uses larger transconductances. 5. Experimental and simulated results A switched-capacitor amplifier using the three-path OTA has been fabricated in a standard 0.5 mm process through the educational service of MOSIS; a microphotograph of the chip is shown in Fig. 12. Input, integrating and load capacitors of 0.5 pF were used. A source follower is used as buffer to drive the large capacitors of the external devices and pads. The amplifier’s pulse response is depicted
Fig. 12. Chip microphotograph of the switched-capacitor three-path amplifier.
1027
in Fig. 13. The 1% settling-time is 12 ns; the standalone buffer, board impedances, connectors, rise and falling time of the signal generator (around 1 ns), and switch delay are responsible for more than 7 ns. Simulations results, discussed in the previous section, show that the amplifier’s settling time is less than 4 ns. This scheme has been successfully used for the design of a high-order 64-MHz switched capacitor filter [18]. A two-stage OTA using NCFF compensation scheme was implemented in AMI 0.5 mm CMOS technology with supply voltages of 71.25 V; the schematic is shown in Fig. 14. The active area for the amplifier is around 0.16 mm2. The bias current for the first stage is only
Fig. 14. Single-ended amplifier with NCFF compensation scheme.
Fig. 13. Pulse response for the switched-capacitor amplifier using the three-path OTA.
ARTICLE IN PRESS 1028
B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
I B1 ¼ 50 mA, and the one used in the second stage is I B2 ¼ 2 mA. For the feed-forward stage the tail current is I B3 ¼ 5 mA. The transistor aspect ratios are 960 mm/0.6 mm for the first differential pair, 600 mm/0.9 mm for the second stage and 120 mm/0.9 mm for the feed-forward path. The goals were to have high dc gain in the first stage with relatively high unity gain frequency, and gm3 bgm1 ; gm2 ; according to Eqs. (18) and (21) the pole–zero matching should be fairly good. Post-layout simulations show that for a load capacitance of 8 pF and an step of 300 mV, the 1% settling time of the OTA was 5.1 ns. Neither overshoots nor low frequency components were observed. The postlayout simulation results for a single ended OTA shows a DC gain of 91 dB, gain-bandwidth product of 325 MHz and slew-rate of 140 V/ms. An inverting amplifier, similar to the one shown in Fig. 1, was experimentally tested. For the test setup,
external capacitors of 5 pF were employed; the load capacitance used was 12 pF (estimated capacitance of measurement equipment probe capacitance and package bond-pad capacitance). The chip was measured; the 1% settling time for an input step of 0.8 V was 16–17 ns; around 12 ns correspond to slew-rate (due to the large signal swing) and 4–5 ns are lumped to the non-linear settling. The amplifier’s pulse response for large input signals (up to 2 V pk-pk) is shown in Fig. 15; notice that most of the settling time is due to slew-rate limitations. For these results, the input edge had a fall time of around 3 ns due to PCB, bond-pad parasitic (DIP-40 package was used), and equipment loading effects. The output step response has no ringing, which shows a good phase margin. Post-layout simulation results for the amplifier with a 4 ns fall time input step, and parasitic capacitors at the OTA input of 3 pF, and load capacitor of 12 pF show a 1%
Fig. 15. (a) Experimental results for the single-ended amplifier, and (b) closed look of the step response.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
settling time of around 13.5 ns, which is in conformance with the measured results. 6. Conclusions Feed-forward techniques can improve the speed of closed-loop switched-capacitor networks. It has been shown that the fully differential OTAs based on multitrajectories present higher slew-rate and superior settling performance than the conventional folded-cascode OTA. The pole–zero pair present in feed-forward topologies must be placed at high frequencies to avoid slow settling components. Another important advantage of feed-forward schemes is that due to the smaller parasitic capacitor present at the input, the error after settling is more than three times smaller than that obtained with the regular folded-cascode OTA. The NCFF compensation scheme allow us to have both high gain and fast settling time, resulting in accurate and fast step response. The increase in GBW as compared to other compensation schemes is due to the fact that the poles are not split. LHP zeros are used to cancel the phase shift of poles to obtain a good phase margin. The effect of pole–zero mismatches on feed-forward amplifier’s performance was studied and it was shown that the pole–zero cancellation should occur at high frequencies for best settling time performance. Experimental results for the OTAs show fast settling time and good stability. Simulation and experimental results for the amplifier are in accordance with the theoretical derivations. References [1] S.I. Liu, C.H. Kuo, R.Y. Tsai, J. Wu, A double-sampling pseudotwo-path bandpass DS modulator, IEEE J. Solid-State Circuits 35 (2000) 276–280. [2] P. Cusinato, D. Tonietto, F. Stefani, A. Baschirotto, A 3.3-V CMOS 10.7-MHz sixth-order bandpass SD modulator with 74-dB dynamic range, IEEE J. Solid-State Circuits 36 (2001) 629–638. [3] T. Salo, T. Hollman, S. Lindfors, K. Halonen, An 80-MHz 8th order bandpass SD modulator with 75 dB SNDR for IS-95, in: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, pp. 179–182. [4] B.K. Thandri, J. Silva-Martinez, M.J. Rocha-Perez, J. Wang, A 92 MHz, 80 dB peak SNR SC bandpass SD modulator based on a high GBW OTA with no Miller capacitors in 0.35 mm CMOS technology, in: Proceedings of the IEEE Custom Integrated Circuits Conference, 2003, pp. 123–126. [5] K. Bult, J.G.M. Geelen, A fast-settling CMOS OpAmp for SC circuits with 90-dB DC gain, IEEE J. Solid-State Circuits 25 (6) (1990) 1379–1384. [6] R. Eschauzier, J. Huijsing, Frequency Compensation Techniques for Low-power Operational Amplifiers, Kluwer Academic Publishers, Boston, 1995. [7] P.R. Gray, R.G. Meyer, MOS operational amplifier design—a tutorial overview, IEEE J. Solid-State Circuits SC-17 (6) (1982) 969–982. [8] T. Wakimoto, Y. Akazawa, A low-power wide-band amplifier using a new parasitic capacitance compensation technique, IEEE J. SolidState Circuits 25 (1) (1990) 200–206.
1029
[9] W. Sansen, Z.Y. Chang, Feedforward compensation techniques of CMOS high-frequency amplifiers, IEEE J. Solid-State Circuits 25 (6) (1990) 1590–1595. [10] F. Opt Eynde, W. Sansen, Design and optimization of CMOS wide band amplifiers, in: Proceedings of the IEEE CICC Conference, San Diego, May 1989, pp. 25.7.1–4. [11] J. Silva-Martinez, F. Carreto-Castro, Improving the high-frequency response of the folded-cascode amplifiers, in: IEEE, Proceedings ISCAS-96, vol. 1, 1996, pp. 500–503. [12] C. Toumazou, S. Setty, Feedforward compensation techniques for the design of low-voltage OPAMPs and OTAs, in: IEEE, Proceedings of the ISCAS-98, vol. 1, 1998, p. 464. [13] R.H.M. van Veldhoven, A triple mode continuous-time SD modulator with switched-capacitor feedback DAC for a GSMEDGE/CDMA2000/UMTS receiver, IEEE J. Solid-State Circuits 38 (12) (2003) 2069–2076. [14] S.T. Ryu, S. Ray, B.S. Song, G.H. Cho, K. Bacrania, A 14-b linear capacitor self-trimming pipelined ADC, IEEE J. Solid-State Circuits 39 (11) (2004) 2046–2051. [15] Y.Q. Yan, A. Chokhawala, M. Alexander, J. Melanson, D. Hester, A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm2, IEEE J. Solid-State Circuits 38 (12) (2003) 2061–2068. [16] M.D. Pardoe, M.G. Degrauwe, A rail-to-rail input/output CMOS power amplifier, IEEE J. Solid-State Circuits 25 (2) (1990) 501–504. [17] G. Olvera-Romero, J. Silva-Martı´ nez, A folded-cascode OTA for high-frequency applications based on complementary differential pairs, in: Proceedings of the IEEE International Workshop on Mixed-Mode Integrated Circuits and Applications, July 26–29, 1999, pp. 57–60. [18] J. Silva-Martinez, J. Adut, M. Rocha-Perez, A 58 dB SNR 6th order broadband 10.7 MHz SC-ladder filter, in: Proceedings of the IEEE Custom Integrated Circuits Conference, September 2003, pp. 13–16. [19] L. Wang, S.H.K. Embabi, Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper, IEEE J. Solid-State Circuits 38 (8) (2003) 1411–1415. [20] J. Grilo, I. Galton, K. Wang, R.G. Montemayor, A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver, IEEE J. Solid-State Circuits 37 (3) (2003) 271–278. [21] R. Gaggl, A. Wiesbauer, G. Fritz, C. Schranz, P. Pessl, A 85-dB dynamic range multibit delta–sigma ADC for ADSL-CO applications in 0.18-_m CMOS, IEEE J. Solid-State Circuits 38 (7) (2003) 1105–1114. [22] F. You, S.H.K. Embabi, E. Sanchez-Sinencio, A multistage amplifier topology with nested Gm-C compensation for low-voltage application, IEEE J. Solid-State Circuits 32 (1997) 2000–2011. [23] R. Eschauzier, et al., A 100-MHz 100-dB operational amplifier with multipath nested miller compensation structure, IEEE J. Solid-State Circuits 27 (1992) 1709–1717. [24] L. Yao, M.S.J. Steyaert, W. Sansen, A 1-V 140-W 88-dB audio sigma-delta modulator in 90-nm CMOS, IEEE J. Solid-State Circuits 39 (11) (2004) 1809–1818. [25] Y.B. Kamath, R. Meyer, P. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. SolidState Circuits 9 (1974) 347–352. [26] H.C. Yan, D.J. Allstot, Considerations for fast settling operational amplifiers, IEEE Trans. Circuits Syst. 37 (1990) 326–334. [27] U. Chilakapati, T. Fiez, Settling time design considerations for SC integrators, IEEE Trans. Circuits Syst. 46 (Part II) (1999) 810–816. [28] A. Thomsen, A five stage chopper stabilized instrumentation amplifier using feedforward compensation, in: Proceedings of the IEEE Symposium on VLSI circuits, Honolulu, 1998, pp. 220–223. [29] B.K. Thandri, J. Silva-Martinez, A robust feedforward compensation scheme for multi-stage operational transconductance amplifiers with no Miller capacitors, IEEE J. Solid-State Circuits 38 (2003) 237–243.
Microelectronics Journal 37 (2006) 1018–1029 www.elsevier.com/locate/mejo
An overview of feed-forward design techniques for high-gain wideband operational transconductance amplifiers Bharath Kumar Thandri, Jose Silva-Martinez Department of Electrical Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX 77843, USA Received 11 January 2005; received in revised form 26 December 2005; accepted 15 February 2006 Available online 19 April 2006
Abstract In this paper, feed-forward techniques are revised and used for the design of high-frequency operational transconductance amplifiers (OTA). For the same power consumption and similar transistor dimensions, the two- and three-path folded-cascode OTA’s present both smaller settling error and faster response as compared to the typical folded-cascode topology. Also, a no-capacitor feed-forward (NCFF) compensation which uses a high-frequency pole–zero doublet to obtain high gain, high GBW and a good phase margin is discussed. The settling-time of the NCFF topology can be faster than that of OTA’s with Miller compensation, even if the latter topology uses larger transconductance values. Experimental results for the multi-trajectory OTA’s fabricated in the AMI 0.5 mm CMOS process demonstrate the feasibility of the feed-forward schemes. r 2006 Elsevier Ltd. All rights reserved. Keywords: Operational transconductance amplifiers; Broadband amplifiers; Feed-forward techniques; Phase compensation techniques; Multipath amplifiers; Folded-cascode amplifiers
1. Introduction The increasing need for faster and more accurate IC’s poses challenging design specifications for the amplifiers which are the basic building blocks for many applications such as precise analog filters, A/D and D/A converters. IF switched-capacitor filters and high-resolution data converters with sampling frequencies above 100 MHz require very fast OTAs with settling times below 3–4 ns for good performance [1–24]. It is very difficult to design an amplifier with both high gain and high bandwidth. High gain amplifiers use cascode structures or multi-stage designs with long channel length transistors biased at low current levels. High bandwidth amplifiers use single-stage designs with short channel length transistors biased at high current levels. Since the folded-cascode OTA presents a single parasitic pole and relatively large DC gain, it is commonly used for high-frequency applications [5,7–18]. For such applications, the typical folded-cascode structure presents some Corresponding author. Tel.: +1 979 845 7477; fax: +1 979 845 7167.
E-mail address: [email protected] (J. Silva-Martinez). 0026-2692/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2006.02.003
limitations because P-type cascode transistors determine the parasitic pole if N-drivers are used; the phase margin of the resulting structure is limited. Regulated telescopic structures are becoming more popular due to the power savings, at the expenses of limited signal swing [13–15]. In order to extend the folded cascode frequency bandwidth, several phase compensation schemes have been reported in the literature [8–12]; these techniques are briefly described in the next section. It is shown that multi-path foldedcascode OTA is faster and more accurate than the conventional folded-cascode OTA due to the action of the feed-forward paths. Cascading of individual gain stages gives a high gain amplifier, but each stage introduces a low frequency pole, which produces a negative phase shift and degrades the phase margin. Many phase compensation schemes for multi-stage amplifiers have been reported in literature [6,7,19–24]. All the reported schemes are a variation of the basic Miller compensation scheme for a two-stage amplifier. The dominant pole is pushed to lower frequencies due to Miller effect, resulting in lower bandwidth structures. Also, a right half-plane (RHP) zero is created; hence a nulling resistor is usually used to cancel its effects. Other
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
reported compensation schemes use the positive phase shift of a left half-plane (LHP) zero created by a feed-forward path to improve amplifier’s phase response [22,23]. The NCFF compensation scheme employs a feed-forward path to create LHP zeros, but does not use any miller capacitor [29]. The dominant pole is not pushed to lower frequencies and results in a higher gain-bandwidth product with a fast step response. The theoretical aspects of feed-forward techniques are discussed in Section 2. Section 3 deals with foldedcascode OTAs with feed-forward paths. High gain twostage amplifiers without Miller compensation are considered in Section 4; it is shown that the NCFF technique is robust even if the integrating and load capacitors are varied in a very large fashion. Section 5 describes the circuit simulation and experimental results; the conclusions are drawn in the last section. 2. Settling-time in presence of a pole–zero pair In this section, the speed of a switched-capacitor amplifier in presence of a pole–zero pair is considered. A macromodel of the typical capacitive amplifier used in switched-capacitor circuits is shown in Fig. 1a. By using conventional circuit analysis techniques, the small signal transfer function can be calculated and is given by ! ! C1 2 1 sC v0 ðsÞ gm C2 ffi , (1) 1 þC 3 ÞÞ vi ðsÞ 1 þ bA1 V 1 þ sðC 4 þbðC bg m
where AV ¼ gm =g0 and b ¼ C 2 =ðC 1 þ C 2 þ C 3 Þ are the amplifier open-loop DC gain and the feedback factor, respectively. A typical open- and closed-loop magnitude C2 C1 vin
vx
C3
vo gmvx
g0
1019
response is depicted in Fig. 1b. The ideal closed-loop amplifier gain is given by C1/C2; it can be noticed in (1) that when the steady state is reached, the error in the final value is determined by the factor 1/(bAV). The closed-loop bandwidth is determined by the RHP zero and parasitic pole. The location of the pole is given by oPeff ¼
bgm C4 þ
C 2 ðC 1 þC 3 Þ C 1 þC 2 þC 3
¼
bgm bg ¼ m, C 4 þ bðC 1 þ C 3 Þ CL
(2)
where CL ( ¼ C4+b(C1+C3)) is the effective loading capacitor. It is important to reduce the parasitic capacitor C3 to increase b, especially for high frequency applications. The typical step response of the underdamped capacitive amplifier is shown in Fig. 2. It consists of two phases, initial slew phase (assumed to be linear) and a non-linear settling to a final value. Single-stage OTA slew-rate (SR) is determined by the amount of current that can be delivered or extracted from the output and the effective load capacitor (SR ¼ I/CL); usually class AB amplifiers increase the SR [2]. The nonlinear phase is determined by both the effective pole’s frequency oPeff and phase margin, and in many practical low-voltage cases dominates the overall settling time. If the slew-rate phase and the RHP zero are ignored, the closed-loop pulse response of the amplifier is given by the following equation: ! 1 eoPeff t vo ðtÞ ¼ vo ðt0 Þ (3) avi ðtÞ, 1 þ bA1 V where a ¼ C 1 =C 2 is the ideal amplifier’s gain. A high performance amplifier should have high oPeff for fast settling and high DC gain AV for accurate final value. The analysis of the amplifier impulse response in the presence of a pole–zero doublet is more complex; in [25–27] it was shown that the presence of low-frequency pole–zero pairs may generate slow components that reduces significantly the amplifier’s speed; this is not the case if high-frequency pole–zero doublets are present. In order to consider the effects of high-frequency pole–zero pairs, the overall open-loop transconductance of the
C4
(a)
-vo Open-loop gain
gmr0
GBW limitation Vin
C1/C2
(b)
DC-gain limitation
Closed-loop gain
1/r0CL ω
ωeff Slew rate
Fig. 1. Typical OTA-based capacitor amplifier: (a) schematic and (b) typical open- and closed-loop magnitude response.
Fig. 2. Step response of a unity gain amplifier with enough phase margin.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1020
amplifier can be simplified as ! 1 þ osZ G m ðsÞ ¼ g . 1 þ osP m
(4)
1
1 þ bA1 V
,
ð5Þ
where oPeff ð¼ bgm C L Þ is defined by Eq. (2). It can be easily found that the closed-loop poles are real if the following condition is satisfied: qffiffiffiffiffiffiffi oPeff oP
þ g0o=CP L 1 þ ooPeff Z
1
hðtÞ ¼
If the right-hand side zero gm/C2 is ignored, using Eqs. (1) and (4), the closed-loop transfer function is obtained as 0 1 1 þ osZ v0 ðsÞ A ffi @ 1 1 vi ðsÞ s2 1 þ o1Z þ oPeff þ bgg0oP s þ o1P oPeff m ! C C2
feedback factor is present. The closed-loop amplifier’s impulse response (assuming that oP1 aoP2 ) is given by ! C
o0:5x.
(6)
Due to the presence of the zero and the finite OTA output resistance, the poles might be real even if oP ooPeff . According to Eq. (5), the closed-loop poles are located at g0 1 oP 1 þ ooPeff þ o C Z L P oP1;2 ffi 2 0 1 vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u oPeff u B C oP B 1 u1 4 ð7Þ 2 C t @ A g0 1 1 þ ooPeff þ C L oP Z For real poles, both poles are located above and below to ðoP ð1 þ oPeff =oZ Þ þ g0 =C L Þ=2, respectively. If the poles are complex conjugate, the real part increases above oP due to the effect of both zero and OTA output resistance. Also, both zero and amplifier output resistance reduces the imaginary part of the poles. Fig. 3 shows the typical root locus of a two-pole and 1 zero system. In both cases, the lowest frequency pole is close to the frequency of the zero if enough feedback is used. A common case for the feedforward amplifiers to be discussed in the following sections is shown in Fig. 4; it corresponds to the root-locus shown in Fig. 3a. Both open- and closed-loop gains are depicted. Notice in this figure that closed-loop pole–zero doublet appears close to the open-loop zero’s frequency if enough
C2
1 þ bA1 V
ðoP1 oP2 ÞððoP1 oZ Þ eoP1 t þ ðoZ oP2 Þ eoP2 t Þ . ðoP1 oP2 ÞoZ
ð8Þ Slow output components are avoided if both closed-loop poles oP1 and oP2 are placed at high frequencies; this however is possible if and only if the zero is located at high frequencies. An important observation here is that if the dominant pole is close to the location of the zero, its coefficient (proportional to oP1 oZ ) is reduced then reducing the effect of possible slow components. 3. Feed-forward techniques for folded-cascode OTAs The typical folded-cascode OTA is shown in Fig. 5a [7]; its small-signal transconductance gain is approximately given by the following expression: gm1 Gm ffi , (9) 1 þ s gC P mP
where gm1 is the small-signal transconductance of M1, and CP is the capacitance associated with the source of MP. The transconductance of the cascode transistors (P-transistors) and the equivalent parasitic capacitor CP at that node determine the open-loop pole’s frequency. For wide-band
Open-Loop Gain
Closed-Loop Gain
C1 C2
ωz ωp2 ωp1 ω Fig. 4. Open- and closed-loop transfer function of a second-order system in presence of a zero. The zero is located after the open-loop poles.
Im
Im
S-plane
X ωz ωp2
(a)
S-plane
X ωp1
Re
X ωp2
ωz
X ωp1
Re
(b)
Fig. 3. Typical root locus for a system with two poles and 1 zero: (a) zero is located at high frequencies; and (b) zero located between the poles. In both cases the dominant pole is terminated by the zero.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
applications, large unity gain frequency is needed, therefore the frequency of the parasitic pole oP ( ¼ gmP/CP) must be placed at very high frequencies. If we consider the same gate dimensions and same bias current for transistors M1 and MP then gm14gmP because the mobility of the N-transistors is higher than the mobility of the P-transistors (three times larger for the technology used). If second-order effects such as mobility degradation, it can be found that sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi gmP 1 2mP 1 oP ¼ (10) ffi I B. Y C OX W P L3P CP In this expression, WP and LP are the width and length of the gate of MP, respectively, and IB is the transistor bias current. COX and mP are the oxide capacitance and the mobility of the carriers in the channel, respectively. The parameter Y is a result of the parasitic capacitors at the cascode node, and can be expressed as P Capacitors at source of MP Y¼ 41, (11) C GSP where CGSP is the gate-source capacitance of MP; for practical circuits 2:54Y41. In accordance with Eqs. (10) and (11), a large Y results in a low frequency nondominant pole; hence it is desirable to reduce as much as possible the drain and source areas of critical transistors. Increasing the bias current increases the frequency of the parasitic poles; unfortunately, the DC gain reduces and the power consumption increases. Limiting the width of the cascode transistor increases the frequency of the parasitic pole but this benefit is limited because the saturation voltage must be maintained within the limits dictated by the supply voltages and signal swing, mobility degradation due to vertical electrical field become more critical in that case as well. On the other hand, a reduction in the length of the cascode transistors reduces VDSAT and increases oP; the drawback is the reduction of the OTA dc gain, and transversal electric field may reduce the effective mobility of the carriers. The frequency of the parasitic pole can be increased by a factor O3 if the dual of the circuit shown in Fig. 5a is employed; the N- and P-type transistors are replaced by P- and N-type transistors, respectively. The drawback is that the overall amplifier’s transconductance is reduced due to the reduced mobility of the carriers in the P-drivers. The ideal OTA should use N-type transistors for both differential pair and cascodes, such that their higher mobility increase both the small signal transconductance and phase margin. This is the major advantage of the telescopic structure [13,14] but unfortunately its output swing is limited, especially for lowvoltage applications and if low VT transistors are not available. To overcome some of these tradeoffs, a number of feedforward compensation techniques have been reported
1021
[5,8–12]. The technique proposed in [9] uses RC networks connected to the gate of the cascode transistors, hence a zero is introduced such that the parasitic pole is partially compensated. In the technique proposed in Ref. [10], the low-frequency signal flows throughout the P-type cascode transistors and, by using RC networks, the highfrequency signal flow throughout the N-type cascode transistors. Due to the higher mobility of the N-transistors, better performances can theoretically be achieved. The additional networks increase the capacitance of the parasitic nodes reducing the frequency of the poles and additional silicon area is needed; a low-frequency pole–zero may increase amplifier’s settling time. In Ref. [11], the gate of the cascode transistor is directly connected to the input signals; by using that feed-forward scheme, further improvements in the OTA phase margin are obtained due to the presence of a high frequency zero. A major drawback of this technique is that the gate-drain capacitors of the cascode transistors affect the precision of the system, especially for switched-capacitor circuits. This drawback has been partially solved by using cross-coupled capacitors [12]. Complementary differential pairs have been used for long time for the design of rail to rail amplifiers [16]. They can also be used for fast amplifiers [17], where all cascode transistors can be exploited as shown in Fig. 5b. It can be shown that the small-signal transconductance of the composite OTA is given by g C gm2 þgm1 g mP CN mN P 1 þ s gC P gm1 þgm2 mP ðgm1 þ gm2 Þ, Gm ðsÞ ffi (12) 1 þ s gC P 1 þ s gC N mP
mN
where CP and CN are the parasitic capacitors lumped to the source of transistors MP and MN, respectively. The overall current consumption is 4*IB, same as the folded-cascode OTA previously discussed. The low-frequency small-signal transconductance is given by gm1+gm2. For same overall current and same input capacitance, its small signal transconductance is around 15% less than the one for the typical folded-cascode OTA. For same transconductance and same power, the width of the drivers must be scaled up by 30%; the input capacitance increases by the same factor, this is a major drawback of this topology. The slew-rate, on the other hand, is 33% higher because the sourced/sinked current can be as high as (4/3)IB. Since the P-transistors at the output stage are handling lesser dc current their dimensions can be relaxed, then the parasitic poles can be placed at higher frequencies. From Fig. 5b, the pole lumped at the source of MP is located at lower frequency than this at the source of MN; the phantom zero lies in between. Since the poles are lumped to the cascode nodes and the zero are located at high frequencies, the settling time is not degraded according to the discussion of the previous section. The current-mirror cascode OTA shown in Fig. 6a has a non-dominant pole at gate of M6 in addition to the poles
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1022
dc gain. It should be pointed out that if the phase margin is enough, this structure may settle faster than the foldedcascode OTA because of its enhanced SR and smaller input capacitance (larger b). A three-path OTA built by the combination of the three different OTAs is depicted in Fig. 6b [18]. A folded-cascode OTA is implemented due to the action of M1, M2 and M3, and a current-mirror cascode OTA is composed by transistors M1–M3 and M6. Also, a current-mirror foldedcascode OTA is embedded due to M1, M4, M6 and M7. The OTA input consists of a split differential pair; half of the ac current generated by the input stage is injected to the source of the N-type cascode transistors, providing a fast path for the current. The other part of the current is delivered to the current mirrors. M6 is the basic transistor of the current mirror: one of its copies, M2, is mirrored to the output stage with a gain of N. M7 provides a current gain factor M. The OTA’s dominant pole is determined by the equivalent resistor and capacitor at the OTA output, while the two non-dominant poles are lumped to the cascode transistors M3 and M4, and the gate of M6, respectively. The small-signal transconductance is given as follows:
(a)
Gm ¼
þ s2 ð1þMþN1 ÞoN2 oP1 þ o1N2 þ 1þN oP1 1 þ osN1 1 þ osN2 1 þ osP1
1 1þMþN
M oN1
ðð1 þ M þ NÞgm1 Þ,
(b) Fig. 5. (a) Typical folded-cascode OTA and (b) folded-cascode OTA using complementary differential pairs.
of the cascode transistor. The overall small signal transconductance is given as Gm ¼
Ngm1 1 þ osN1 1 þ osN2
(13)
and oN1 ffi
1þs
gm6 ; C GS6 ð1 þ NÞ
oN2 ffi
gm3 , C GS3 þ C SB3
(14)
where gm3(6) is the transconductance of transistor M3 (M6), and N ¼ gm2/gm6. The current-mirror cascode OTA suffers from a similar limitation as the standard folded-cascode OTA; during negative slewing, only half of the drain current of M2 is employed in discharging the load capacitance because the dc current provided by M5 cancels the other half. However, a larger fraction of the overall current used can be transferred to the load if N41. With a current gain greater than 1 in the current mirror, the size of the input transistors can be reduced for same GBW as the folded-cascode OTA. Although this decreases the input capacitance, the parasitic capacitance at the gate of M6 increases, which pushes the non-dominant pole to lower frequencies. For same power consumption, N41 increases the current levels at the output stage, lowering the OTA’s
gm3 ; C GS3 þ C SB3 gm4 ffi . C GS4 þ C SB4
oN1 ffi oP1
oN2 ffi
ð15Þ gm6 , C GS6 ð1 þ M þ N Þ ð16Þ
oN2 is the most important non-dominant pole and limits the frequency response of the overall amplifier. Transistors M2, M6 and M7 must be optimized for maximum frequency response. Since the frequency of one of the zeros is below the frequency of oN1 and oP1, in an aggressive design oN2 can be selected close to the OTA’s unity gain frequency. As compared with the regular foldedcascode OTA, oN2 is below the frequency of the nondominant pole of the folded-cascode structure; it can be shown that for same VDSAT and same L, the ratio of the non-dominant pole of the two strctures, onon-dominant F-C/ onon-dominant-3-path, is roughly 2/(1+M+N). The three-path OTA has smaller input transistor sizes, leading to reduced input capacitances; as a result, its closed-loop feedback factor increases and the closed-loop response is faster if the phase margin is good enough. For slew, the three-path OTA output current is a greater portion of the total current, as all transistors except M5 adjust dynamically their currents during slewing. On the other hand, this topology is a bit noisier than the folded-cascode OTA and the one using the complementary differential pairs due to the smaller transconductance of the input stage. This is, however, not critical for many SC applications wherein the
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1023
(a)
(b) Fig. 6. (a) Two-current mirror OTA with cascode output stage and (b) three-path operational transconductance amplifier.
most important noise contributions are due to the switch resistance. The four OTAs discussed in this section were compared in a SC fully differential amplifier with input, feedback and loading capacitors of 1 pF each. The OTAs were designed for the same transconductance, same current consumption and same output voltage swing. The three-path OTA was designed with N ¼ 4 and M ¼ 1; for the current mirror cascode OTA we used a current mirror factor of N ¼ 4. The pulse response for these topologies is shown in Fig. 7. Whereas the other OTAs use smaller fraction of the total bias current during the slewing phase, the three-path OTA outperforms the other topologies in this aspect. Although the multi-path OTAs suffer from relatively poor phase margin its settling time is comparable with other topologies. The multiple-path designs achieve a substantial
improvement in both SR and accuracy as compared with the regular folded-cascode OTA. The three-path design achieves the best settling accuracy (settling erroro0.42%). This study suggests that the simple current-mirror cascode OTA, usually not preferred for high-speed applications because of poor phase margin, performs better than the standard folded-cascode OTA. The results are summarized in Table 1. 4. Feed-forward scheme for multi-stage OTAs with no Miller capacitors Amplifiers with cascaded gain stages are very popular for switched-capacitor applications as well [6,19–24]. Several compensation schemes have been reported in literature for multi-stage amplifiers [22,23]; two of them
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1024
0.6 3-path Current mirror 0.4
Complementary
Output voltage (V)
Folded-cascode 0.2
0.505 Current-mirror 0.500
0.0
3-path
0.495 Complementary
-0.2 0.490
-0.4
Folded-cascode 0.485 4
5
6
7
-0.6 0
1
2
3 4 Time (nsecs)
5
6
7
Fig. 7. OTAs ransient response for a differential input step of 500 mV. The pulse is applied at t ¼ 0:25 ns.
Table 1 Comparison of simulation results for four different OTAs Parameter
Folded-cascode
Current-mirror cascade
Complementary diff pairs
Three-path OTA
SR (V/ms) DC gain (dB) Ts (1%) (ns) Ts (0.1%) (ns) Settling error (%) Input noise (109 V/Hz1/2)
392 55.9 4.2 5.3 1.15 1.67
496 55.9 3.7 4.9 0.75 2.4
473 60.6 3.7 4.7 0.95 1.73
555 60.4 3.6 4.2 0.42 2.43
The OTA small signal transconductance is around 4.2 mS for all structures
Cm1 Cm2 -1 gm2
gm1
v0
gm2
vi (a)
Cm1 Cm2 -1 gm1
gm2
gm3
v0
vi
gm4 (b) Fig. 8. Three-stage amplifiers with: (a) nested Miller compensation, and (b) nested Miller compensation with a feed-forward path.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
are shown in Fig. 8. The inverting amplifiers are not needed if differential stages are used. The DC gain for these structures is given by the multiplication of the three-gain stages; hence dc gains of 90–100 dB can easily be achieved. Due to the three high impedance nodes, double miller compensation is required for proper phase margin. The multi-path Miller structure shown in Fig. 8b incorporates a feed-forward path (gm4); this trajectory improves the high frequency response of the structure canceling the righthand zero due to the miller capacitors, but still double miller compensation is needed. The classic two-stage miller compensation scheme is shown in Fig. 9. The open-loop dominant pole, opd ¼ g01 =AV2 C m , is pushed to lower frequency because of the increase in the effective capacitance caused by the compensation capacitor (Cm) and the gain of the second stage. This decreases the open-loop unity gain frequency ou ðgm1 =C m Þ and results in slower settling time. The non-dominant pole is mainly given by gm2 =ðC 01 þ C 02 Þ; unfortunately the load capacitor C02 depends on the application and might be large, hence the speed of the system is limited. For good stability, the condition gm2 =ðC 01 þ C 02 Þ4gm1 =C m must be satisfied; unfortunately high-frequency SC circuits may require large load capacitors that force us to use large gm2 further increasing the power consumption and parasitic capacitances. RHP zero at oZ ¼ gm2 =C m is generated and a nulling resistor must be used to compensate this effect. In some other circuits such as that shown in Fig. 8b a feedforward path (gm4) is used for this purpose. Feed-forward compensation techniques have been used to boost the dc gain of OTAs, especially for low-frequency
Cm
gm1
g01
C01
gm2
Rz
v0 C02
g02
vi
1025
applications [28]. In this design, feed-forward paths are used for the phase compensation of a multi-path OTA [29]. Fig. 10 shows the simplified schematic of the proposed compensation scheme. The NCFF compensation scheme does not employ any compensation capacitor, but uses a Left plane (LHP) zero for obtaining good phase response. LHP zero causes positive phase shift in the phase and it is used to cancel part of the negative phase shift caused by the poles. The concept can be explained if the structure is analyzed. It can be easily found that the overall open-loop small signal transconductance gain is Gm ðsÞ ffi
1 þ gm2 ðAs o gm3
1
1 þ osP
PÞ
ðA1 gm2 þ gm3 Þ ¼
1 þ osZ 1 þ osP
gm ,
(17)
where A1 is the dc gain of the first stage ( ¼ gm1/g01), and the dominant pole of the first stage is located at oP ¼ g01 =C 01 . The dc transconductance is approximately given by gm¼ gm1 gm2 =g01 . By using this OTA in the amplifier configuration shown in Fig. 1, and according to Eqs. (1), (2), (4), (5), (7) and 17 it can be found that the closed-loop zero and poles are located at the following frequencies: gm2 gm1 oZ ffi , (18) gm3 C 01 oP1;2 ffi
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 0 1 ! u u gm3 þ g02 @ g g C L A m1 m2 1 t1 4 . 2C L C 01 ðgm3 þ g02 Þ2
(19) Notice that the real poles can always be obtained if gm3 is further increased, but the frequency of the closed-loop dominant pole and zero decreases, and slow components might appear (see Eq. (8)). The dominant pole and zero are close enough (mismatch lesser than 10%) if ! gm1 gm2 CL 4 o0:25. (20) C 01 ðgm3 þ g0 Þ2 Additional computations show that under this condition, the poles are located at
Fig. 9. Two-stage Miller compensation.
oP1 ffi
bgm1 gm2 , C 01 ðbgm3 þ g0 Þ
(21)
oP2 ffi
bgm3 bgm3 . ¼ CL C 4 þ bðC 1 þ C 3 Þ
(22)
-1 gm1 vi
v0
gm2 g01
g02
C01
C02
gm3
Fig. 10. No capacitor feed-forward (NCFF) compensated two-stage amplifier.
Notice that under these conditions oZ and oP1 are very close to each other regardless (when there is enough feedback) the absolute value of the load capacitors used; the root-locus is similar to the one depicted in Fig. 3. The frequency of both oP1 and oZ increases, increasing the speed, if the parasitic capacitors at the output of the first stage, C01, are reduced; this is a quite important design consideration. If C01 is reduced, then complex poles might appear, but these can be tolerated.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
1026
Although some ringing appears in the transient response, fast response results if the real part of the poles is large enough. A switched-capacitor amplifier has been simulated with C1 ¼ C3 ¼ C4 ¼ 0:5 pF, and C 2 ¼ 1 pF (refer to Fig. 1). The transconductances gm1, gm2 and gm3 were set at 1, 4 and 10 mA/V, respectively; the parasitic capacitor at the output of the first stage, C01, was estimated to be around 0.25 pF (see Fig. 10). The amplifier dc gain is around 90 dB, because a telescopic amplifier is used for the first stage; the design details of the amplifier are discussed in the next section. Shown in Fig. 11a is the transient response for the NCFF amplifier under the following cases (C 3 ¼ 0:25 pF and C 4 ¼ 0:5 pF):
(1) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:25 pF (nominal case). (2) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:5 pF (large capacitance at the output of first stage). (3) C 1 ¼ 0:5 pF, C 2 ¼ 1 pF and C 01 ¼ 0:75 pF (largest capacitance at the output of first stage).
(4) C 1 ¼ 1 pF, C 2 ¼ 2 pF and C 01 ¼ 0:25 pF (bigger input and integrating capacitors). As expected, case 3 is the most critical one; larger C01 ( ¼ 0.75 pF) leads to a zero located around 170 MHz only; the closed-loop dominant pole is located around this frequency leading to slow components. This effect is evident in curve 3. Although the variations in parameters are large, the 0.1% settling time is around 3.2 ns for cases 1 and 4. The pulse response is very slow if C01 increases, cases 2 and 3, where 1% settling is 3.3 and 7 ns, respectively. For comparison, a two-stage miller amplifier with large transconductance stages was designed; the transconductances used are gm1 ¼ gm2 ¼ 10 mA=V and a nominal Miller compensating capacitor of 2 pF; a nulling resistor optimized for RHP zero cancellation is used. The amplifier dc gain is set at 90 dB. Three cases are simulated for the miller amplifier: (1) Input and integrating capacitors of 0.5, 1 pF and C miller ¼ 2 pF.
0.6
Vout (Volts)
0.4 3
2
1 4
0.505 0.500
0.2
0.495
Case 1 0.0
0.490
Case 2
0.485
Case 3 0.480 3E-9
-0.2 0E+0
2E-9
4E-9
4E-9 6E-9 Time (Secs)
(a)
5E-9
8E-9
6E-9
1E-8
0.6
3
0.4 Vout (Volts)
1
2
0.515 0.510
0.2
0.505
Case 1
0.500
Case 2 0.0
Case 3 NCFF-1
-0.2 0E+0 (b)
2E-9
0.495 0.490 3.0E-9
4.0E-9
4E-9 6E-9 Time (Secs)
5.0E-9
8E-9
6.0E-9
1E-8
Fig. 11. (a) Pulse response for the NCCF two-stage amplifier and (b) the Miller amplifier.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
(2) Input and integrating capacitors of 1, 2 pF and C miller ¼ 3 pF. (3) Input and integrating capacitors of 1, 2 pF and C miller ¼ 4 pF. Notice that the NCFF approach (nominal case, C 01 ¼ 0:25 pF) can be faster than the Miller amplifier, even if the latter structure uses larger transconductances. 5. Experimental and simulated results A switched-capacitor amplifier using the three-path OTA has been fabricated in a standard 0.5 mm process through the educational service of MOSIS; a microphotograph of the chip is shown in Fig. 12. Input, integrating and load capacitors of 0.5 pF were used. A source follower is used as buffer to drive the large capacitors of the external devices and pads. The amplifier’s pulse response is depicted
Fig. 12. Chip microphotograph of the switched-capacitor three-path amplifier.
1027
in Fig. 13. The 1% settling-time is 12 ns; the standalone buffer, board impedances, connectors, rise and falling time of the signal generator (around 1 ns), and switch delay are responsible for more than 7 ns. Simulations results, discussed in the previous section, show that the amplifier’s settling time is less than 4 ns. This scheme has been successfully used for the design of a high-order 64-MHz switched capacitor filter [18]. A two-stage OTA using NCFF compensation scheme was implemented in AMI 0.5 mm CMOS technology with supply voltages of 71.25 V; the schematic is shown in Fig. 14. The active area for the amplifier is around 0.16 mm2. The bias current for the first stage is only
Fig. 14. Single-ended amplifier with NCFF compensation scheme.
Fig. 13. Pulse response for the switched-capacitor amplifier using the three-path OTA.
ARTICLE IN PRESS 1028
B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
I B1 ¼ 50 mA, and the one used in the second stage is I B2 ¼ 2 mA. For the feed-forward stage the tail current is I B3 ¼ 5 mA. The transistor aspect ratios are 960 mm/0.6 mm for the first differential pair, 600 mm/0.9 mm for the second stage and 120 mm/0.9 mm for the feed-forward path. The goals were to have high dc gain in the first stage with relatively high unity gain frequency, and gm3 bgm1 ; gm2 ; according to Eqs. (18) and (21) the pole–zero matching should be fairly good. Post-layout simulations show that for a load capacitance of 8 pF and an step of 300 mV, the 1% settling time of the OTA was 5.1 ns. Neither overshoots nor low frequency components were observed. The postlayout simulation results for a single ended OTA shows a DC gain of 91 dB, gain-bandwidth product of 325 MHz and slew-rate of 140 V/ms. An inverting amplifier, similar to the one shown in Fig. 1, was experimentally tested. For the test setup,
external capacitors of 5 pF were employed; the load capacitance used was 12 pF (estimated capacitance of measurement equipment probe capacitance and package bond-pad capacitance). The chip was measured; the 1% settling time for an input step of 0.8 V was 16–17 ns; around 12 ns correspond to slew-rate (due to the large signal swing) and 4–5 ns are lumped to the non-linear settling. The amplifier’s pulse response for large input signals (up to 2 V pk-pk) is shown in Fig. 15; notice that most of the settling time is due to slew-rate limitations. For these results, the input edge had a fall time of around 3 ns due to PCB, bond-pad parasitic (DIP-40 package was used), and equipment loading effects. The output step response has no ringing, which shows a good phase margin. Post-layout simulation results for the amplifier with a 4 ns fall time input step, and parasitic capacitors at the OTA input of 3 pF, and load capacitor of 12 pF show a 1%
Fig. 15. (a) Experimental results for the single-ended amplifier, and (b) closed look of the step response.
ARTICLE IN PRESS B.K. Thandri, J. Silva-Martinez / Microelectronics Journal 37 (2006) 1018–1029
settling time of around 13.5 ns, which is in conformance with the measured results. 6. Conclusions Feed-forward techniques can improve the speed of closed-loop switched-capacitor networks. It has been shown that the fully differential OTAs based on multitrajectories present higher slew-rate and superior settling performance than the conventional folded-cascode OTA. The pole–zero pair present in feed-forward topologies must be placed at high frequencies to avoid slow settling components. Another important advantage of feed-forward schemes is that due to the smaller parasitic capacitor present at the input, the error after settling is more than three times smaller than that obtained with the regular folded-cascode OTA. The NCFF compensation scheme allow us to have both high gain and fast settling time, resulting in accurate and fast step response. The increase in GBW as compared to other compensation schemes is due to the fact that the poles are not split. LHP zeros are used to cancel the phase shift of poles to obtain a good phase margin. The effect of pole–zero mismatches on feed-forward amplifier’s performance was studied and it was shown that the pole–zero cancellation should occur at high frequencies for best settling time performance. Experimental results for the OTAs show fast settling time and good stability. Simulation and experimental results for the amplifier are in accordance with the theoretical derivations. References [1] S.I. Liu, C.H. Kuo, R.Y. Tsai, J. Wu, A double-sampling pseudotwo-path bandpass DS modulator, IEEE J. Solid-State Circuits 35 (2000) 276–280. [2] P. Cusinato, D. Tonietto, F. Stefani, A. Baschirotto, A 3.3-V CMOS 10.7-MHz sixth-order bandpass SD modulator with 74-dB dynamic range, IEEE J. Solid-State Circuits 36 (2001) 629–638. [3] T. Salo, T. Hollman, S. Lindfors, K. Halonen, An 80-MHz 8th order bandpass SD modulator with 75 dB SNDR for IS-95, in: Proceedings of the IEEE Custom Integrated Circuits Conference, 2002, pp. 179–182. [4] B.K. Thandri, J. Silva-Martinez, M.J. Rocha-Perez, J. Wang, A 92 MHz, 80 dB peak SNR SC bandpass SD modulator based on a high GBW OTA with no Miller capacitors in 0.35 mm CMOS technology, in: Proceedings of the IEEE Custom Integrated Circuits Conference, 2003, pp. 123–126. [5] K. Bult, J.G.M. Geelen, A fast-settling CMOS OpAmp for SC circuits with 90-dB DC gain, IEEE J. Solid-State Circuits 25 (6) (1990) 1379–1384. [6] R. Eschauzier, J. Huijsing, Frequency Compensation Techniques for Low-power Operational Amplifiers, Kluwer Academic Publishers, Boston, 1995. [7] P.R. Gray, R.G. Meyer, MOS operational amplifier design—a tutorial overview, IEEE J. Solid-State Circuits SC-17 (6) (1982) 969–982. [8] T. Wakimoto, Y. Akazawa, A low-power wide-band amplifier using a new parasitic capacitance compensation technique, IEEE J. SolidState Circuits 25 (1) (1990) 200–206.
1029
[9] W. Sansen, Z.Y. Chang, Feedforward compensation techniques of CMOS high-frequency amplifiers, IEEE J. Solid-State Circuits 25 (6) (1990) 1590–1595. [10] F. Opt Eynde, W. Sansen, Design and optimization of CMOS wide band amplifiers, in: Proceedings of the IEEE CICC Conference, San Diego, May 1989, pp. 25.7.1–4. [11] J. Silva-Martinez, F. Carreto-Castro, Improving the high-frequency response of the folded-cascode amplifiers, in: IEEE, Proceedings ISCAS-96, vol. 1, 1996, pp. 500–503. [12] C. Toumazou, S. Setty, Feedforward compensation techniques for the design of low-voltage OPAMPs and OTAs, in: IEEE, Proceedings of the ISCAS-98, vol. 1, 1998, p. 464. [13] R.H.M. van Veldhoven, A triple mode continuous-time SD modulator with switched-capacitor feedback DAC for a GSMEDGE/CDMA2000/UMTS receiver, IEEE J. Solid-State Circuits 38 (12) (2003) 2069–2076. [14] S.T. Ryu, S. Ray, B.S. Song, G.H. Cho, K. Bacrania, A 14-b linear capacitor self-trimming pipelined ADC, IEEE J. Solid-State Circuits 39 (11) (2004) 2046–2051. [15] Y.Q. Yan, A. Chokhawala, M. Alexander, J. Melanson, D. Hester, A 114-dB 68-mW chopper-stabilized stereo multibit audio ADC in 5.62 mm2, IEEE J. Solid-State Circuits 38 (12) (2003) 2061–2068. [16] M.D. Pardoe, M.G. Degrauwe, A rail-to-rail input/output CMOS power amplifier, IEEE J. Solid-State Circuits 25 (2) (1990) 501–504. [17] G. Olvera-Romero, J. Silva-Martı´ nez, A folded-cascode OTA for high-frequency applications based on complementary differential pairs, in: Proceedings of the IEEE International Workshop on Mixed-Mode Integrated Circuits and Applications, July 26–29, 1999, pp. 57–60. [18] J. Silva-Martinez, J. Adut, M. Rocha-Perez, A 58 dB SNR 6th order broadband 10.7 MHz SC-ladder filter, in: Proceedings of the IEEE Custom Integrated Circuits Conference, September 2003, pp. 13–16. [19] L. Wang, S.H.K. Embabi, Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper, IEEE J. Solid-State Circuits 38 (8) (2003) 1411–1415. [20] J. Grilo, I. Galton, K. Wang, R.G. Montemayor, A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver, IEEE J. Solid-State Circuits 37 (3) (2003) 271–278. [21] R. Gaggl, A. Wiesbauer, G. Fritz, C. Schranz, P. Pessl, A 85-dB dynamic range multibit delta–sigma ADC for ADSL-CO applications in 0.18-_m CMOS, IEEE J. Solid-State Circuits 38 (7) (2003) 1105–1114. [22] F. You, S.H.K. Embabi, E. Sanchez-Sinencio, A multistage amplifier topology with nested Gm-C compensation for low-voltage application, IEEE J. Solid-State Circuits 32 (1997) 2000–2011. [23] R. Eschauzier, et al., A 100-MHz 100-dB operational amplifier with multipath nested miller compensation structure, IEEE J. Solid-State Circuits 27 (1992) 1709–1717. [24] L. Yao, M.S.J. Steyaert, W. Sansen, A 1-V 140-W 88-dB audio sigma-delta modulator in 90-nm CMOS, IEEE J. Solid-State Circuits 39 (11) (2004) 1809–1818. [25] Y.B. Kamath, R. Meyer, P. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. SolidState Circuits 9 (1974) 347–352. [26] H.C. Yan, D.J. Allstot, Considerations for fast settling operational amplifiers, IEEE Trans. Circuits Syst. 37 (1990) 326–334. [27] U. Chilakapati, T. Fiez, Settling time design considerations for SC integrators, IEEE Trans. Circuits Syst. 46 (Part II) (1999) 810–816. [28] A. Thomsen, A five stage chopper stabilized instrumentation amplifier using feedforward compensation, in: Proceedings of the IEEE Symposium on VLSI circuits, Honolulu, 1998, pp. 220–223. [29] B.K. Thandri, J. Silva-Martinez, A robust feedforward compensation scheme for multi-stage operational transconductance amplifiers with no Miller capacitors, IEEE J. Solid-State Circuits 38 (2003) 237–243.