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An overview to integrated power module design for high power electronics packaging
Microelectronics Reliability 40 (2000) 365±379
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Introductory invited paper
An overview to integrated power module design for high power electronics packaging A.B. Lostetter, F. Barlow*, A. Elshabini 1 Electrical Engineering Department, University of Arkansas, 3217 Bell Engineering Center, Fayettville, AR 72701, USA Received 18 May 1999; received in revised form 2 September 1999
Abstract In recent years, there has been an explosion in demand for smaller and lighter, more ecient, and less expensive power electronic supplies and converters. There are a number of reasons for this recent necessity, ranging from the need for smaller and cheaper power converters for consumer electronics (such as laptop computers and cellular phones) to the need for highly reliable power electronics for such items as satellite and military craft power systems, which are required to be highly ecient, light in weight, smaller in volume, and low cost. This paper discusses the concept of Integrated Power Modules (IPMs), in which the electronic control circuitry and the high power electronics of the converter are integrated into a single compact standardized module. The advantages and disadvantages of such an approach will be discussed in reference to the current industry standard for power electronics design and packaging. The researchers will then take the readers through the IPM design, including basic circuit topology layout, module fabrication processes, and ®nally thermal considerations. # 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction Integrated Power Module (IPM) is a power electronics packaging strategy which extends the concept of Multichip Modules (MCMs) to high power electronics assemblies, with the idea being that the control and power circuitry components are integrated together into a single compact power module. A single high conductivity metal layer is utilized for power routing with multiple copper bonded polymer layers utilized for control signal routing. The circuit topology routing is produced employing basic Printed Circuit
* Corresponding author. E-mail addresses: [email protected] (F. Barlow), [email protected] (A. Elshabini). 1 Also corresponding author.
Board (PCB) etching techniques with surface mount and bare die chip components attached using standard wirebond and surface mount attachment processes. This design approach, which later will be discussed in detail, is an alternative over today's current industry practice.
2. Current industry standard The design and packaging of power converters and power supplies is often a tedious process with a multitude of variables, where few things have been standardized (unlike other electronic ®elds such as digital design). As a result, a signi®cant amount of engineering time and energy is spent in topology design and packaging schemes. The current solution is essentially
0026-2714/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 9 ) 0 0 2 1 9 - X
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Fig. 1. Separation of stages in power design.
the separation of the problems, as illustrated in Fig. 1, by fabricating multiple boards. For the majority of high power applications, the power electronic control circuitry is contained on a separate board (typically PCB) from the high power switching devices (MOSFETs or IGBTs), often time with a third stage containing the power magnetics and ®lters [1,2]. Through this separation, the problems are isolated; the electronics engineer focuses upon the topology of the converter design while the packaging engineer can focus upon, mainly, the thermal problems of the high power switching devices or magnetics. In recent years, a number of companies in the electronics industry have released power modules known as ``bricks'' or ``blocks'', the cross-section of which is illustrated in Fig. 2. These bricks are pre-packaged power stages, typically MOSFETs or IGBTs packaged in a half-bridge or full-bridge con®guration. The bricks are then simply bolted (or bonded) to a heat sink or metal housing, and then electrically attached to the control and ®lter stages of the power converter. Manufacturers of these bricks include companies such as International Recti®er, Fuji, Motorola, and IXYS [3±5]. The advantage of this approach is convincing in terms
of cost. The bricks are an attempt to standardize power electronics design, thus reducing the required time for engineers to focus on electronic packaging and thermal issues. The overall cost in the ®nal converter is reduced with this scheme while reliability of the power stage is improved. The bricks typically rely on Direct Bond Copper (DBC) or Active Metal Braze, since these technologies allow for the thick metallizations necessary for power systems. The DBC substrates typically consist of 25 mil (635, mm) AlN or BeO directly bonded with 12 mil (305 mm) copper plates on either side. Although these approaches are proven performers, there exists a few key short comings; namely, low circuit density and the inability to incorporate ®ne pitch components. This inability to incorporate small components eectively prevents the integration of control and/or protection circuits, since these components require 5±10 mil (125± 255 mm) pitch. A DBC metallization with a thickness of 8±12 mils (200±305 mm) cannot be etched to a ®ne resolution with any reasonable yield, since the trace width to thickness aspect ratio approaches 1 : 1. As a result, the power stage is packaged separately and an additional PCB is normally required to provide the low power circuits. This in turn increases the size and cost of the system while the board-to-board electrical connections introduce undesirable degrading parasitics.
3. IPM strategy A possible solution to these problems is the development of standardized IPMs, which improves upon current industry technologies by extending Multichip Module Laminate (MCM-L) concepts to power electronics packaging. IPMs can be used as the building blocks to a wide variety of power systems, including
Fig. 2. Cross-section of industry standard ``brick''.
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applications such as buck/boost recti®ers and power converters of all types and con®gurations (ac/dc halfbridge and dc/dc full bridge converters to name a few topologies), with variable frequency and/or variable duty cycle control. Engineers can rely upon these power module building blocks by linking them together when designing power systems, thus resulting in increased system reliability and yield with reduced eorts for work and rework, all at an attractive cost. Although the industry is still quite distant from standardizing these IPMs (the eventual goal), it has been shown technologically and economically viable to integrate control circuitry and power circuitry into a single ecient module [6,16±18,29]. SynQor has demonstrated this viability with the recent commercial release of its dc/dc power converter with a 30 A and 3.3 V output, stressing the reliability of the product while reducing the design impact of thermal issues [7].
4. IPM circuit design There are a signi®cant number of dierent circuit topologies and strategies that are used in power electronics circuit design, too many to be covered within the scope of this paper. The basics elements consist of boost and buck conversion (either stepping up or down the voltage and currents), ac/dc and dc/dc conversion, switch topology strategies (half-bridge, fullbridge, single transistor), and type of switching (pulse width modulation (PWM), frequency modulation, zero voltage switching, zero current switching, or a combination thereof) [8,9]. To discuss these concepts in full is beyond the scope of a technical paper; therefore, an overview will be discussed in this paper which gives the engineer the basic understanding of common power switching design. To achieve the objective, half-bridge power converters will be focused upon. The half-bridge topology can be used in a wide range of applications (including both ac/dc and dc/dc converters), it has wide power range applications (utilized in circuits from a few watts to those converting kilowatts), and is fairly simple to discuss to demonstrate the concept. The design of the half-bridge circuit can be divided into three basic stages: switch design, driver and control design, and ®lter and magnetics design. The ®rst choice to make when designing the circuit is to decide what type of switch topology to use (halfbridge, full-bridge, etc.) This choice is typically based upon the required power to be switched, the voltage ratings, and the current ratings. Appropriate IGBTs or Power MOSFETs that fall within the maximum ratings and desired switching speeds must be chosen, and if power diodes are required in the circuit, then those
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diodes should also be selected to perform within the power ratings. IGBTs generally can operate at higher power levels with reduced voltage losses, but Power MOSFETs can operate at much higher frequencies. Therefore, it is important to decide upon the general range of frequency operation when deciding on what type of devices to utilize. As stated previously, the topology of a half-bridge will be selected for the purposes of the examples in this paper. There are a great number of driver and control chips available in power electronics circuit design, and particularly half-bridge drivers. International Recti®er produces the line of IR21xx chips which are halfbridge drivers, and manufacturers such as Unitrode and Motorola produce PWM chips for frequency, duty cycle, and dead time control. Fig. 3 illustrates a typical half-bridge circuit with a control chip and half-bridge driver chip. Important considerations in the circuit design include frequency control, which is designed through the components Rt and Ct : Bypass capacitors are important in the reduction of noise (0.10 mF). Damping of spikes on the half-bridge voltage reference (pin 6 of a chip such as the IR2110) is critical for reliability issues, and it is achieved through the use of Rdamp and Ddamp. The illustrated circuit contains no feedback control, though feedback circuitry can be added and eciently utilized by a UC1825 or similar control chip [10±12]. The ®lter of the electrical circuit is dependent upon the designated applications. It is important to keep in mind during the design phase that the higher the operating frequency, the smaller the size of the ®lter components and magnetics of the circuit. Many of today's circuits employ resonant or quasi-resonant ®lters for zero-voltage or zero-current switching, thereby reducing ineciencies and circuit losses [13±15].
5. IPM fabrication The IPM packaging approach will be explained by referencing a cross-sectional representation of the strategy from Reference, as illustrated in Fig. 4 [19±21]. The foundation of the module is a variation upon the proven strategy of DBC or Insulated Metal Substrates (IMSs) in which conductor traces can be etched from a thick copper plane. This etched DBC or IMS copper plane forms the module's primary power layer upon which the bare die power devices are mounted. A spacer, containing cavities for the power devices, and vias for interconnections, is then attached to the DBC or IMS baseplate. This spacer is fabricated from a number of nonconductive ceramic or polymer layers interlaced with thin copper and adhesive layers (serving as imbedded low power control circuitry). A top cop-
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Fig. 3. Typical half-bridge circuit.
per layer, upon which the low power control and protection devices can be mounted, is then laminated to the spacer. Finally, in order to provide proper thermal management, the entire structure/module is bonded to a copper or Metal Matrix Composite (MMC) heat spreader. The IPM approach allows for signi®cant integration of control and protection circuits from which low power vias can be used to connect the power and control circuitry to provide for electrical drive, protection, and feedback.
5.1. IPM baseplate and heat spreader The IPM baseplate provides the module with the primary power layer, the proper mechanical support, and a low resistance thermal path to the heat spreader and heat sink. Both DBC and IMS technologies have been used to achieve the concept. DBC has the advantage of a higher thermal conductivity, thicker copper traces, but with the disadvantage of higher cost. IMS, on the other hand, has good thermal conductivity and
Fig. 4. Cross-section of IPM.
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Fig. 5. IPM baseplate process.
power handling capabilities, but at a reduced cost when compared to DBC. The baseplate, in either case, consists of two layers of copper separated by an electrically insulating dielectric, as illustrated in Fig. 5. The copper is typically nickel plated to reduce oxidation and improve material adhesion properties. The topside copper is then etched with the power layer circuit topology (using standard PCB etching technology) while the bottom side copper layer is retained as a single copper plane for thermal spreading to the heat spreader. The important characteristics of a thermal heat spreader material are its thermal conductivity and its coecient of thermal expansion (CTE), as illustrated in Table 1. Copper and aluminum are the industry standard heat spreaders due to their high thermal conductivity properties, but in recent years, the popularity of MMCs such as Aluminum Silicon Carbide (AlSiC) and Beryllium±Beryllium Oxide (Be±BeO) have been creating an impact on the commercial market. MMCs are gaining in popularity since they have fairly low CTEs, which are better suited than copper to match the CTE characteristics of silicon, while at the same time retaining high thermal conductivity properties.
Table 1 Material properties Material
CTE (ppm/K)
Thermal conductivity (W/m K)
AlN Al2O3 (96%) AlSiC (60% Al) AlSiC (63% SiC) Aluminum Be±BeO MMC Copper Cu±Mo Cu±W (20% Cu) Diamond Graphite±Cu MMC Gold Invar Kovar Moltbdenum Silicon Silver Solder
3.0±4.0 6.4 12.6 7.9 24 6.8 17 7.2 7.0 0.8±2.0 0±2.0 (Directional)
100±170 35 240 175 (minimum) 226 240 393 197 248 1000±2000 356 (minimum) 317 11 17 143 136 429 50
3.1 5.3 4.9 4.1
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Companies such as Lanxside, Toshiba, and Brush Wellman are experimenting with carbon graphite MMCs, and there has been a recent interest in academia and high performance products involving diamond based materials for use as substrates and heat spreaders. 5.2. IPM spacer and control layers As illustrated in Fig. 6, the spacer is fabricated from multiple layers of a dielectric material which electrically insulates the power layer from the one or more control signal layers. The copper control layers can be interspersed between the multiple dielectric layers of the spacer in order to increase signal density. The dielectric layers can consist of ceramics or polymers, typically tapes, which are
bonded to the copper layers or each other under high temperature and high pressure through the use of adhesive glues, such as WA2 adhesive. Thus, the internal low power interconnects for control and protection circuits can be built directly into the spacer. The researchers utilized Kapton1 as the polymer of choice for the dielectric layer due to its high temperature processing properties. Initially, each copper layer used is bonded to a dielectric sheet and processed independently, utilizing standard PCB processing techniques. Each copper/ dielectric layer is ®rst exposed to a standard electroless nickel (or in some cases nickel/gold) plating process in which the copper metallization is coated with a thin layer of nickel. This plating step reduces the amount of oxidation that forms on the metallization traces, thus improving adhesion and simplifying the surface mount and die attachment processes by allowing ®rm
Fig. 6. IPM spacer process.
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wirebond attachments between the bare die devices and the circuit traces or interconnects. The copper/ dielectric layers are then etched, the control vias drilled (utilizing either a laser or drill press) and plated, the power vias and device cavities cut (utilizing a laser or saw) and the independent copper/dielectric layers laminated together under high temperature and pressure. Finally, the spacer structure is bonded to the baseplate, as illustrated in Fig. 7. 5.3. Devices and components attachment The attachment process is illustrated in Fig. 8. The low power surface mount chips and/or bare die components and devices are re¯ow soldered to the top metallization layer using a high temperature solder paste, such as 96Sn±4Ag at 2218C. The bare die interconnections are performed using 1 mil diameter gold wire and an ultrasonic wirebonder. Power devices are placed in the recessed openings in the spacer and bonded to the DBC or IMS using medium temperature solder preforms, such as 62Sn±36Pb± 2Ag at 1798C. This allows for removal of the bare die power devices (if needed for repair) without disturbing
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the surface control components. The power vias are ®lled by small blocks of metal machined from molybdenum, which are also bonded to the power layer using medium temperature solder preforms. Interconnections to the top surface of the power bare die devices are accomplished using 5 mil (125 mm) diameter aluminum wirebonds. Finally, the entire module is soldered to the heat spreader through the use of a low temperature solder, such as 97In±3Ag at 1438C.
6. Thermal design of IPMs Thermal considerations and proper thermal management in power electronics packages are vital requirements for successful modules. Concerning IPMs, the problem of thermal dissipation and heat transfer is one of the most important issues, and requires signi®cant attention in order to produce functioning reliable packages. The basic problem with thermal design is that the devices and components within a circuit are not ideal; in other words, they have ineciencies which transform some of the electrical energy into undesired ther-
Fig. 7. IPM spacer to baseplate lamination.
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mal energy. The engineer's task is to remove that unwanted thermal energy from the package. The ®rst prime issue is to reduce the total amount of initial thermal energy by creating an ecient circuit design. Typical overall eciencies for power converters range between 80 and 90%, but the more ecient the design, the less encountered the waste to remove from the package. The second immediate issue to recognize is the importance of the circuit layout. Only a few of the components in a converter dissipate large amounts of power, and typically these components merit the focus of the engineer. The power transistors, the power diodes, the transformers, and the inductors are the components that produce large amounts of heat. It is wise when performing circuit layout to distribute these components evenly across the board, so that hot spots do not develop. The real work of thermal management begins with the package design. It should be remembered that thermal energy can be transferred in three fundamental fashions: through conduction, convection, and radiation. In conduction transfer, thermal energy is trans-
ferred through a stationary medium through the vibratory motion of atoms and molecules. In convection transfer, thermal energy is transferred through mass movement (such as a gas or liquid) which is ¯owing around the heat generating object. In radiation transfer, the thermal energy is converted into electromagnetic radiation, which is then absorbed by the surrounding environment [23,24]. In electronic packaging, radiation eects are seldom sucient to cause a noticeable change (with the exception of some space applications) and therefore, conduction and convection will be focused upon. There are a number of parameters, or characteristics, that are involved in the design of a power package. Power dissipation of the components is the most important parameter in this design. Everything in the design is based upon that single parameter. In power electronics, total thermal power dissipation can range anywhere from a few watts to hundreds of watts, and the expected value has great signi®cance in the package design. Another important parameter is maximum operating temperature. For most applications, this maximum temperature is the maximum operating tem-
Fig. 8. IPM device placement process.
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perature of the silicon device junction, typically 1258C. Regardless of the value, it must be known what temperature value cannot be exceeded, and the location of the generated temperature. Thermal conductivity is another important design parameter. Thermal conductivity is a measure of how conducive a material is to transferring thermal energy. It is important to design a power package with materials of high thermal conductivities, which also encourages thermal spreading from the small surface area of the device to the larger surface area of the thermal spreader. The CTE property of materials is a measure of how much a material expands and contracts during heating and cooling. The engineer would like to match the CTEs of the materials within the package in order to reduce stresses between materials, and thus improve the overall reliability [25±27]. And ®nally, it is vital to know how the thermal energy will ultimately be removed from the package. Will the module be bolted to a heat sink? Is it natural air convection cooling? Or is it forced liquid convection cooling? Will the module have no heat sink at all and be packaged within an insulating plastic? These are important questions that must be answered before or during the thermal design process. The two major energy equality equations governing heat transfer are as follows: qx T1 ÿ T2 kA=t
Heat conduction
1
qx T1 ÿ T2 hA=t
Heat
2
convection
where qx k T h A t
heat ¯ow rate (W), thermal conductivity (W/m 8C), temperature (8C), heat transfer coecient (W/m2 8C), surface area (m2), thickness (m).
The IPM is of a stacked con®guration, and as before, the IPMs designed by the researchers will be used as the basis for example. These power electronic packages consist of a power layer upon which the power components (switches and magnetics) are bonded and an electrically insulating spacer consisting of layers of polymers. The disadvantage of this approach is that the polymer spacer also acts as a thermal insulator. This, therefore, constricts heat removal to the surface of the components and through the bottom of the power package. It is thus important to obtain either good air ¯ow across the top of the components, or more importantly, good thermal spreading and conduction through the base of the package to the heat spreader and heat sink. A common approach to thermal design is; given a
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speci®c module structure, maximum operating temperature of a device, and power dissipation of a device, what type of heat sink will be required to maintain reliable functionality? Typically, heat sinks are rated by their thermal resistance, and there will be several ratings, or often a graph, depending on conditions (forced air convection, liquid cooling, etc.). Another approach to thermal design is; given a certain heat sink and condition, module structure, and temperature, how much maximum power can the device dissipate while maintaining functionality? Or a modi®cation of this approach; given power dissipation, at what temperature will the device be running? Another concern in thermal design is how large to make the heat spreader and heat sink. It is important to have adequate thermal dissipation, but overkill leads to waste and expense. It is something to be avoided. These are all common and valid issues, and the design philosophy to these approaches will be discussed in the following sections. 6.1. Thermal resistance Thermal resistance is a concept which is analogous to electrical resistance, obeying the same laws. The heat ¯ow rate qx can be equated to current, temperatures (T ) can be equated to voltages, and t=kA or 1=hA can be equated to resistance. It will be assumed that thermal energy is removed convectively through air ¯ow across the device surfaces, and conductively through to the base of the module and then convectively from the heat sink. In reality, thermal energy is also dissipated through the edges of the package, and to some extent (depending on spacer materials) from the top of the package. One of the tasks of the thermal engineer is to determine the thermal resistances of the electronic package and to minimize these thermal resistances. Fig. 9 illustrates a typical IPM, utilizing DBC with AlN substrate and a AlSiC MMC heat spreader. Also illustrated is the equivalent thermal circuit. Utilizing materials with high thermal conductivities, the engineer can reduce these thermal resistances. Solders, adhesives, thermal glues, voids, rough surfaces, and imperfect bonds all are expected eect package thermal
Fig. 9. IPM thermal example.
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resistances, although they will not be added to the calculations presented in this work. Surface area also has a tremendous eect on thermal resistance. By increasing the amount of spreading that occurs as the thermal energy transfers through a material, the thermal resistance of that portion of the package can be reduced. It is, therefore, desirable to gain considerable spreading.
L2
6.2. Thermal spreading
6.3. Thermal example
A standard simple rule of thumb is that heat spreads through materials at a 458 angle, but sometimes there is a requirement to perform a more detailed analysis. When materials are stacked together, such as is the case with IPMs, the degree of spreading changes as the thermal energy transfers from one material to the next, as thoroughly and in great detail explained in a paper by Nguyen [22]. When two or more materials are stacked, the angle of thermal spreading and surface length of thermal eect are illustrated in Fig. 10, and calculated as follows:
Assuming an IPM is desired with the previously mentioned structure of a DBC, AlN substrate baseplate, and an AlSiC MMC heat spreader, and assuming it is known that the highest concentration of power loss is from the IGBT silicon device. One may ask, what should the steps be in insuring a proper thermal design? The ®rst step in the thermal design is to determine the thermal spreading area at the base of the heat spreader for each of the major power dissipating devices. Thus, the engineer has an idea of the minimum amount of surface distance that should be left between the thermal intensive devices when laying out the circuit. Suppose it is desired to determine the area of thermal eect across the base of a heat spreader from an IGBT device (one of two IGBTs in a halfbridge con®guration) that is approximately 10 mm square, and assuming this is the highest thermal concentration in the package, what is the minimum surface distance that should be placed between the two IGBTs? The solution is to calculate the angle of spreading through each material as well as the surface area at each layer interface. At the ®nal interface between the
aa tanÿ1 ka =kb L2 2tan aa L1
Heat spreading Length of thermal effect
3 4
where aa ka kb L1
angle of thermal spreading through material one (8 angle), thermal conductivity of material one (W/m 8C), thermal conductivity of material two (W/m 8C), length of thermal eect into material one (m), and
length of thermal eect into material two (m)
The quandary that this places the designer in is a need to increase thickness of a layer to increase thermal spreading, but as a result, the thermal resistance of that layer is also increased. The two opposing necessities must be weighed against each other and a compromising solution should be devised by the engineer.
Fig. 10. Thermal spreading.
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spreader and heat sink, the overall area of thermal spreading can be calculated for each device. Finally, the minimum distance between devices can be computed from the area of thermal spreading. The calculations are tabulated in Appendix A. From the calculations, it can be seen for this example that the minimum distance that should be placed between the edges of the two IGBTs is approximately 0.016 m or 16 mm. Designing this minimum distance into the circuit topology layout, the engineer can insure full use and eciency of the heat spreader. The engineer can also through this method, by calculating the areas required for all major thermal components, decide upon the minimum heat spreader size that will be needed for an adequate design. It is noted that thermal sources can be placed closer together than the Lmin calculation, but this will not make full ecient use of spreading and will result in localized hot spots that are of higher temperature than need to be. This is basically a design decision, and often times the layout is limited by the allowed surface area. Space may not be a luxury the designer is given, or the hot spots may be within acceptable temperature ranges. Again, these are decisions that are required by the engineer. Once the engineer has determined the total eective area of heat spreading across the base of the heat spreader, a proper heat sink can be designed for. Continuing the previous example and making the assumption that there are no magnetics or other additional thermal sources in the IPM, how would a proper heat sink be determined? It is important to estimate the amount of thermal energy that is being dissipated into the package in order to calculate the required heat sink to remove that energy. Assuming the half-bridge of this example is switching a total of 3 kW of electrical energy, and assuming approximately 96.6% eciency of the devices (a common assumption for IGBT power switches), then approximately 100 W of thermal energy needs to be removed from the package, 50 W from each of the two IGBT devices. Since the heat is spreading as it transfers through a material, the average cross-sectional area of each material (from the eect of two IGBTs) must ®rst be calculated, followed by the thermal resistances, as tabulated in Appendix B. Rsink 1:0758C/W is the maximum resistance that a desired heat sink can be rated if a maximum operating temperature of the IGBTs is to be kept below 1258C (for this example). A heat sink with a higher resistance value would result in a DT that is larger than 1008C, and thus an operating temperature that is higher than the maximum rating of 1258C would result. A heat sink with a lower resistance value would result in a smaller DT, thus lowering the operating temperature
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below the maximum rating of 1258C. It must again be stated that imperfect bonds, thermal epoxies, solders, etc., add to the overall structure thermal resistance, though such eects have been assumed negligible for the purposes of this example. Another task an engineer may be faced with is, given a speci®c IPM structure and heat sink, what is the maximum temperature that will be reached? Taking the previous example with the same conditions and utilizing a free air convection cooled heat sink, where Rsink 0:408C/W, a solution is devised as calculated in Appendix C of Tmax 49:58C. For more detailed analysis and design, the engineer can then begin computer modeling of the problem to gain a more accurate solution, especially if high performance is required. Fig. 11 illustrates a three-dimensional thermal solution to the previous example performed on FLOTHERM2 software. Thermal analysis programs such as this utilize ®nite analysis methods in a reiterative process to re®ne grid solutions to within acceptable error. Fig. 12 illustrates an experimental thermal map of the IGBT device of the fabricated IPM discussed in this paper. The thermal map was imaged under conditions matching those of the example problem stepped through for the thermal calculations. These ®gures demonstrate an approximate 10% error between the experimental, computer, and calculated temperatures [28].
7. Conclusions This paper has explored an overview to IPM design for high power electronic packaging, a concept which extends the idea of MCMs to high power electronics assemblies by integrating power and control circuitry into a single standard compact module. This approach is a possible alternative to current industry standard practices. Topics covered in this paper include basic switching circuit designs, fabrication processes for IPM construction, and thermal design considerations for heat management. IPMs have the future potential of increasing reliability and performance while simultaneously reducing engineering time, design costs, size, and weight, all through the utilization of existing, low cost, industry standard processes.
Acknowledgements The researchers at the Microelectronics Laboratories of Virginia Polytechnic Institute and State University would like to thank the Oce of Naval Research (ONR) and the IMAPS Educational Foundation for their support towards this project. In addition, the
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Fig. 11. FLOTHERM2 thermal simulation of IPM design.
Fig. 12. Experimental thermal map of IPM power switch.
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researchers would also like to thank International Recti®er, Brush Wellman Industries, and Orthodyne Electronics for their generous materials and assistance.
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L5 2 td tan ad L4 2 6:20 10ÿ3 m 1:06 0:01293 m 0:02607 m 2
A5 L5 2 0:02607 m 0:6796 10ÿ3 m2 Appendix A. Thermal spreading and Lmin
ASpreading 0:6796 10ÿ3 m2 Lmin L5 ÿ L1 1=2 L5 ÿ L1 1=2 0:016 m
L1 0:01 m 2
A1 L1 2 0:01 m 0:10 10ÿ3 m2 aa tanÿ1 ka =kb tanÿ1 393 W=m 8C= 170 W=m 8C 66:618 L2 2 ta tan aa L1 2 0:30 10ÿ3 m 2:31 0:01 m 0:01139 m 2
A2 L2 2 0:01139 m 0:1297 10ÿ3 m2 aa tanÿ1 kb =kc tanÿ1 170 W=m 8C= 393 W=m 8C 23:398 L3 2 tb tan aa L2
Appendix B. Average areas and Rsink
ÿ 2 Aaverage Number of IGBTS 1=2 LTop LBottom 2 2 Aa 2 1=2 L1 L2 2 1=2 0:01 m 0:01139 m 0:2288 10ÿ3 m2 2 Ab 2 1=2 L2 L3 2 2 1=2 0:01139 m 0:01195 m 0:2724 10ÿ3 m2
2 0:65 10ÿ3 m 0:432 0:01139 m 0:01195 m
2 Ac 2 1=2 L3 L4
A3 L3 2 0:01195 m 0:1428 10ÿ3 m2
2 2 1=2 0:01195 m 0:01293 m
ac tanÿ1 kc =kd
0:3096 10ÿ3 m2
2
tanÿ1 393 W=m 8C= 240 W=m 8C 58:598
2 Ad 2 1=2 L4 L5 2 2 1=2 0:01293 m 0:02607 m
L4 2 tc tan ac L3 2 0:30 10ÿ3 m 1:64 0:01195 m 0:01293 m 2
A4 L4 2 0:01293 m 0:1672 10ÿ3 m2 ad tanÿ1 kd =ke tanÿ1 240 W=m 8C= 226 W=m 8C 46:728
0:7606 10ÿ3 m2 Following are the thermal resistance calculations, Rsurface 1= hair A1 2 ÿ 1= 100 W=m2 8C 0:10 10ÿ3 m2 2 508C=W
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Rsink RT Rsurface RT Rstructure Rsurface
Ra ta = ka ÿ Aa ÿ 0:30 10ÿ3 m = 393 W=m 8C 0:2288 10ÿ3 m2
Rstructure = Rsurface ÿ RT 1:08C=W 508C=W 1:08C=W 0:05328C=W
0:00338C=W
508C=W 0:05328C=W = 508C=W ÿ 1:08C=W
Rb tb = kb ÿ Ab ÿ 0:65 10ÿ3 m = 170 W=m 8C 0:2724 10ÿ3 m2 0:01408C=W
Rc tc kc ÿ Ac 0:30 10ÿ3
ÿ m = 393 W=m 8C 0:3096 10ÿ3 m2
0:00258C=W
Rsink 1:0758C=W
Appendix C. Tmax
RT Rsurface == Rstructure Rsink Rsurface Rstructure Rsink = Rsurface Rstructure
Rd td = kd ÿ Ad ÿ 6:20 10ÿ3 m = 240 W=m 8C 0:7606 10ÿ3 m2
Rsink
508C=W 0:05328C=W 0:408C=W =
0:03348C=W
508C=W 0:05328C=W 0:408C=W
Rsink unknown
RT 0:44918C=W
Solving for Rsink,
DT RT qx 0:44918C=W 50 W 22:468C
Rstructure Ra Rb Rc Rd
)
0:00338C=W 0:01408C=W 0:00258C=W 0:03348C=W
Tmax Troom DT 278C 22:468C 49:58C Tmax
0:05328C=W
DTmax Tmax ÿ Troom 1258C ÿ 278C 988C
DTmax RT qx 4 RT DT=qx 988C=100 W 1:08C=W
RT Rsurface == Rstructure Rsink Rsurface Rstructure Rsink = Rsurface Rstructure Rsink
References [1] Godbold C, Sankaran V, Hudgins J. Novel designs in power modules. In: IEEE 30th Industry Applications Conference, Piscataway, NJ. 1995. p. 911±5. [2] Harris Corporation. Power electronic building block. Navy-ARPA-EPRI Joint Technical Review, September 1995. [3] Snook J, Visser R. Direct bond copper (DBCu) technologies. In: IEEE Industries Applications Conference, New York, NY. 1995. [4] FUJI Electric Co. FUJI IGBT modules application manual, 1995. [5] IXYS. IGBT data manual G-series, 1996. [6] Porter E, Ang S, Burgers K, Glover M, Olejniczak K. Miniaturizing power electronics using multichip module
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technology. International Journal of Microcircuits and Electronic Packaging 1997;20(3):397±401. Mannion P. Cool 90% ecient converter delivers 30 A at 3.3 V. Electronic design, February, 1999. pp. 36±40. Brown M. Power supply cookbook. Newton, MA: Butterworth±Heinemann, 1994. Kassakian J, Schlecht M, Verghese G. In: Principles of power electronics. Reading, MA: Addison Wesley, 1992. Unitrode. Applications handbook, 1997. Kiraly L. Solving noise problems in high power, high frequency control IC driven power stages. IR design tips, DT 92-B. Choi C, Wilhelm D. Design checklist for IR21xx control ICs. IR design tips, DT 94-1SA. Wu T, Chen Y. Modeling PWM DC/DC converters out of basic converter units. IEEE Transactions on Power Electronics 1998;13(5):870±1. Bhat A. Analysis and design of a modi®ed series resonant converter. In: Conference Proceedings to Sixth Annual Applied Power Electronics Conference, Dallas, TX. 1991. p. 594±600. Steigerwald R. A comparison of half-bridge resonant converter topologies. IEEE Transactions on Power Electronics 1998;3(2):l74±182. Hoagland R, Lostetter AB, Webster J, Barlow F, Nelson D, Elshabini-Riad A. Electronic packaging for power electronic building blocks. In: Proceedings of GOMAC Conference, March. 1997. p. 433±6. Lostetter AB, Webster J, Hoagland R, Barlow F, Elshabini-Riad A, Nelson D. Materials issues for solutions of power electronic building blocks (PEBB). In: Third International Symposium on Advanced Packaging Materials, Atlanta, Georgia, March. 1997. p. 177±9. Lostetter AB, Webster J, Hoagland R, Barlow F, Elshabini-Riad A. High density power modules: a packaging strategy. In: 1997 ISHM International Symposium on Microelectronics, Philadelphia, PA, October. 1997. p. 102±7. Lostetter AB, Barlow F, Elshabini A. Multilayer interconnects for a high power packaging strategy. In: 1998
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IMAPS International Symposium on Microelectronics, San Diego, CA, November. 1998. p. 330±4. Lostetter AB, Barlow F, Elshabini A. Packaging and thermal analysis of high density power modules. In: Proceedings of the 1998 International Symposium on Microelectronics and Packaging, Israel, June. 1998. p. 92±9. Lostetter AB, Barlow F, Elshabini A. Integrated power modules (IPMs). A novel MCM approach to high power electronics design and packaging. International Journal of Microcircuits and Electronic Packaging 1998;21(3):274±8. Nguyen N. Properly implementing thermal spreading will cut cost while improving device reliability. In: International Symposium on Microelectronics. 1996. p. 383±8. Incropera F, Witt D. Introduction to heat transfer, 2nd ed. New York, NY: Wiley, 1990. Kordyban T. Hot air rises and heat sinks. New York, NY: ASME, 1998. Bruce A Smetana, Giri Venkataramanan. Advanced thermal management for high density distributed power systems. In: HFPC Conference, Ventura, CA, May. 1995. p. 27±32. Sonuparlak, Lehigh M. Design and fabrication of thermal management materials for high performance electronic packages. In: International Symposium on Microelectronics, Minneapolis, MN. 1996. p. 377±82. Premkumar M, Sawtell R. Alcoa's AlSiC cermet technology for microelectronics packaging. Advancing Microelectronics July/August 1995;22(4). Lostetter AB, Barlow F, Elshabini A. Thermal evaluation and comparison study of power baseplate materials. Advancing Microelectronics January/February 1998;25±27. Linden R, Fryho R. Integrated low cost power MCM technology. In: 1998 IMAPS International Symposium on Microelectronics, San Diego, CA, November. 1998. p. 335±40.
www.elsevier.com/locate/microrel
Introductory invited paper
An overview to integrated power module design for high power electronics packaging A.B. Lostetter, F. Barlow*, A. Elshabini 1 Electrical Engineering Department, University of Arkansas, 3217 Bell Engineering Center, Fayettville, AR 72701, USA Received 18 May 1999; received in revised form 2 September 1999
Abstract In recent years, there has been an explosion in demand for smaller and lighter, more ecient, and less expensive power electronic supplies and converters. There are a number of reasons for this recent necessity, ranging from the need for smaller and cheaper power converters for consumer electronics (such as laptop computers and cellular phones) to the need for highly reliable power electronics for such items as satellite and military craft power systems, which are required to be highly ecient, light in weight, smaller in volume, and low cost. This paper discusses the concept of Integrated Power Modules (IPMs), in which the electronic control circuitry and the high power electronics of the converter are integrated into a single compact standardized module. The advantages and disadvantages of such an approach will be discussed in reference to the current industry standard for power electronics design and packaging. The researchers will then take the readers through the IPM design, including basic circuit topology layout, module fabrication processes, and ®nally thermal considerations. # 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction Integrated Power Module (IPM) is a power electronics packaging strategy which extends the concept of Multichip Modules (MCMs) to high power electronics assemblies, with the idea being that the control and power circuitry components are integrated together into a single compact power module. A single high conductivity metal layer is utilized for power routing with multiple copper bonded polymer layers utilized for control signal routing. The circuit topology routing is produced employing basic Printed Circuit
* Corresponding author. E-mail addresses: [email protected] (F. Barlow), [email protected] (A. Elshabini). 1 Also corresponding author.
Board (PCB) etching techniques with surface mount and bare die chip components attached using standard wirebond and surface mount attachment processes. This design approach, which later will be discussed in detail, is an alternative over today's current industry practice.
2. Current industry standard The design and packaging of power converters and power supplies is often a tedious process with a multitude of variables, where few things have been standardized (unlike other electronic ®elds such as digital design). As a result, a signi®cant amount of engineering time and energy is spent in topology design and packaging schemes. The current solution is essentially
0026-2714/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 9 9 ) 0 0 2 1 9 - X
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Fig. 1. Separation of stages in power design.
the separation of the problems, as illustrated in Fig. 1, by fabricating multiple boards. For the majority of high power applications, the power electronic control circuitry is contained on a separate board (typically PCB) from the high power switching devices (MOSFETs or IGBTs), often time with a third stage containing the power magnetics and ®lters [1,2]. Through this separation, the problems are isolated; the electronics engineer focuses upon the topology of the converter design while the packaging engineer can focus upon, mainly, the thermal problems of the high power switching devices or magnetics. In recent years, a number of companies in the electronics industry have released power modules known as ``bricks'' or ``blocks'', the cross-section of which is illustrated in Fig. 2. These bricks are pre-packaged power stages, typically MOSFETs or IGBTs packaged in a half-bridge or full-bridge con®guration. The bricks are then simply bolted (or bonded) to a heat sink or metal housing, and then electrically attached to the control and ®lter stages of the power converter. Manufacturers of these bricks include companies such as International Recti®er, Fuji, Motorola, and IXYS [3±5]. The advantage of this approach is convincing in terms
of cost. The bricks are an attempt to standardize power electronics design, thus reducing the required time for engineers to focus on electronic packaging and thermal issues. The overall cost in the ®nal converter is reduced with this scheme while reliability of the power stage is improved. The bricks typically rely on Direct Bond Copper (DBC) or Active Metal Braze, since these technologies allow for the thick metallizations necessary for power systems. The DBC substrates typically consist of 25 mil (635, mm) AlN or BeO directly bonded with 12 mil (305 mm) copper plates on either side. Although these approaches are proven performers, there exists a few key short comings; namely, low circuit density and the inability to incorporate ®ne pitch components. This inability to incorporate small components eectively prevents the integration of control and/or protection circuits, since these components require 5±10 mil (125± 255 mm) pitch. A DBC metallization with a thickness of 8±12 mils (200±305 mm) cannot be etched to a ®ne resolution with any reasonable yield, since the trace width to thickness aspect ratio approaches 1 : 1. As a result, the power stage is packaged separately and an additional PCB is normally required to provide the low power circuits. This in turn increases the size and cost of the system while the board-to-board electrical connections introduce undesirable degrading parasitics.
3. IPM strategy A possible solution to these problems is the development of standardized IPMs, which improves upon current industry technologies by extending Multichip Module Laminate (MCM-L) concepts to power electronics packaging. IPMs can be used as the building blocks to a wide variety of power systems, including
Fig. 2. Cross-section of industry standard ``brick''.
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applications such as buck/boost recti®ers and power converters of all types and con®gurations (ac/dc halfbridge and dc/dc full bridge converters to name a few topologies), with variable frequency and/or variable duty cycle control. Engineers can rely upon these power module building blocks by linking them together when designing power systems, thus resulting in increased system reliability and yield with reduced eorts for work and rework, all at an attractive cost. Although the industry is still quite distant from standardizing these IPMs (the eventual goal), it has been shown technologically and economically viable to integrate control circuitry and power circuitry into a single ecient module [6,16±18,29]. SynQor has demonstrated this viability with the recent commercial release of its dc/dc power converter with a 30 A and 3.3 V output, stressing the reliability of the product while reducing the design impact of thermal issues [7].
4. IPM circuit design There are a signi®cant number of dierent circuit topologies and strategies that are used in power electronics circuit design, too many to be covered within the scope of this paper. The basics elements consist of boost and buck conversion (either stepping up or down the voltage and currents), ac/dc and dc/dc conversion, switch topology strategies (half-bridge, fullbridge, single transistor), and type of switching (pulse width modulation (PWM), frequency modulation, zero voltage switching, zero current switching, or a combination thereof) [8,9]. To discuss these concepts in full is beyond the scope of a technical paper; therefore, an overview will be discussed in this paper which gives the engineer the basic understanding of common power switching design. To achieve the objective, half-bridge power converters will be focused upon. The half-bridge topology can be used in a wide range of applications (including both ac/dc and dc/dc converters), it has wide power range applications (utilized in circuits from a few watts to those converting kilowatts), and is fairly simple to discuss to demonstrate the concept. The design of the half-bridge circuit can be divided into three basic stages: switch design, driver and control design, and ®lter and magnetics design. The ®rst choice to make when designing the circuit is to decide what type of switch topology to use (halfbridge, full-bridge, etc.) This choice is typically based upon the required power to be switched, the voltage ratings, and the current ratings. Appropriate IGBTs or Power MOSFETs that fall within the maximum ratings and desired switching speeds must be chosen, and if power diodes are required in the circuit, then those
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diodes should also be selected to perform within the power ratings. IGBTs generally can operate at higher power levels with reduced voltage losses, but Power MOSFETs can operate at much higher frequencies. Therefore, it is important to decide upon the general range of frequency operation when deciding on what type of devices to utilize. As stated previously, the topology of a half-bridge will be selected for the purposes of the examples in this paper. There are a great number of driver and control chips available in power electronics circuit design, and particularly half-bridge drivers. International Recti®er produces the line of IR21xx chips which are halfbridge drivers, and manufacturers such as Unitrode and Motorola produce PWM chips for frequency, duty cycle, and dead time control. Fig. 3 illustrates a typical half-bridge circuit with a control chip and half-bridge driver chip. Important considerations in the circuit design include frequency control, which is designed through the components Rt and Ct : Bypass capacitors are important in the reduction of noise (0.10 mF). Damping of spikes on the half-bridge voltage reference (pin 6 of a chip such as the IR2110) is critical for reliability issues, and it is achieved through the use of Rdamp and Ddamp. The illustrated circuit contains no feedback control, though feedback circuitry can be added and eciently utilized by a UC1825 or similar control chip [10±12]. The ®lter of the electrical circuit is dependent upon the designated applications. It is important to keep in mind during the design phase that the higher the operating frequency, the smaller the size of the ®lter components and magnetics of the circuit. Many of today's circuits employ resonant or quasi-resonant ®lters for zero-voltage or zero-current switching, thereby reducing ineciencies and circuit losses [13±15].
5. IPM fabrication The IPM packaging approach will be explained by referencing a cross-sectional representation of the strategy from Reference, as illustrated in Fig. 4 [19±21]. The foundation of the module is a variation upon the proven strategy of DBC or Insulated Metal Substrates (IMSs) in which conductor traces can be etched from a thick copper plane. This etched DBC or IMS copper plane forms the module's primary power layer upon which the bare die power devices are mounted. A spacer, containing cavities for the power devices, and vias for interconnections, is then attached to the DBC or IMS baseplate. This spacer is fabricated from a number of nonconductive ceramic or polymer layers interlaced with thin copper and adhesive layers (serving as imbedded low power control circuitry). A top cop-
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Fig. 3. Typical half-bridge circuit.
per layer, upon which the low power control and protection devices can be mounted, is then laminated to the spacer. Finally, in order to provide proper thermal management, the entire structure/module is bonded to a copper or Metal Matrix Composite (MMC) heat spreader. The IPM approach allows for signi®cant integration of control and protection circuits from which low power vias can be used to connect the power and control circuitry to provide for electrical drive, protection, and feedback.
5.1. IPM baseplate and heat spreader The IPM baseplate provides the module with the primary power layer, the proper mechanical support, and a low resistance thermal path to the heat spreader and heat sink. Both DBC and IMS technologies have been used to achieve the concept. DBC has the advantage of a higher thermal conductivity, thicker copper traces, but with the disadvantage of higher cost. IMS, on the other hand, has good thermal conductivity and
Fig. 4. Cross-section of IPM.
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Fig. 5. IPM baseplate process.
power handling capabilities, but at a reduced cost when compared to DBC. The baseplate, in either case, consists of two layers of copper separated by an electrically insulating dielectric, as illustrated in Fig. 5. The copper is typically nickel plated to reduce oxidation and improve material adhesion properties. The topside copper is then etched with the power layer circuit topology (using standard PCB etching technology) while the bottom side copper layer is retained as a single copper plane for thermal spreading to the heat spreader. The important characteristics of a thermal heat spreader material are its thermal conductivity and its coecient of thermal expansion (CTE), as illustrated in Table 1. Copper and aluminum are the industry standard heat spreaders due to their high thermal conductivity properties, but in recent years, the popularity of MMCs such as Aluminum Silicon Carbide (AlSiC) and Beryllium±Beryllium Oxide (Be±BeO) have been creating an impact on the commercial market. MMCs are gaining in popularity since they have fairly low CTEs, which are better suited than copper to match the CTE characteristics of silicon, while at the same time retaining high thermal conductivity properties.
Table 1 Material properties Material
CTE (ppm/K)
Thermal conductivity (W/m K)
AlN Al2O3 (96%) AlSiC (60% Al) AlSiC (63% SiC) Aluminum Be±BeO MMC Copper Cu±Mo Cu±W (20% Cu) Diamond Graphite±Cu MMC Gold Invar Kovar Moltbdenum Silicon Silver Solder
3.0±4.0 6.4 12.6 7.9 24 6.8 17 7.2 7.0 0.8±2.0 0±2.0 (Directional)
100±170 35 240 175 (minimum) 226 240 393 197 248 1000±2000 356 (minimum) 317 11 17 143 136 429 50
3.1 5.3 4.9 4.1
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Companies such as Lanxside, Toshiba, and Brush Wellman are experimenting with carbon graphite MMCs, and there has been a recent interest in academia and high performance products involving diamond based materials for use as substrates and heat spreaders. 5.2. IPM spacer and control layers As illustrated in Fig. 6, the spacer is fabricated from multiple layers of a dielectric material which electrically insulates the power layer from the one or more control signal layers. The copper control layers can be interspersed between the multiple dielectric layers of the spacer in order to increase signal density. The dielectric layers can consist of ceramics or polymers, typically tapes, which are
bonded to the copper layers or each other under high temperature and high pressure through the use of adhesive glues, such as WA2 adhesive. Thus, the internal low power interconnects for control and protection circuits can be built directly into the spacer. The researchers utilized Kapton1 as the polymer of choice for the dielectric layer due to its high temperature processing properties. Initially, each copper layer used is bonded to a dielectric sheet and processed independently, utilizing standard PCB processing techniques. Each copper/ dielectric layer is ®rst exposed to a standard electroless nickel (or in some cases nickel/gold) plating process in which the copper metallization is coated with a thin layer of nickel. This plating step reduces the amount of oxidation that forms on the metallization traces, thus improving adhesion and simplifying the surface mount and die attachment processes by allowing ®rm
Fig. 6. IPM spacer process.
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wirebond attachments between the bare die devices and the circuit traces or interconnects. The copper/ dielectric layers are then etched, the control vias drilled (utilizing either a laser or drill press) and plated, the power vias and device cavities cut (utilizing a laser or saw) and the independent copper/dielectric layers laminated together under high temperature and pressure. Finally, the spacer structure is bonded to the baseplate, as illustrated in Fig. 7. 5.3. Devices and components attachment The attachment process is illustrated in Fig. 8. The low power surface mount chips and/or bare die components and devices are re¯ow soldered to the top metallization layer using a high temperature solder paste, such as 96Sn±4Ag at 2218C. The bare die interconnections are performed using 1 mil diameter gold wire and an ultrasonic wirebonder. Power devices are placed in the recessed openings in the spacer and bonded to the DBC or IMS using medium temperature solder preforms, such as 62Sn±36Pb± 2Ag at 1798C. This allows for removal of the bare die power devices (if needed for repair) without disturbing
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the surface control components. The power vias are ®lled by small blocks of metal machined from molybdenum, which are also bonded to the power layer using medium temperature solder preforms. Interconnections to the top surface of the power bare die devices are accomplished using 5 mil (125 mm) diameter aluminum wirebonds. Finally, the entire module is soldered to the heat spreader through the use of a low temperature solder, such as 97In±3Ag at 1438C.
6. Thermal design of IPMs Thermal considerations and proper thermal management in power electronics packages are vital requirements for successful modules. Concerning IPMs, the problem of thermal dissipation and heat transfer is one of the most important issues, and requires signi®cant attention in order to produce functioning reliable packages. The basic problem with thermal design is that the devices and components within a circuit are not ideal; in other words, they have ineciencies which transform some of the electrical energy into undesired ther-
Fig. 7. IPM spacer to baseplate lamination.
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mal energy. The engineer's task is to remove that unwanted thermal energy from the package. The ®rst prime issue is to reduce the total amount of initial thermal energy by creating an ecient circuit design. Typical overall eciencies for power converters range between 80 and 90%, but the more ecient the design, the less encountered the waste to remove from the package. The second immediate issue to recognize is the importance of the circuit layout. Only a few of the components in a converter dissipate large amounts of power, and typically these components merit the focus of the engineer. The power transistors, the power diodes, the transformers, and the inductors are the components that produce large amounts of heat. It is wise when performing circuit layout to distribute these components evenly across the board, so that hot spots do not develop. The real work of thermal management begins with the package design. It should be remembered that thermal energy can be transferred in three fundamental fashions: through conduction, convection, and radiation. In conduction transfer, thermal energy is trans-
ferred through a stationary medium through the vibratory motion of atoms and molecules. In convection transfer, thermal energy is transferred through mass movement (such as a gas or liquid) which is ¯owing around the heat generating object. In radiation transfer, the thermal energy is converted into electromagnetic radiation, which is then absorbed by the surrounding environment [23,24]. In electronic packaging, radiation eects are seldom sucient to cause a noticeable change (with the exception of some space applications) and therefore, conduction and convection will be focused upon. There are a number of parameters, or characteristics, that are involved in the design of a power package. Power dissipation of the components is the most important parameter in this design. Everything in the design is based upon that single parameter. In power electronics, total thermal power dissipation can range anywhere from a few watts to hundreds of watts, and the expected value has great signi®cance in the package design. Another important parameter is maximum operating temperature. For most applications, this maximum temperature is the maximum operating tem-
Fig. 8. IPM device placement process.
A.B. Lostetter et al. / Microelectronics Reliability 40 (2000) 365±379
perature of the silicon device junction, typically 1258C. Regardless of the value, it must be known what temperature value cannot be exceeded, and the location of the generated temperature. Thermal conductivity is another important design parameter. Thermal conductivity is a measure of how conducive a material is to transferring thermal energy. It is important to design a power package with materials of high thermal conductivities, which also encourages thermal spreading from the small surface area of the device to the larger surface area of the thermal spreader. The CTE property of materials is a measure of how much a material expands and contracts during heating and cooling. The engineer would like to match the CTEs of the materials within the package in order to reduce stresses between materials, and thus improve the overall reliability [25±27]. And ®nally, it is vital to know how the thermal energy will ultimately be removed from the package. Will the module be bolted to a heat sink? Is it natural air convection cooling? Or is it forced liquid convection cooling? Will the module have no heat sink at all and be packaged within an insulating plastic? These are important questions that must be answered before or during the thermal design process. The two major energy equality equations governing heat transfer are as follows: qx T1 ÿ T2 kA=t
Heat conduction
1
qx T1 ÿ T2 hA=t
Heat
2
convection
where qx k T h A t
heat ¯ow rate (W), thermal conductivity (W/m 8C), temperature (8C), heat transfer coecient (W/m2 8C), surface area (m2), thickness (m).
The IPM is of a stacked con®guration, and as before, the IPMs designed by the researchers will be used as the basis for example. These power electronic packages consist of a power layer upon which the power components (switches and magnetics) are bonded and an electrically insulating spacer consisting of layers of polymers. The disadvantage of this approach is that the polymer spacer also acts as a thermal insulator. This, therefore, constricts heat removal to the surface of the components and through the bottom of the power package. It is thus important to obtain either good air ¯ow across the top of the components, or more importantly, good thermal spreading and conduction through the base of the package to the heat spreader and heat sink. A common approach to thermal design is; given a
373
speci®c module structure, maximum operating temperature of a device, and power dissipation of a device, what type of heat sink will be required to maintain reliable functionality? Typically, heat sinks are rated by their thermal resistance, and there will be several ratings, or often a graph, depending on conditions (forced air convection, liquid cooling, etc.). Another approach to thermal design is; given a certain heat sink and condition, module structure, and temperature, how much maximum power can the device dissipate while maintaining functionality? Or a modi®cation of this approach; given power dissipation, at what temperature will the device be running? Another concern in thermal design is how large to make the heat spreader and heat sink. It is important to have adequate thermal dissipation, but overkill leads to waste and expense. It is something to be avoided. These are all common and valid issues, and the design philosophy to these approaches will be discussed in the following sections. 6.1. Thermal resistance Thermal resistance is a concept which is analogous to electrical resistance, obeying the same laws. The heat ¯ow rate qx can be equated to current, temperatures (T ) can be equated to voltages, and t=kA or 1=hA can be equated to resistance. It will be assumed that thermal energy is removed convectively through air ¯ow across the device surfaces, and conductively through to the base of the module and then convectively from the heat sink. In reality, thermal energy is also dissipated through the edges of the package, and to some extent (depending on spacer materials) from the top of the package. One of the tasks of the thermal engineer is to determine the thermal resistances of the electronic package and to minimize these thermal resistances. Fig. 9 illustrates a typical IPM, utilizing DBC with AlN substrate and a AlSiC MMC heat spreader. Also illustrated is the equivalent thermal circuit. Utilizing materials with high thermal conductivities, the engineer can reduce these thermal resistances. Solders, adhesives, thermal glues, voids, rough surfaces, and imperfect bonds all are expected eect package thermal
Fig. 9. IPM thermal example.
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resistances, although they will not be added to the calculations presented in this work. Surface area also has a tremendous eect on thermal resistance. By increasing the amount of spreading that occurs as the thermal energy transfers through a material, the thermal resistance of that portion of the package can be reduced. It is, therefore, desirable to gain considerable spreading.
L2
6.2. Thermal spreading
6.3. Thermal example
A standard simple rule of thumb is that heat spreads through materials at a 458 angle, but sometimes there is a requirement to perform a more detailed analysis. When materials are stacked together, such as is the case with IPMs, the degree of spreading changes as the thermal energy transfers from one material to the next, as thoroughly and in great detail explained in a paper by Nguyen [22]. When two or more materials are stacked, the angle of thermal spreading and surface length of thermal eect are illustrated in Fig. 10, and calculated as follows:
Assuming an IPM is desired with the previously mentioned structure of a DBC, AlN substrate baseplate, and an AlSiC MMC heat spreader, and assuming it is known that the highest concentration of power loss is from the IGBT silicon device. One may ask, what should the steps be in insuring a proper thermal design? The ®rst step in the thermal design is to determine the thermal spreading area at the base of the heat spreader for each of the major power dissipating devices. Thus, the engineer has an idea of the minimum amount of surface distance that should be left between the thermal intensive devices when laying out the circuit. Suppose it is desired to determine the area of thermal eect across the base of a heat spreader from an IGBT device (one of two IGBTs in a halfbridge con®guration) that is approximately 10 mm square, and assuming this is the highest thermal concentration in the package, what is the minimum surface distance that should be placed between the two IGBTs? The solution is to calculate the angle of spreading through each material as well as the surface area at each layer interface. At the ®nal interface between the
aa tanÿ1 ka =kb L2 2tan aa L1
Heat spreading Length of thermal effect
3 4
where aa ka kb L1
angle of thermal spreading through material one (8 angle), thermal conductivity of material one (W/m 8C), thermal conductivity of material two (W/m 8C), length of thermal eect into material one (m), and
length of thermal eect into material two (m)
The quandary that this places the designer in is a need to increase thickness of a layer to increase thermal spreading, but as a result, the thermal resistance of that layer is also increased. The two opposing necessities must be weighed against each other and a compromising solution should be devised by the engineer.
Fig. 10. Thermal spreading.
A.B. Lostetter et al. / Microelectronics Reliability 40 (2000) 365±379
spreader and heat sink, the overall area of thermal spreading can be calculated for each device. Finally, the minimum distance between devices can be computed from the area of thermal spreading. The calculations are tabulated in Appendix A. From the calculations, it can be seen for this example that the minimum distance that should be placed between the edges of the two IGBTs is approximately 0.016 m or 16 mm. Designing this minimum distance into the circuit topology layout, the engineer can insure full use and eciency of the heat spreader. The engineer can also through this method, by calculating the areas required for all major thermal components, decide upon the minimum heat spreader size that will be needed for an adequate design. It is noted that thermal sources can be placed closer together than the Lmin calculation, but this will not make full ecient use of spreading and will result in localized hot spots that are of higher temperature than need to be. This is basically a design decision, and often times the layout is limited by the allowed surface area. Space may not be a luxury the designer is given, or the hot spots may be within acceptable temperature ranges. Again, these are decisions that are required by the engineer. Once the engineer has determined the total eective area of heat spreading across the base of the heat spreader, a proper heat sink can be designed for. Continuing the previous example and making the assumption that there are no magnetics or other additional thermal sources in the IPM, how would a proper heat sink be determined? It is important to estimate the amount of thermal energy that is being dissipated into the package in order to calculate the required heat sink to remove that energy. Assuming the half-bridge of this example is switching a total of 3 kW of electrical energy, and assuming approximately 96.6% eciency of the devices (a common assumption for IGBT power switches), then approximately 100 W of thermal energy needs to be removed from the package, 50 W from each of the two IGBT devices. Since the heat is spreading as it transfers through a material, the average cross-sectional area of each material (from the eect of two IGBTs) must ®rst be calculated, followed by the thermal resistances, as tabulated in Appendix B. Rsink 1:0758C/W is the maximum resistance that a desired heat sink can be rated if a maximum operating temperature of the IGBTs is to be kept below 1258C (for this example). A heat sink with a higher resistance value would result in a DT that is larger than 1008C, and thus an operating temperature that is higher than the maximum rating of 1258C would result. A heat sink with a lower resistance value would result in a smaller DT, thus lowering the operating temperature
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below the maximum rating of 1258C. It must again be stated that imperfect bonds, thermal epoxies, solders, etc., add to the overall structure thermal resistance, though such eects have been assumed negligible for the purposes of this example. Another task an engineer may be faced with is, given a speci®c IPM structure and heat sink, what is the maximum temperature that will be reached? Taking the previous example with the same conditions and utilizing a free air convection cooled heat sink, where Rsink 0:408C/W, a solution is devised as calculated in Appendix C of Tmax 49:58C. For more detailed analysis and design, the engineer can then begin computer modeling of the problem to gain a more accurate solution, especially if high performance is required. Fig. 11 illustrates a three-dimensional thermal solution to the previous example performed on FLOTHERM2 software. Thermal analysis programs such as this utilize ®nite analysis methods in a reiterative process to re®ne grid solutions to within acceptable error. Fig. 12 illustrates an experimental thermal map of the IGBT device of the fabricated IPM discussed in this paper. The thermal map was imaged under conditions matching those of the example problem stepped through for the thermal calculations. These ®gures demonstrate an approximate 10% error between the experimental, computer, and calculated temperatures [28].
7. Conclusions This paper has explored an overview to IPM design for high power electronic packaging, a concept which extends the idea of MCMs to high power electronics assemblies by integrating power and control circuitry into a single standard compact module. This approach is a possible alternative to current industry standard practices. Topics covered in this paper include basic switching circuit designs, fabrication processes for IPM construction, and thermal design considerations for heat management. IPMs have the future potential of increasing reliability and performance while simultaneously reducing engineering time, design costs, size, and weight, all through the utilization of existing, low cost, industry standard processes.
Acknowledgements The researchers at the Microelectronics Laboratories of Virginia Polytechnic Institute and State University would like to thank the Oce of Naval Research (ONR) and the IMAPS Educational Foundation for their support towards this project. In addition, the
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Fig. 11. FLOTHERM2 thermal simulation of IPM design.
Fig. 12. Experimental thermal map of IPM power switch.
A.B. Lostetter et al. / Microelectronics Reliability 40 (2000) 365±379
researchers would also like to thank International Recti®er, Brush Wellman Industries, and Orthodyne Electronics for their generous materials and assistance.
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L5 2 td tan ad L4 2 6:20 10ÿ3 m 1:06 0:01293 m 0:02607 m 2
A5 L5 2 0:02607 m 0:6796 10ÿ3 m2 Appendix A. Thermal spreading and Lmin
ASpreading 0:6796 10ÿ3 m2 Lmin L5 ÿ L1 1=2 L5 ÿ L1 1=2 0:016 m
L1 0:01 m 2
A1 L1 2 0:01 m 0:10 10ÿ3 m2 aa tanÿ1 ka =kb tanÿ1 393 W=m 8C= 170 W=m 8C 66:618 L2 2 ta tan aa L1 2 0:30 10ÿ3 m 2:31 0:01 m 0:01139 m 2
A2 L2 2 0:01139 m 0:1297 10ÿ3 m2 aa tanÿ1 kb =kc tanÿ1 170 W=m 8C= 393 W=m 8C 23:398 L3 2 tb tan aa L2
Appendix B. Average areas and Rsink
ÿ 2 Aaverage Number of IGBTS 1=2 LTop LBottom 2 2 Aa 2 1=2 L1 L2 2 1=2 0:01 m 0:01139 m 0:2288 10ÿ3 m2 2 Ab 2 1=2 L2 L3 2 2 1=2 0:01139 m 0:01195 m 0:2724 10ÿ3 m2
2 0:65 10ÿ3 m 0:432 0:01139 m 0:01195 m
2 Ac 2 1=2 L3 L4
A3 L3 2 0:01195 m 0:1428 10ÿ3 m2
2 2 1=2 0:01195 m 0:01293 m
ac tanÿ1 kc =kd
0:3096 10ÿ3 m2
2
tanÿ1 393 W=m 8C= 240 W=m 8C 58:598
2 Ad 2 1=2 L4 L5 2 2 1=2 0:01293 m 0:02607 m
L4 2 tc tan ac L3 2 0:30 10ÿ3 m 1:64 0:01195 m 0:01293 m 2
A4 L4 2 0:01293 m 0:1672 10ÿ3 m2 ad tanÿ1 kd =ke tanÿ1 240 W=m 8C= 226 W=m 8C 46:728
0:7606 10ÿ3 m2 Following are the thermal resistance calculations, Rsurface 1= hair A1 2 ÿ 1= 100 W=m2 8C 0:10 10ÿ3 m2 2 508C=W
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Rsink RT Rsurface RT Rstructure Rsurface
Ra ta = ka ÿ Aa ÿ 0:30 10ÿ3 m = 393 W=m 8C 0:2288 10ÿ3 m2
Rstructure = Rsurface ÿ RT 1:08C=W 508C=W 1:08C=W 0:05328C=W
0:00338C=W
508C=W 0:05328C=W = 508C=W ÿ 1:08C=W
Rb tb = kb ÿ Ab ÿ 0:65 10ÿ3 m = 170 W=m 8C 0:2724 10ÿ3 m2 0:01408C=W
Rc tc kc ÿ Ac 0:30 10ÿ3
ÿ m = 393 W=m 8C 0:3096 10ÿ3 m2
0:00258C=W
Rsink 1:0758C=W
Appendix C. Tmax
RT Rsurface == Rstructure Rsink Rsurface Rstructure Rsink = Rsurface Rstructure
Rd td = kd ÿ Ad ÿ 6:20 10ÿ3 m = 240 W=m 8C 0:7606 10ÿ3 m2
Rsink
508C=W 0:05328C=W 0:408C=W =
0:03348C=W
508C=W 0:05328C=W 0:408C=W
Rsink unknown
RT 0:44918C=W
Solving for Rsink,
DT RT qx 0:44918C=W 50 W 22:468C
Rstructure Ra Rb Rc Rd
)
0:00338C=W 0:01408C=W 0:00258C=W 0:03348C=W
Tmax Troom DT 278C 22:468C 49:58C Tmax
0:05328C=W
DTmax Tmax ÿ Troom 1258C ÿ 278C 988C
DTmax RT qx 4 RT DT=qx 988C=100 W 1:08C=W
RT Rsurface == Rstructure Rsink Rsurface Rstructure Rsink = Rsurface Rstructure Rsink
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