An RRAM-based MLC design approach

Microelectronics Journal 64 (2017) 9–18

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MARK

An RRAM-based MLC design approach A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

⁎

Dept. of E. E., School of Engineering, Shahed University, Tehran, Iran

A R T I C L E I N F O

A B S T R A C T

Keywords: Attached capacitor based design Memristor MLC RRAM Stanford and Peking-Stanford RRAM models

RRAM is an emerging technology with vast applications in computation and storage. RRAM with MLC capabilities is more interesting owing to its higher storage density. In this study, we proposed an approach for RRAM-based MLC design. The approach starts with capacitor-based quantization of electric charge applying to RRAM. Numerical characterizations of a unit-circuit, including RRAM, capacitor and one MOS transistor were used. Two Stanford and Peking-Stanford RRAM models were employed in this study. The proposed design results in simplified circuitry and avoids power hungry elements (e.g. Op-Amp). A detailed RRAM-based MLC memory array is implemented. To simplify the memory read process, a TIQ-ADC is employed. To evaluate the approach, circuit-level mixed SPICE/Verilog-A simulations were performed. The variation and random effects are experimented using Monte-Carlo simulations. The costs of the proposed approach are design-time precomputation and complexity of one-time device characterization.

1. Introduction Resistive random-access memory (RRAM) is a physical realization of memristor [1]. The memristor and RRAM are directional devices and their symbol is illustrated in Fig. 1. This device is studied as a promising replacement for the next-generation of non-volatile memories (NVM) [2]. Conventional NVMs, such as NAND flash memories, are chargestorage devices [3], but RRAMs are gap length state dependent nonvolatile resistive devices. RRAM as a storage element has advantages against charge-storage memories, including faster read/write speed, longer data retention, better scalability, higher endurance and lower power consumption [4]. Regardless of storage technology, the multilevel cell (MLC) is demanded to improve the storage density while cutting the price per bit [5]. One of the factors which is intended as the desirability factor of a memory technology is its MLC capability, and it is necessary to note that MLC needs more complicated read/write algorithm and peripherals. Considering RRAM characteristics, it was revealed that MLC implementation of this technology could be easier than conventional ones [6]. It has been demonstrated that RRAM, as a future memory candidate, has advantages in MLC applications. The RRAM-based MLC memory researches are grouped into two main branches. The first involves device fabrication and material-related topics, while the second is more focused on system-level issues. Most of the researches in the fabrication field are on Titanium Dioxide, and Hafnium Oxide based RRAMs and there are reports of successful fabrications of MLC employing other materials [7]. Regular RRAMs suffer from endurance and reliability ⁎

with stochastic behavior [8]. These are the main barriers when using traditional RRAMs in MLC applications. Therefore, the material science is playing a crucial role, for instance; it has been demonstrated that number of oxygen vacancies in switching layer can be utilized to enhance the variability [9] or replacing nitrogen instead of oxygen comes with more advantage [10]. Filamentary RRAM, which is considered as RRAM with higher stochastic behavior, can be modified based on engineered layer structure to results in successful 3-bit MLC [11,12]. On the other hand, from the system-level perspective, the effort is mostly on benefits and usage of RRAM-based MLC read/write circuitry [13] and RRAM modeling, optimizations and fault [14]. In this study, we want to present an RRAM based MLC design approach employing realistic RRAM models. Selected models are Stanford RRAM model ver.1 [15] and Peking-Stanford RRAM model ver.2 [16]. The former is a one dimensional (1D) model and shows a fair fit into TiOx based RRAM characteristic curves [17]. The later is a two dimensional (2D) model and successfully fits into both TiOx and HfOx based RRAMs [18]. Conventionally, RRAM setting is conducted in time domain employing continuous or pulse trained voltage or current sources. When the RRAM is used in analog-like applications the usage of slow and power hungry analog devices (e.g. comparators) is unavoidable in time-based approaches [19]. This requirement is due to RRAM's complicated dynamic behavior. We previously proposed an approach called attached capacitor-based design [20]. The main idea behind this method is to cope with dynamic nature of the RRAM. This approach is employed to involve time domain effects inside characteristic curves.

Corresponding author. E-mail address: [email protected] (M.B. Ghaznavi-Ghoushchi).

http://dx.doi.org/10.1016/j.mejo.2017.03.014 Received 29 July 2016; Received in revised form 24 November 2016; Accepted 31 March 2017 0026-2692/ © 2017 Elsevier Ltd. All rights reserved.

Microelectronics Journal 64 (2017) 9–18

A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 1. Memristor symbol and polarity.

For this purpose, we established our approach on numerical characterizations of a unit circuit, which includes all the dynamic behaviors. The read/write circuits of MLC memory are proposed based on characteristic curves and circuit level constraints. We employed Threshold Inverter Quantization (TIQ) based analog to digital converter (ADC) in digital output generation [21]. This technique simplifies analog to digital conversions, while inserting a new constraint into design approach. The reset of paper is organized as follows: In Section 2, we will discuss required backgrounds about RRAM and related works. Third section is dedicated to our work, including characterization and main circuit design. In Section 4, simulation results are shown and finally a conclusion is given in section 5.

Fig. 2. RRAM structure.

tunneling from cathode to anode, 4- tunneling from cathode to traps, 5- emission from trap to conduction band, 6- F–N-like tunneling from trap to conduction band, 7- trap to trap tunneling, 8-tunneling from traps to anode [32]. 2.3. RRAM models Because we want to obtain the most realistic results in a circuit level design, so we need to utilize accurate available device models. Two models employed within this paper could represent TiOx and HfOx based RRAMs. These models encountered dynamic temperature and device variability. Position of the oxygen ions inside insulator of MIM structure enact as the device state. In case of TiOx, the gap length is the state variable, and moving of oxygen ions, due to applied electric field, modifies it. With respect to major effect of gap length, one dimensional model leads to an acceptable approximation. In HfOx based devices, alongside gap length, diameter of conductive filament (CF) plays an important role; so, at least, a 2D model is required. The first model used in this paper is Stanford RRAM model with the current and gap dynamic equation as shown in (1). Tunneling effects are the conduction mechanisms which form the current equation. The dynamic equation is the result of the oxygen ions movements and generation- recombination of vacancies [17]. In these equations, g and V are the gap length and voltage over device electrodes, respectively. In addition, V0, I0 and g0 are the fitting parameters, ν0 is a velocity, which includes the attempt-to-escape frequency, Ea is the activation energy, a is the hopping site distance and L is the device thickness.

2. Background In this section, a brief introduction about memristor and RRAM is presented, then two used RRAM models are discussed with more details, and finally a review on MLC and RRAM-based MLCs is presented. 2.1. Memristor Memristor was introduced in 1971 as a passive circuit element, which explains missing linkage between flux and charge [22]. According to generalization of memristor, the main fingerprint of a memristor is in origin-pinched hysteresis V-I curve, which leads to discrimination of four classes of memristive devices [23]. In line with generalized memristor definition, Phase Change Memory (PCM), Magnetoresistive RAM (MRAM), Conductive Bridging RAM (CBRAM) and RRAM, are some sample of memristor's realization [24]. A comparison among emerging NVM technologies reveals that RRAM has advantages, such as scalability, power consumption, CMOS compatibility and noise immunity. RRAM has MLC capability due to the large ratio between Low Resistivity State (LRS) and High Resistivity State (HRS). Low and high resistivity states can also be referred to as SET and RESET state, respectively.

⎧ ⎛ −g ⎞ ⎛ V ⎞ dg ⎛ qaγV ⎞ ⎛ −Ea, m ⎞ ⎨I (g , V ) = I0 exp ⎜ ⎟ sinh ⎜ ⎟ = v0 exp ⎜ ⎟ sinh ⎜ ⎟ ⎝ LkT ⎠ ⎝ kT ⎠ ⎝ V0 ⎠ dt ⎝ g0 ⎠ ⎩ ⎪ ⎪

(1) A concept called minimum field (Fmin) is define in this model. It represents, minimum required electric field for ion movement. This parameter is a function of both applied voltage across RRAM electrodes and gap length. Peking-Stanford RRAM model is more accurate and includes parasitic resistors and capacitors, tunneling current between top and bottom metal plates and the role of CF diameter in the total current. In the current equation of this model (2), x is the gap length, w is the filament diameter, V is applied voltage over electrodes, xT and VT are the characteristics of length and voltages, WCF is the maximum diameter of CF, RCF is a rough approximation of device resistance which is a function of x and w, L0 is thickness of active area and finally I1 is the independent gap length passing current between electrodes.

2.2. RRAM An RRAM is a metal-insulator-metal (MIM) structure, in which the position of ions inside the crystal defines its state. The electrical equation of such a device was first introduced in 1940 [25]. Event of changing a nominally insulator into a conductor in a MIM structure has been reported several times in 1960s [26,27]. Resistive switching devices were considered to be used in memory applications and so RRAMs attracted more interest in 2000s [28,29] and finally the first RRAM-based memory in a 1T1R structure was reported in 2004 [30]. Conventionally, RRAM is utilized as a binary memory with two states as HRS and LRS with two processes of “set” and “reset”, which refers to switching from HRS to LRS and reverse process, respectively. The simplified structure of RRAM and required voltage polarity to place device in LRS and HRS is illustrated in Fig. 2. The black dots indicate position of ions inside insulator. In set operation, the atoms of oxygen which have been knocked out of lattice during formation process, drift toward anode (bottom) electrode and the opposite event occurs in reset. The movement of ions inside lattice is due to high electric field [31]. The possible electron conduction mechanism in a MIM structure could be named as: 1Schottky emission, 2- Fowler–Nordheim (F-N) tunneling, 3- Direct

⎧ ⎛ V − (I − I1) RCF (x, w ) ⎞ ⎛ x⎞ w2 ⎪ I (x, w, V ) = I1 + I0 π exp ⎜ − ⎟ sinh ⎜ ⎟ ⎠ ⎝ ⎝ xT ⎠ 4 VT ⎪ ⎨ ⎛ W2 ⎞ ⎞ ⎛ ⎞ ⎛ w L V ⎪ 0 CF ⎪ I1 (w, V ) = I0 π ⎜ 4 − 4 ⎟ exp ⎜⎝ − x ⎟⎠ sinh ⎜⎝ V ⎟⎠ ⎝ ⎠ T T ⎩

(2)

The dynamic equation of Peking-Stanford RRAM model in SET and RESET process is different, which is not given here for the sake of simplicity. The gap length variation (dx/dt) is just a function of applied voltage over electrodes and CF diameter variation (dw/dt) is a function of voltage and w. According to this model, in RESET operation, there 10

Microelectronics Journal 64 (2017) 9–18

A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

are three processes, which explain dx/dt and the slowest one will be selected. It can be seen by referring to the implemented model that when voltage over terminals is negative (RESET), the dw/dt has been placed equal to zero regardless of initial value of w. There are a few points with regard to these models, including no limitation on ion movement speed, lack of window function and not considering the filament diameter decrement, in RESET process. Therefore, models employed within this paper are modified to address the above-mentioned drawbacks as explained in [20].

2.4. Related works One of the first multi-level memories was introduced in 1980 [33]. Effort to increase the density of NVMs leads to fully commercial MLC, mostly NAND based storages. The importance of MLC has turned it into one of the features in comparison between emerging technologies [34]. The fabrication process and material science technologies play an important role in the realization of RRAM-based MLCs, which is not subject of this paper. There are researches about multi-level memory based on memristor as a device in φ vs. q domain. In this definition, the resistance change could be expressed as function of φ or q. In these works, the main goal is to control memristor state based on applied flux or charge. Given that the voltage and current are measurable circuit variables, final results should be in these terms. A feedback mechanism or quantization of flux or charge is the control mechanism responsible for setting multi-level resistance, which can be interpreted as different levels of data [35,36]. Multi-level RRAM demonstration can be based on direct applied voltage across the device [7,37]. Algorithms of program and verification are utilized in MLC application of RRAM. In this schema, there are iterations in which, first a voltage pulse with adjustable amplitude is applied across the device (program), and then a read operation is performed to check (verify) the resistivity. These cycles run until the device reaches the pre-defined state [38]. Due to of speed considerations, direct approaches without verification are more desirable. It has been demonstrated that using pulsetrains instead of one voltage pulse leads to a reliable and verificationfree, RRAM-based MLC approach [39]. The response time, complicated control circuits, variable or multiple voltage source and in most cases required verifications are the main limitations in pulse train based approaches. The common circuit level approach to achieve the different levels of resistivity in RRAM is to control the time and amount of the passing current through the device during SET operation [40]. In case of one transistor one resistor (1T1R) configuration, gate voltage of the access transistors can be employed to control the passing current through RRAM. The main limitation in this approach is the transistor's region of operation. Effect of dynamic voltage drop and the body effects on transistor, limit the current controllability and reduce the MLC efficiency [41]. Moreover, generation of required gate voltages is an issue. In addition, using voltage pulse duration as the state control element to achieve MLC in RRAMs is investigated [42].

Fig. 3. The characterization unit circuit.

3.1. Numerical characterizations This work uses numerical characterization of a unit circuit as shown in Fig. 3. The characterization results will be used during the design process. There are three main elements in this figure, including transistor, RRAM and capacitor. The aspect ratio (W/L) and gate voltage (Vselect) of the access transistor are fixed in order to make a low-resistance current path into ground. RRAM parameters are shown in Table 1, and its initial state is known. Actually, the initial state of RRAM should be selected as SET or RESET. Supplies are restricted to positive voltages, so the polarity of RRAM should be selected with respect to its initial state. Polarity of RRAM in Fig. 3 is appropriate for the HRS device. Capacitor specifications, including its value (C) and initial voltage (Vcharge) are simulation variables. To perform the simulation, first the capacitor will be charged with a pre-defined voltage and then this charged capacitor is applied to a series combination of RRAM and transistor. In this configuration, all the charge across the capacitor will flow in RRAM and so will change its state. The simulation variables are RRAM's initial state, C and Vcharge. With the assumption of two initial states for the RRAM, we perform two sets of simulations in which C and Vcharge are variables. The results are final value of state variable and elapsed time for steady-state condition. Fig. 4 presents the simulation result of the circuit unit with Stanford RRAM model, in which maximum gap length is 1.5 nm. In this simulation, the ranges of Vcharge and C are 1–3 V with 0.05 V steps and 10 to 500fF with 5fF steps, respectively. The parts (a) and (b) of Fig. 4 are final gap length for an RRAM initially in the HRS and LRS, respectively. Fig. 5(a) and (b) are the contour plots of the steady-state time of initially SET and RESET device, respectively. In these plots, darker color indicates more required time for steady-state condition, which can be employed to check the expected response time during the design process. In Peking-Stanford RRAM model, HRS implies that the gap length is in its maximum and CF diameter is in its minimum point, and LRS implies the opposite. In simulations of this model, the range of capacitor value is 10 to 600 fF with 5 fF steps, and the voltage range is 1–2.5 v with 0.05 v steps. Fig. 6 presents RRAM's characteristics, for initially HRS device. Part (a) of this figure is the final state of gap length, and part (b) is the final state of CF diameter.

3. Attached capacitor based design In the previous section, we mentioned recently published RRAMbased MLC design approaches. In this section, we want to introduce our approach, called attached capacitor based design. The goal behind using a capacitor is to include dynamic behavior of the circuit inside the control mechanism. This approach is mainly based on numerical characterizations of a unit circuit, which is discussed in the following. Simple and intrinsic control mechanism, fast response time and few number of voltage sources are the benefits of this approach.

Table 1 Value of RRAM parameters.

11

Parameter

Value

gapmax g0 V0 I0 v0

1.7e−9 0.25e−9 0.43 6.14e−5 150

Microelectronics Journal 64 (2017) 9–18

A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 6. Simulation results of basic unit circuit in using Stanford-Peking RRAM model in HRS, (a) final gap length, (b) final CF diameter. Fig. 4. Simulation results of basic circuit unit in using Stanford RRAM model, (a) final gap length (HRS), (b) final gap length (LRS).

The simulation of device in LRS is illustrated in Fig. 7. For the device in this state, the initial electric field is very high, even in low voltages, and so the CF diameter shrinks very fast. So, in this figure, the graph of CF diameter is not shown, and only the final gap state is depicted. To show the RRAM behavior in LRS the ranges of voltage and capacitor values are extended to 1–4 v and 10 to 1100 fF, respectively. In Fig. 8(a) and (b), the required times for steady-state condition are plotted in the contour format for initially RESET and SET device, respectively. In these graphs, the darker colors indicate more time. Results of numerical characterizations demonstrate that the final state of RRAM, is a function of both capacitor value and its initial voltage. Capacitor is a design time parameter, but voltage is not only a design time but also a run time parameter. The following proposed design approach requires accurate voltage, which its generation using variable voltage source is too complicated, and so the voltage as run time parameter will not be utilized. Even the multiple high accuracy fixed voltage generation requires complicated circuits; therefore, we need to limit the number of voltage sources. According to these

Fig. 7. Final gap length of basic unit circuit using Stanford-Peking RRAM model in LRS.

conditions, in proposed design approach, Vcharge and capacitor values will be the design parameters. Based on performed characteristics, the following observations were concluded: 1- Controlling of initial HRS RRAM in Stanford RRAM

Fig. 5. Steady state time of basic circuit unit with Stanford RRAM model, (a) Initially RESET device, (b) initially SET device.

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A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 8. Steady state time of basic circuit unit with Peking-Stanford RRAM model, (a) Initially RESET device, (b) initially SET device.

requires seven TIQ comparators to generate 3-bit binary output using thermometric to the binary converter. In erase mode, according to selected row and column, one RRAM is connected to the VEraes and ground. In this mode, the current flow is in the opposite direction of write mode, which can put the device in HRS. The configuration of capacitors in Fig. 9 can be employed to implement a linear function between Vout and capacitor value. According to inverted input signals and binary weighed capacitor assumption, we can define a linear functionality in which C0+7C1 and -C1 will be y-intercept and the slope, respectively. This configuration is employed because we insist on utilizing the minimum number of capacitors. We will use circuit of Fig. 9, with both models of RRAM, with different capacitors' value, Vcharge, Vread, load devices and TIQ comparators. This is a low power design. Write time power consumption of the proposed circuit is in a known range and is proportional to total attached capacitor and Vcharge. The read operation power is equal to the sum of TIQ power and resistive power-loss in load device, switches and selected RRAM. Because it is important to have low voltage drop over switches in RRAM current path, the transistors sizing should be a bit large. The sizing of PMOS and NMOS for switches in RRAM path are selected as (4/0.18) and (3/0.18), respectively. These sizing increases the overhead of this design in term of area. We presented a 3-bit version of the circuit, but in reality, the 3-bit MLC capability of RRAM could be a questionable issue. The main objective of our work is the design methodology not the number of bits per cell. The proposed circuit could be easily adopted into 2-bit or 4-bit versions. So, we select 3-bit MLC for the sake of simplicity without any degradation on the generality.

model needs less power and is more controllable rather than LRS device. 2- Gap length of Peking-Stanford RRAM model in HRS is not reliable for multi-leveling. 3- CF diameter changes of HRS device in Peking-Stanford RRAM model is smooth and so could be employed in MLC applications. 4- The functionality of gap length upon the capacitor value in initial LRS of Peking-Stanford RRAM model is step like. Therefore, for MLC application based on attached capacitor, HRS RRAM is more suitable in both models. In Peking-Stanford RRAM model, it is not reliable to utilize gap length as the controllable state variable in multi-leveling applications and so CF diameter will be used. 3.2. Proposed RRAM-based MLC approach The schematic of proposed 3-bit, MxN RRAM-based MLC memory is presented in Fig. 9. This circuit has three modes, including read, write and erase. Read and write are complementary modes and can be selected with a single command (RW). Erase mode is utilized to put an individual RRAM in HRS, which is necessary before each write operation. Rowx and Colx are row and column selector signals. All the switches are voltage controlled and can be implemented by transistors. Switches are labeled as Stx, Snx and Spx representing transmission gate, NMOS and PMOS types, respectively. In case of Spx, the commands are inverted. The load block, will be replaced with proper element with respect to the RRAM model. TIQ comparator and its next blocks are forming TIQ analog to digital converter. The circuit operation is discussed in the following. In write phase Sp2, one switch among St4, St5 and St6 and one switch among Sn1, Sn2 and Sn3 are close. Given the state of input signals (In0, In1 and In2), the charge across previously charged capacitors with initial voltage of VCharge, will flow in selected RRAM to the ground. After discharging of the capacitors, there will be a shift in the state of selected RRAM. Based on polarity of RRAMs in Fig. 9, the current flow form capacitors to the ground can just decrease the RRAMs resistivity. In read phase, Sp1 is closed and all the input signals are high, so VCharge is connected to capacitors (C0, C1, 2C1 and 4C1); in addition, Sp3 is connecting the load device to the selected RRAM, and St7 connects the main circuit to the output. In this phase, an analog voltage (Vout) is generated at intersection of load and RRAM array as the result of a voltage division. Vread selection is important in read phase to prevent RRAM state change. To generate the final digital output, we employed TIQ based ADC as proposed in [21]. The main reason behind this selection is to avoid slow or power hungry ADC topologies. TIQ causes new constrains on range of Vout. The operation of TIQ is based on changing the switching point of an inverter using NMOS and PMOS sizing. In this regard, suitable point is around Vcc/2. TIQ is more sensitive to PVT rather than other ADCs but because ADC design in not the target of this paper, so we assume we have a set of comparators with acceptable variability, which is a realistic assumption. Our design

3.3. Stanford RRAM model based MLC design In this section, we will present the details of MLC design approach based on Stanford RRAM model. With reference to the Fig. 9, range of Vout should meet the TIQ specs. The output voltage in read phase is a function of RRAM and load device. The simplest option for the load device is a resistor, which has been employed in current design, but it should be noted that any selection should lead to a linear-like equation for Vout as function of the total capacitor. Fig. 10 presents the simplified circuit in read mode. Replacing the load device with a resistor (R), and assuming a small voltage drop over switches, we can write (3) according to current equality of RRAM and resistor. It is impossible to drive explicate inverse function of Vout with respect to R and gap length (g), which is required. Therefore, we used curve fitting to generate this equation. The Eq. (4) is used to approximate Vout, based on linear estimation of Sinh function, where a1, b1, c1 and d1 are constant curve fitting parameters. The result of curve fitting is plotted in Fig. 11(a). The maximum absolute error value 13

Microelectronics Journal 64 (2017) 9–18

A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 9. Schematic of proposed MLC design.

Gap range estimation, besides steady-state time limitation, can be utilized to select the charging voltage of capacitors. The Vcharge selection, defines curves such as Fig. 12(a) and (b) which are sections of Fig. 4(a) and Fig. 5(a), respectively, for a fixed voltage of 1.5 V. In Fig. 12(a), the points are the results of characterization simulation, and the line is the 5th order least-squares fit through these points (5), which defines an equation between gap length (g) and total attached capacitor. In this equation, all of a2, b2, c2, d2, e2 and f2 are the curve fitting parameters. The Fig. 12(b) should be checked to meet the time constrains.

Fig. 10. Simplified circuit in read mode.

of the plotted function is less than 0.03 v.

⎛V ⎞ − Vout IRRAM = IR ⇒ g = −g0 ln ⎜ Read I0 R⎟ ⎝ Sinh(Vout /V0 ) ⎠

Vout (g, R ) =

a1 VRead V0 + d1 b1 V0 + RI0 exp (c1 (g /g0 ))

(3)

g (C ) = a2 + b 2 C + c2 C 2 + d2 C 3 + e2 C 4 + f2 C 5 (4)

(5)

Up to this point, we have an estimation on value of resistor (R), Vout as function of gap length, Vcharge and gap length as function of the total capacitor. Therefore, we can drive an equation for Vout as function of the total capacitor. This functionality and its linear approximation is plotted in Fig. 13. The general form of this linear equation is Vout=a3b3C, where both a3 and b3 are positive values, and it is the reason of inverted inputs in Fig. 9. Using this equation, the value of C0, C1 with respect to voltage range of TIQ can be calculated. The bold dots of Fig. 13 indicate the value of the total capacitor for each input code. In the case of not acceptable linearity, value of R and consequently, VCharge has to be re-selected.

Based on the TIQ input voltage range, Fig. 11(a), can be employed to select the resistor value. The region, with lower resistor value, is appropriate. The sections of surface with small value of the resistor are plotted for three different value of R in Fig. 11(b). The figure shows that the more the resistor, the better the linearity in desired Vout region (middle part) but limits the range of voltage and gap, and vice versa. Therefore, a moderate value of the resistor could be selected as an initial choice. At this point, by fixing the value of R in Eq. (5), we have an explicit equation between Vout and gap length (g). Moreover, this selection specifies gap and Vout range. 14

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Fig. 13. Plot of Vout respect to total capacitor and its linear approximation.

Fig. 14. pMOS load device characterization; (a) pMOS configuration, (b) simulation result.

Fig. 11. Vout functionality respect to resistance and gap position; (a) Vout(g, R), (b) Vout (g) for specific values of R.

source and drain voltage difference. This estimation's error is in the range of a few nA. In Eq. (6), a4 to h4 are curve fitting parameters.

3.4. Peking-Stanford RRAM model based MLC design

ID (VS , VD ) = a4 + b4 (VS − VD ) + c4 (VS − VD )2 + ... +h4 (VS − VD )6

The second design approach is similar to previous design, but as earlier mentioned, in Peking-Stanford RRAM model, the CF diameter comes with multi-level controllable physical characteristic. Here simple resistor could not be utilized as the load device, because Vout as a function of capacitor value cannot be linear enough in this configuration. Based on experiments, we are convinced to use a pMOS load device, where the bulk of the pMOS is connected to its drain as proposed in [43]. In this configuration, Vout is drain voltage of MOS transistor, and its equation is written using current equality of pMOS transistor, and RRAM. Due to required accuracy, long channel transistor model, is not usable and generated equation for Vout using this model is far from reality. Our target transistor technology is standard CMOS 180 nm with level 49, and we require a transistor current equation with respect to voltage of drain and source. Therefore, we characterized the pMOS load shown in Fig. 14(a). The simulations are conducted by setting drain and source voltages and measuring the current for various transistor sizing. The proper sizing has been selected based on best guess try and error. The simulation result for a pMOS device, with W/L of 600 nm/180 nm, with source voltage (VSource) of 2.0–1.0 V and drain voltage (VDrain) of 1.5–0 V has been plotted in Fig. 14(b). We used Eq. (6) to fit the characterization results, using sixth order least-squares

(6)

In the second design, we have one new parameter, which is VSource or Vread. This parameter should be selected to generate drain voltage in range of TIQ inputs. Fixation of source voltage (VS) in (6) results in transistor current equation as function of Vout (VD). So, we can drive Eq. (7) between CF diameter (w) and Vout, based on (2) and (6). In this equation, TE and BE represent voltages of top and bottom electrodes of RRAM and Fx and Gx are Intermediate equations. All other parameters have been introduced before.

⎧ Fx (Vout , BE ) ⎪ w (Vread , Vout , BE ) = 2 Id (Vread , Vout ) − Gx (Vout , BE ) ⎪ ⎪ ⎛ W2 ⎞ ⎛ TE − BE ⎞ ⎛ L ⎞ ⎪ ⎨ Fx (TE , BE ) = I0 π ⎜ CF ⎟ exp ⎜ − 0 ⎟ Sinh ⎜ ⎟ ⎠ ⎝ ⎝ xT ⎠ VT ⎝ 4 ⎠ ⎪ ⎪ ⎞ ⎛ ⎛ ⎞ ⎛ ⎪Gx (TE , BE ) = ⎜π TE − BE ⎟ − I π exp ⎜ − L 0 ⎟ Sinh ⎜ TE − BE ⎞⎟ 0 ⎪ ⎠ ⎝ ⎝ xT ⎠ ⎝ rou L 0 ⎠ VT ⎩

(7)

Assuming a low voltage drop across switches and so considering BE at ground voltage in read phase (Fig. 10), we can plot Vout against Vread and w as illustrated in Fig. 15(a). Given the source voltage of transistor or Vread, we can write Vout as function w with a 3rd order approxima-

Fig. 12. One Section of characteristic surface for fixed voltage of 1.5 v. (a) Final gap length, (b) Steady state time.

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A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 17. Plot of Vout vs. capacitor and its linear approximation.

3.5. Simulation results In this section, the simulation results of the circuit, shown in Fig. 9, will be demonstrated. In the following simulations, ideal switches are replaced with corresponding transistor-based counter parts. Transistor technology is CMOS standard 180 nm. Both RRAM models are implemented in Verilog-A, and they are initially in HRS. TIQ comparators, has also been implemented in Verilog-A. All the simulations are carried out using mixed Verilog-A and SPICE simulator. 3.6. Simulation result of stanford RRAM model based MLC Fig. 15. (a) Vout as function of Vcc and CF diameter (w), (b) Vout as function of w @ Vcc=1.4 v.

In design based on Stanford RRAM model Vcc=Vread=1.8 V and the load device is a 500 kΩ resistor. These selections satisfy the minimum field condition and prevent state change during read operation. The target Vout and corresponding total capacitors, are expressed in the first two columns of Table 2. These value of capacitors, were also shown in Fig. 13. The capacitors of Fig. 9 can be calculated as follows: C0=68fF, C1=31fF. The transient simulation of Vout for all input codes, for a single RRAM is depicted in Fig. 18(a). The range of output binary codes is also illustrated in this figure. The simulation results of Vout and its difference from desired value (error) are stated in the last two columns of Table 2. RRAM's stochastic behavior and circuit elements' tolerance will cause variations in analog generated output voltage (Vout). In our design approach, the important effective factors on Vout, are variations and tolerance in: RRAM's initial state, Vcharge and capacitances. To demonstrate these effects, we conduct Monte Carlo simulations, based on the following comments; Low tolerance fixed voltage generation is feasible, so the tolerance of Vcharge is selected as 1%. Giving enough time to an RRAM in erase mode, can cause ions to return to their original position in HRS, therefore the initial state variation is selected as 2%. The tolerances of capacitors are selected as 10%. Furthermore, the Stanford RRAM model can simulate the randomness in gap length, which is utilized with different random seeds in each of the simulations. The results of 100 Monte Carlo simulations, for each input code, including mentioned effects are presented in Fig. 18(b). The small plot shows more detailed behavior of Vout. The variation on each line is the result of random gap length effects. Minimum voltage difference of two side by side states is more than 65 mV.

tion (8), where a5, b5, c5 and d5 are fitting parameters. In Vread selection, two facts should be taken into consideration; First, Vread should be high enough to cover the input range of TIQ converter, and second, it should be low enough to prevent state change in memory read mode. The first constraint could be achieved using Fig. 15(a). To meet the second constraint, because no minimum field concept is defined in Peking-Stanford RRAM model, we can use voltage range, which results in very small dw/dt values and some try an errors. Fig. 15(b) depicts the Vout against w for Vread=1.4 V. In this figure, dots are points from Eq. (7) and line is the plot of Eq. (8).

Vout (w ) = a5 + b5 w + c5 w 2 + d5 w 3

(8)

We can select one section from the surface of Fig. 6(b) by fixing the Vcharge, with respect to the required range of w that can be determined based on Fig. 15(b). Then we can drive Eq. (9) to describe CF diameter (w) as the function of the total capacitor, where a6 to f6 are fitting parameters. In Fig. 16, the dots are the simulation result from the characterization surface, and line is the plot of Eq. (9) for Vcharge=2 V.

w (C ) = a6 + b6 w + c6 w 2 + d 6 w 3 + e6 w 4 + f6 w 5

(9)

Using (8) and (9), we can describe Vout as a function of the total capacitor, which is plotted in Fig. 17. In this figure, the solid line is (9), and dashed line is its linear approximation. In the case of high error of linear approximation, the load device, Vread and Vcharge should be reselected. Illustrated dots on Fig. 17 are corresponding capacitors for input codes, which could be achieved utilizing the capacitor array of Fig. 9.

Table 2 Target and achieved output voltage and corresponding capacitance and error for circuit using Stanford RRAM model.

Fig. 16. CF diameter (w) as function of total capacitor (C).

16

Input

Vout (desired)

C (fF)

Vout (Simulated)

Error (v)

0 1 2 3 4 5 6 7

0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3

284 253 222 191 160 130 99 68

0.59 0.69 0.80 0.92 1.03 1.13 1.23 1.30

−0.01 −0.01 0 0.02 0.03 0.03 0.03 0

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A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

Fig. 18. Transient simulation of Vout in main circuit for all input codes, (a) simulation of circuit with Stanford RRAM model; (b) Mont Carlo simulation of circuit using Stanford RRAM model including 1%, 2% and 10% variation in Vcharge, initial gap length and capacitances, respectively, (c) simulation of circuit with Peking-Stanford RRAM model; (d) Mont Carlo simulation of circuit using Peking-Stanford RRAM model including 1%, 2% and 10% variation in Vcharge, initial gap length and capacitances, respectively.

To show the sensitivity of the design, Monte Carlo simulations are performed. Similar to the first design, the variations of Vcharge, initial state and capacitance are set to 1%, 2% and 10%, respectively. In these simulations, because the gap length is in its minimum position for all states, the random effects are applied to CF diameter (w). Fig. 18(d) illustrates the transient Monte Carlo simulation results. The small plot of this figure shows more detailed behavior of Vout. In addition, it demonstrates that the worst-case voltage difference between two states is around 40 mV. Knowing Vout sensitivity of the designed circuit can be employed to select TIQ comparators levels as: 0.45, 0.53, 0.61, 0.69, 0.77, 0.85, 0.93 V. Finally, it is important to note that, in the capacitor based design approach, regardless of RRAM model, the Vcharge is the most important variations' source.

Fig. 18(b) can be used to select the switching points of TIQ comparators. In our case, the seven levels of switching points are: 0.62, 0.73, 0.84, 0.96, 1.1, 1.2 and 1.3 V. Because the TIQ design is not the subject of this paper, its variations effects, and thus digital related errors are not discussed. 3.7. Simulation result of Peking-Stanford RRAM model based MLC In Peking-Stanford RRAM model based circuit, the load device is replaced with pMOS as shown in Fig. 14(a), with sizing of 600 nm/ 180 nm. In this design, Vread and VCharge are selected as 1.4 and 2 V, respectively. Increasing the Vread or increasing the sizing of the load transistor will cause state change in the higher resistivity state of RRAM. The desired Vout and its related capacitor values are depicted in the first two columns of Table 3. The capacitors of the main circuit can be calculated as follows: C0=30fF, C1=79fF. The result of transient simulation using pMOS load device and Peking-Stanford RRAM model is presented in Fig. 18(c). The range of output binary codes is also shown in this figure. The final simulated Vout values and its difference from target value (error) are presented in the last two columns of Table 3.

3.8. Memory array simulation The general functionality of proposed memory array, based on Stanford RRAM model, is presented in Fig. 19. This figure shows all defined operational modes, including erase, read and write. At first, a read is conduct on RRAM in row two and column three, and then a cycle of erase, write and read is performed on RRAM in row one, and column two. Finally, state of RRAM in row three and column one is erased. Gap length of all three RRAM is shown in a single plot, two dotted lines in two ends belong to the first and third mentioned RRAM and the line in the middle shows the gap length of an RRAM during all operating modes. Input and output code words, and all controlling signals are plotted in Fig. 19.

Table 3 Target and achieved output voltage and corresponding capacitance and error for circuit using Peking-Stanford RRAM model. Input

Vout (desired)

C (fF)

Vout (Simulated)

Error (v)

0 1 2 3 4 5 6 7

0.45 0.52 0.59 0.66 0.73 0.80 0.87 0.95

557 478 399 320 241 161 82 30

0.44 0.51 0.58 0.65 0.72 0.79 0.87 0.98

−0.01 −0.01 −0.01 −0.01 −0.01 −0.01 0 0.03

4. Conclusion In this paper, we introduced an RRAM-based MLC design approach, which is based on the attached capacitor. Two realistic RRAM models, 17

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A.A. Bagheri-Soulla, M.B. Ghaznavi-Ghoushchi

[13]

[14]

[15]

[16]

[17] [18]

Fig. 19. Simulation scenario on general functionality of proposed memory array, showing one read operation, one cycle of erase, write and read operation and one erase operation. Controlling signal of Row, Col, RW and Erase are in agreement with Fig. 9. Input and Output are in/out code words and gap length show state of three RRAM in a single plot.

[19]

including Stanford and Peking-Stanford RRAM models have been utilized. The detailed circuit of an MxN MLC memory, including controlling signals, is proposed. The numerical characterizations of the unit circuit and devices' behavioral equations are employed during the design process. The proposed circuit has three working modes, including write, read and erase. In write mode, the state of RRAM will be changed from initially HRS, which is previously obtained in erase process. During read operation, first an analog voltage is generated, and then an ADC will convert that voltage into binary output. We employed TIQ-based ADC for its simplicity, without any assertion. The SPICE based simulations, showed the accuracy of proposed design approach. The Monte Carlo simulations are performed to show the sensitivity of design approach to the tolerance and variations. Moreover, the results of Monte Carlo simulations are used to set the switching levels of TIQ comparators. In this paper, we considered a 3-bit MLC, but the number of levels is not our point of emphasis, and the approach can easily be adapted to 2 or 4 level devices.

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