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Analog-to-digital converter modeling: a survey
.i ~,.
PII: S0263-2241 (97)00009-2
ELSEVIER
MeasurementVol. 19, No. 3/4, pp. 139-146, 1996 © 1997 Elsevier ScienceLimited. All rights reserved Printed in The Netherlands 0263-2241/96$15.00 +0.00
Analog-to-digital converter modeling: a survey A. Baccigalupi a.,, M. D'Apuzzo b a Department of Computer Science, University of Naples, Naples, ltaly b Department of Electrical Engineering, University of Naples, Naples, Italy
Abstract
The paper begins with an overview of the many application fields of analog-to-digital converter modeling techniques, then makes a general classification of the ADC models into three categories (electrical models, behavioral models and mixed models) and suggests the criteria for choice for each of them. The remainder of the paper reviews the research contribution of the authors on ADC modeling. Special emphasis is given to models for the compensation of ADC dynamic errors. In order to give a complete perspective of the many facets implied in ADC modeling, the discussion is widely supported by technical references. © 1997 Elsevier Science Ltd.
Keywords: Analog-to-digital conversion; Artificial neural network; Modeling
in the measurement laboratory, would like to have an accurate model of the ADC under test for fixing the ADC performance from a metrological point of view. As a consequence, different users of ADC models are interested in different modeling details. Therefore, at present, a lot of ADC models are proposed in the scientific literature: some of them describe specific error sources [1-3]; some others, instead, are devised to connect conversion techniques and corresponding errors [4-7]; still others are devoted to measuring the effect of each error source in order to compensate it [8]. Finally, many papers [9-12], suggest general guidelines for different ADC models. Thus, a huge amount of papers are actually present in the scientific literature, and the many facets of each of them make it difficult to give a complete perspective of ADC models now available. The technological progress, which is rapidly increasing, makes this task even harder. So, models of advanced digitizers must fit the new technology characteristics.
I. Introduction
Analog-to-digital converter (ADC) modeling pertains to many fields of scientific research, even though the special interest may be different in distinct application areas. Production factories for ADCs, for instance, are aware of the forecasting capabilities provided by the use of modeling techniques, which allow better understanding of error sources, the possibility of verifying the consequences of different design choices, and so on. The interest of the end user for ADC modeling is completely different. As a matter of fact, he is concerned with increasing ADC performance with suitable signal processing of the acquired data. Conversion system designers use ADC models for a still different aim. They have no interest in the conversion process or in knowledge of the ADC error sources. They, instead, desire a tool allowing the insertion of ADC parts into simulation programs in order to simulate the whole conversion system behavior. Finally, the measurist, working * Corresponding author. 139
140
A. Baccigalupi, M. D'Apuzzo
2. A classification of ADC modeling techniques
The possibilities for classifying the variegated ADC models are many. In particular, we chose a classification embracing ADC models in three categories: (i) electrical models, (ii) behavioral models, and (iii) mixed electrical/behavioral models. 2.1. A D C electrical models
Electrical models describe the ADC in terms of its equivalent circuit. Hence, the model itself describes the details of any electrical and/or electronic part included in the converter under test. Obviously, these models give the best working detail of the converter and, therefore, they are the most suitable for the designer, as they allow the converter behavior to be accurately forecast during the design phase. On the contrary, they seem not very well suited for applications in which such simulation details are not required, because of the huge amount of CPU time needed to compute, step by step, all the voltages across the nodes and all the currents into the branches of the electrical model.
ADC circuit is divided into sections, some described in terms of behavioral models and the remaining by electrical circuits. This kind of model is generally used every time complete visibility of some ADC details is needed (described with electrical circuits), whereas other ADC details are unnecessary (described with behavioral black boxes). This approach has the advantage of saving a lot of CPU time which is not wasted by showing superfluous details. Therefore, by a proper choice of the ADC details to be shadowed, the optimal trade-off between computing time and simulation goal reaching can be reached. The remainder of the paper gives particular emphasis to modeling techniques for ADC dynamic error compensation. Therefore, in the following, special attention will be paid to investigating models capable of evidencing errors peculiar to the ADC under test.
3. A serial ADC error model
Behavioral models completely leave the ADC physical realization out of consideration; instead, they describe an ADC working in terms of mathematical or algorithmic formulations. The complexity of the behavioral model is absolutely variable, and changes according to the requested simulation accuracy. ADC behavioral models are frequently described by means of functional blocks composed of a number of black boxes, each of which takes into account a specific characteristic or a peculiar aspect of the converter under test (e.g., noise, gain error, offset, non-linearity, quantization). As a consequence, ADC behavioral models are often used to improve the converter operation by compensating some of the systematic errors of the converter under test.
Usually, ADC error sources are both of static and dynamic nature, their weight being dependent on input signal harmonics compared with the ADC maximum sampling rate. Static errors are mainly generated by a non-uniform spacing of the quantization thresholds, and thus significantly affect the ADC spectral purity. In turn, dynamic errors depend on sources, such as thermal noise, uncertainty of the aperture time, and delay introduced by the conversion process. The dynamic error sources change their weight depending on the frequency of the input signal, and are evidenced at the ADC output as the introduction of spurs and noise [13]. Disregarding the error sources, the proposed approach [14] models the ADC behavior into a chain of functional blocks, each of which accounts for a specific error. In particular, the ADC errors are considered by three equivalent error blocks: (i) amplitude compression block, (ii) jitter and (iii) distortion (Fig. 1).
2.3. A D C mixed electrical/behavioral models
3.1. Amplitude compression block
ADC mixed models are those in which the complexity of the modeling of the whole of the
Amplitude compression is usually present at ADC output, arising from saturation phenomena
2.2. A D C behavioral models
A. BaccigalupL M. D'Apuzzo
II
jitter
(] 1,d/dO I Vo
'l
ampfitude-compression(tanh)
141
~ distortion (cosh)
11v,
bV
Fig. 1. Block diagram of the serial A D C error model.
typical of analog circuitry of the converter itself. It is evidenced, in the frequency domain, as the introduction of odd spurs. ADC behavioral models can use proper amplitude compression blocks in order to consider the whole of odd spurs, disregarding the source which actually produced the distortion itself. In particular, the expression used to describe the amplitude compression is: vl = a* tan
h(vo/b)
( 1)
where parameters a and b must be tuned in order to fit all of the odd spurs at the output of the converter under test.
distortion attached to even spurs is instead considered by the distortion block. The corresponding mathematical formulation is expressed in terms of the transfer function: v3 = v2 + v~
(4)
where v; ---f*[ 1 - c o s
h(v2/e)]
(5)
in which parameters e and f are obtained to fit the appropriate even harmonic level, and fall-off rate of even spurs.
3.2. Jitter block
4. A parallel A D C error model
The effect of sampling jitter at the ADC output results in a reduction of the signal-to-noise ratio, evidenced in the frequency domain as a noise floor growth. Therefore, ADC behavioral models can use proper jitter blocks in order to fit the signalto-noise ratio at the output of the ADC under test. The expression used to simulate the jitter effect was derived from that employed by Gray et al. in Ref. [15] to describe the sample and hold jitter:
The main drawback of the model presented in Section 3 comes from the objective difficulty to conform model parameters to actual ADC behavior. This difficulty is due to the chain structure of the model itself: the in-series structure implies that any parameter change requires the rearrangement of all the other parameters in the model. Thus, the parameters cannot be evaluated separately from each other, but they must be fixed all at once. In this section a different model structure is described, with the aim of obtaining parameters as independent as possible from each other. The solution is an error model with a parallel structure, which allows a more robust parameter identification technique and, at the same time, a better fitting of the model output to the experimental data in terms of frequency spectrum. The parallel ADC error model (Fig. 2) includes: (i) a delay block, (ii) an amplitude compression block, (iii) a distortion block, and (iv) a gain block. With regard to the amplitude compression and the distortion blocks, they work like those already examined in the previous section, but now
1~2 = V1 -[- V~
(2)
where
v~ = (c- d*lvl I)*6vl/6t
(3)
and parameters c and d should be evaluated in order to best fit the noise floor present at the output of the ADC under test.
3.3. Distortion block The aforementioned amplitude compression block accounts for any odd spur. The harmonic
142
A. Baccigalupi, M. D 'Apuzzo
ampfitudecompression (tanh)
V2
distortion (cosh)
v3
v4
ia at
~
/16 ID
]quantizer
Fig. 2. Block diagram of the parallel ADC error model.
they are in parallel so there is no mutual influence in fixing parameters a, b, c and d. In addition, the jitter block, used to adjust the noise floor, is no longer present because the noise floor is fixed by varying the resolution of the ideal quantizer block (quantization noise). Furthermore, the gain factor k is used to scale the magnitude of the fundamental compared with the total harmonic distortion. Finally, the delay block z introduces the input/output time shift which can be of great interest in on-lineapplications. As previously mentioned, one of the prime advantages of the parallel over the chain structure lies in the possibility to simplify model parameter identification. In fact, the parallel structure allows one to identify the model parameters individually, according to some physical considerations. In Ref. [16] the authors describe a closed form algorithm to evaluate the model parameters as a function of a set of experiments to be carried out on the actual ADC under test.
5. A neural ADC error model
Both the models proposed in Sections 3 and 4 have the disadvantage that the model parameters are functions of the input signal bandwidth, so they can be properly applied only if the input signal is known to be band limited inside the bandwidth in which the model parameters may be considered to be constant. To overcome this drawback, one of the most interesting proposals for ADC dynamic compensation is referred to as phase plane compensation, proposed by Irons in Ref. [17]. The ADC dynamic
behavior is considered by mapping its conversion errors on the phase plane (i.e., conversion errors are mapped for any level and slope of the input signal). The phase plane implementation stores conversion errors in two-dimensional error tables in which the row index is the signal level (represented by the corresponding ADC output code) and any columnindex is the signal slope (evaluated as the difference between actual and previous ADC output codes scaled by the sampling period). The idea is very interesting, but the implementation becomes impracticable as the ADC resolution (and hence the number of ADC codes) increases. In this case, Irons proposes the abatement of the error table dimension by assuming the signal dynamic in squared areas, endorsed by a number of adjacent rows and columns, to be constant. A different method, which employs artificial neural networks (ANN) to reduce the matrix dimension of the phase plane approach, has been proposed by the authors in Ref. [18]. The basic idea is based on the generalization capabilities of the ANN which is able to forecast the converter behavior all over the phase plane, from the knowledge of a reduced set of the error table (to be used as learning set). As is well known, working ANNs require a preliminary learning phase in which the learning set must be provided to the ANN in terms of input/output values. In the case of interest, the preliminary learning phase works on the principle shown in Fig. 3. At any instant of time, a test signal v(t) is acquired both by the ADC under test and by an ideal quantizer, thus providing y and y~ codes respectively. Furthermore, the value y acquired at the previous time step t_ 1 is stored as x. The error e(x,y) is computed as Y-Yl and is
A. Baccigalupi,M. D'Apuzzo
v(t)
143
Ideal Quantizer
ADC
l y-yi I Y
•; b ~
1 under test I
[x(r°windex) I
T
e(x, y)
'
y (col. index) Fig. 3. Construction of the reduced size error table. stored in the table T at location x,y. This process continues until a sufficient number of e(x,y) values fill in the table T. Once a particular reduced-size error table T has been built up, it is used for the successive ANN learning phase, whose working operation is sketched in Fig. 4, in which the input/output learning set is provided by: (1) (x) and (y) as the input learning set; (2) e(x,y) as the output learning set.
The number of elements chosen for the construction of the reduced size compensation table affects the number of tests required to build the tables themselves, as well as the ANN's compensation performance. Hence, a reduced size choice can be considered proper only if it is able to guarantee a satisfactory trade-off between the number of tests and the related ANN compensation performance.
6. Modeling of advanced transient digitizers Hence, the learning phase tries to find out the ANN weight and bias values which minimize the difference: e(x, y)= e(x, y)-e*(x, y). Once the learning phase is completed, the ANN is ready to perform its compensation task in the so-called production phase. In this phase, the output of the actual ADC feeds the ANN, according to what was learnt in the previous phase, and produces the correction e*(x,y) to apply to the ADC samples, as depicted in Fig. 5.
Technological progress in the field of analog-todigital converters is continuously evolving at a very high speed. Thus, modeling of new digitizers requires continuous adjustments in order to consider the characteristics peculiar to the new technology as well. Scan converter-based digitizers, for example, are characterized by peculiar dynamic error sources arising from the working of such devices [19,20]. Reading and digitizing operations
"
.......
learning algorithm
.
l
[
e (x,y)
e
Fig. 4. ANN learning phase.
144
A. Baccigalupi, M. D'Apuzzo
e'(x,y) ~ actual ADC
I
I
[
-I
I
y"
Fig. 5. ANN production phase.
are carried out at a slow speed, so that the corresponding errors turn out to be negligible [21,22]. On the other hand, singular error sources arise from the writing mechanism and from the target semiconductor diodes that remarkably influence the dynamic behavior of the digitizer [23]. The main error sources in the writing mechanism can deform the beam and thus can give rise to trace distortions as a blooming effect near sine wave crests, or insufficient intensity in fast rising edges. Differences in dynamic behavior of the semiconductor diodes usually arise, in spite of their correction through the reference array, depending on the technology and on the practical realization. As a consequence of the aforementioned error sources, in the writing phase, the error magnitude depends (i) on the way the electron beam forces each diode of the target and (ii) on which particular diode is forced. Hence, the errors can vary significantly according to the written area and, correspondingly, to the instantaneous value of the input signal. Owing to such peculiar behavior, the use of the aforementioned models seems not to be well suited to increase scan converter performance by means of error compensation techniques. Thus, a technique for evaluating the distortion of the charge distribution, aimed at improving the signal extraction in scan converters, is proposed in Ref. [24]. Such a technique consists of (i) the analysis of actual charge distributions on the columns through the evaluation of statistical parameters based on the first four moments around the mean, (ii) the characterization of the distortion across the target through the parameter trend assessment, and (iii) the improvement of the signal extraction through the model identification of the distribution [25]. Since the statistical parameters are normalized to
the distribution spread, a suitable model, that relates the spread to the input signal rate, is integrated in the proposed technique to describe adequately dynamic distortion effects. In addition, in order to model the dependence of the scan converter behavior from the beam position, a proper behavioral model has been proposed (see Fig. 6): the scan converter can be seen as a number of different conversion subsystems (S/H and A D C ) each of which operates in an instant of time properly delayed for the sampling period.
7. Concluding remarks ADC modeling is still of great interest in many fields of application, so that much work has been spent in designing different models for different goals. The huge amount of papers actually present in the literature, and the many facets of each of them, did not allow for a complete survey of all the proposed models. Therefore, only a survey of the ADC model techniques set up by the authors has been presented. By inspecting the available references, we can see that the world of ADC modeling is evolving to reach the continuous technological progress which is running at a very high speed. Every new ADC presented on the market shows new performance and new characteristics, requiring new models to be designed in order to evidence the new ADC behavior. The present research is now focused on refining the scan converter model; the basic approach is described in Section 6. The current main difficulty in research arises from the lack, on the market, of proper testing equipment capable of acting as a
145
A. Baccigalupi, M. D'Apuzzo
V(t)
%(nAt) Fig. 6. Scan converter behavioral model.
reference for the experimental validation of the proposed theories all over the working range of the scan converter ( 10 Vpp, 200 GHz).
References 1. R.J. Polge, B.K. Bhagavan and L. Callas, Evaluating analog-to-digital converters, Simulations, March 1975, pp. 81-86. 2. Y.C. Jenq, Measuring harmonic distortion and noise floor of an A/D converter using spectral averaging, IEEE Trans. Instrum. Measurement 37 (December 1988). 3. A. Petraglia and S.K. Mitra, Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer, IEEE Trans. Instrum. Measurement 40(5) (October 1991) 831-835. 4. E.G. Soenen, P.M. Vanpeteghem, H. Liu, S. Narayan and J.T. Cummings, A framework for design and testing of analog integrated circuits, IEEE Trans. Instrum. Measurement 39(6) (December 1990) 890-893. 5. K. Hejn and I. Kale, Some theorems on Walsh transforms of quantizer differential and integral non-linearity, Proc. IMTC-90, Atlanta, USA, pp. 55-61. 6. G. Ruan, A behavioral model of A/D converters using a mixed mode simulator, IEEE J. Solid State Circuits 26(3) (March 1991) 283-290. 7. T.R. McComb, J. Kuffel and R. Malewsky, Measuring characteristics of the fastest commercially available digitizers, IEEE Trans. Power Delivery 2(3) (July 1987) 661-670. 8. F.H. Irons, D.M. Hummels and S.P. Kennedy, Improved Compensation for analog-to-digital converters, 1EEE Trans. Circuits Systems 38(8) (August 1991) 958-961. 9. A. Baccigalupi, F. Cennamo and M. D'Apuzzo, Digital recording of high speed voltage transients, Proceedings o f 3rd IMEKO TC4 International Symposium on Measurement and Electronic Power Systems, Zurich, September 1989. 10. M.V. Borsche, J. Shonkens and J. Renneboog, Dynamic
testing and diagnostic of A/D converters, IEEE Trans. C.A.S. 33(8) (August 1986) 775-778. 11. D.W. Doerfler, Dynamic testing of a slow sample rate, high resolution data acquisition system, IEEE Trans. Instrum. Measurement 35(4) (December 1986) 477~82. 12. J. Kuffel, R. Malewsky and R.G. Van Heeswijk, Modeling of the dynamic performance of transient recorders used for high voltage impulse tests, IEEE Trans. Power Delivery 6(2) (April 1991) 507-515. 13. D. Asta and F.H. Irons, Dynamic error compensation of analog to digital converters, Lincoln Lab. J. 2 (1989) 161-182. 14. A. Baccigalupi, P. Daponte and M. D'Apuzzo, An ADC error model for testing digitizing signal analyzers, Proceedings o f 5th International Symposium on Electrical Measuring Instruments for Low and Medium frequencies, Vienna, 1992, pp. 167-174. 15. J.R. Gray and S.C. Kistopoulos, A precision sample and hold circuit with subnanosecond switching, IEEE Trans. Circuit Theory (September 1964) 389-396. 16. A. Baccigalupi, P. Daponte and M. D'Apuzzo, An improved error model of data acquisition systems, IEEE Trans. Instrum. Measurement 43(2) (April 1994) 220-225. 17. T.A. Rebold and F.H. Irons, A phase plane approach to the compensation of high speed analog-to-digital converters, Proceedings o f IEEE International Symposium on Circuits and Systems, 1987, pp. 455458. 18. A. Baccigalupi, A. Bernieri and C. Liguori, Error compensation of A/D converters using neural networks, IEEE Trans. Instrum. Measurement 45(2) (April 1996). 19. P. Arpaia, A. Baccigalupi, F. Cennamo and M. D'Apuzzo, Testing uncertainty of scan converter based transient digitizers, Proceedings o f 7th IMEKO TC4 International Symposium, Prague, September, 1995. 20. P. Arpaia, A. Baccigalupi and F. Cennamo, Measurement on A/N and N/A conversion systems (in Italian), CNR GMEE Symposium, Bologna, 18-20 September 1995. 21. J. Kuffel, R. Malewsky and R.G. van Heeswijk, Modeling of the dynamic performance of transient recorders used for high voltage impulse tests, IEEE Trans. Power Delivery 6 (April 1991) 507-515.
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4. Baccigalupi, M. D'Apuzzo
22. P. Arpaia, F. Cennamo, P. Daponte and M. D'Apuzzo, Dynamic characterization of scan conversion based transient digitizers, IEEE Trans. Instrum. Measurement /June 1995). 23. P. Arpaia, F. Cennamo, P. Daponte and M. D'Apuzzo, A behavioral model for scan converter based transient digitizers, Measurement 17(2) 103 114.
24. P. Arpaia, A. Baccigalupi and F. Cennamo, Techniques of improved signal extraction in scan conversion-based transient digitizers, Proceedings ~?["IEEE Instrumentation and Measurement Technology ConJerence, Brussels, Belgium, 4-6 June 1996. 25. A. Haber and R.P. Runyon, General Statistics Reading, Addison Wesley, Massachusetts, 1969.
PII: S0263-2241 (97)00009-2
ELSEVIER
MeasurementVol. 19, No. 3/4, pp. 139-146, 1996 © 1997 Elsevier ScienceLimited. All rights reserved Printed in The Netherlands 0263-2241/96$15.00 +0.00
Analog-to-digital converter modeling: a survey A. Baccigalupi a.,, M. D'Apuzzo b a Department of Computer Science, University of Naples, Naples, ltaly b Department of Electrical Engineering, University of Naples, Naples, Italy
Abstract
The paper begins with an overview of the many application fields of analog-to-digital converter modeling techniques, then makes a general classification of the ADC models into three categories (electrical models, behavioral models and mixed models) and suggests the criteria for choice for each of them. The remainder of the paper reviews the research contribution of the authors on ADC modeling. Special emphasis is given to models for the compensation of ADC dynamic errors. In order to give a complete perspective of the many facets implied in ADC modeling, the discussion is widely supported by technical references. © 1997 Elsevier Science Ltd.
Keywords: Analog-to-digital conversion; Artificial neural network; Modeling
in the measurement laboratory, would like to have an accurate model of the ADC under test for fixing the ADC performance from a metrological point of view. As a consequence, different users of ADC models are interested in different modeling details. Therefore, at present, a lot of ADC models are proposed in the scientific literature: some of them describe specific error sources [1-3]; some others, instead, are devised to connect conversion techniques and corresponding errors [4-7]; still others are devoted to measuring the effect of each error source in order to compensate it [8]. Finally, many papers [9-12], suggest general guidelines for different ADC models. Thus, a huge amount of papers are actually present in the scientific literature, and the many facets of each of them make it difficult to give a complete perspective of ADC models now available. The technological progress, which is rapidly increasing, makes this task even harder. So, models of advanced digitizers must fit the new technology characteristics.
I. Introduction
Analog-to-digital converter (ADC) modeling pertains to many fields of scientific research, even though the special interest may be different in distinct application areas. Production factories for ADCs, for instance, are aware of the forecasting capabilities provided by the use of modeling techniques, which allow better understanding of error sources, the possibility of verifying the consequences of different design choices, and so on. The interest of the end user for ADC modeling is completely different. As a matter of fact, he is concerned with increasing ADC performance with suitable signal processing of the acquired data. Conversion system designers use ADC models for a still different aim. They have no interest in the conversion process or in knowledge of the ADC error sources. They, instead, desire a tool allowing the insertion of ADC parts into simulation programs in order to simulate the whole conversion system behavior. Finally, the measurist, working * Corresponding author. 139
140
A. Baccigalupi, M. D'Apuzzo
2. A classification of ADC modeling techniques
The possibilities for classifying the variegated ADC models are many. In particular, we chose a classification embracing ADC models in three categories: (i) electrical models, (ii) behavioral models, and (iii) mixed electrical/behavioral models. 2.1. A D C electrical models
Electrical models describe the ADC in terms of its equivalent circuit. Hence, the model itself describes the details of any electrical and/or electronic part included in the converter under test. Obviously, these models give the best working detail of the converter and, therefore, they are the most suitable for the designer, as they allow the converter behavior to be accurately forecast during the design phase. On the contrary, they seem not very well suited for applications in which such simulation details are not required, because of the huge amount of CPU time needed to compute, step by step, all the voltages across the nodes and all the currents into the branches of the electrical model.
ADC circuit is divided into sections, some described in terms of behavioral models and the remaining by electrical circuits. This kind of model is generally used every time complete visibility of some ADC details is needed (described with electrical circuits), whereas other ADC details are unnecessary (described with behavioral black boxes). This approach has the advantage of saving a lot of CPU time which is not wasted by showing superfluous details. Therefore, by a proper choice of the ADC details to be shadowed, the optimal trade-off between computing time and simulation goal reaching can be reached. The remainder of the paper gives particular emphasis to modeling techniques for ADC dynamic error compensation. Therefore, in the following, special attention will be paid to investigating models capable of evidencing errors peculiar to the ADC under test.
3. A serial ADC error model
Behavioral models completely leave the ADC physical realization out of consideration; instead, they describe an ADC working in terms of mathematical or algorithmic formulations. The complexity of the behavioral model is absolutely variable, and changes according to the requested simulation accuracy. ADC behavioral models are frequently described by means of functional blocks composed of a number of black boxes, each of which takes into account a specific characteristic or a peculiar aspect of the converter under test (e.g., noise, gain error, offset, non-linearity, quantization). As a consequence, ADC behavioral models are often used to improve the converter operation by compensating some of the systematic errors of the converter under test.
Usually, ADC error sources are both of static and dynamic nature, their weight being dependent on input signal harmonics compared with the ADC maximum sampling rate. Static errors are mainly generated by a non-uniform spacing of the quantization thresholds, and thus significantly affect the ADC spectral purity. In turn, dynamic errors depend on sources, such as thermal noise, uncertainty of the aperture time, and delay introduced by the conversion process. The dynamic error sources change their weight depending on the frequency of the input signal, and are evidenced at the ADC output as the introduction of spurs and noise [13]. Disregarding the error sources, the proposed approach [14] models the ADC behavior into a chain of functional blocks, each of which accounts for a specific error. In particular, the ADC errors are considered by three equivalent error blocks: (i) amplitude compression block, (ii) jitter and (iii) distortion (Fig. 1).
2.3. A D C mixed electrical/behavioral models
3.1. Amplitude compression block
ADC mixed models are those in which the complexity of the modeling of the whole of the
Amplitude compression is usually present at ADC output, arising from saturation phenomena
2.2. A D C behavioral models
A. BaccigalupL M. D'Apuzzo
II
jitter
(] 1,d/dO I Vo
'l
ampfitude-compression(tanh)
141
~ distortion (cosh)
11v,
bV
Fig. 1. Block diagram of the serial A D C error model.
typical of analog circuitry of the converter itself. It is evidenced, in the frequency domain, as the introduction of odd spurs. ADC behavioral models can use proper amplitude compression blocks in order to consider the whole of odd spurs, disregarding the source which actually produced the distortion itself. In particular, the expression used to describe the amplitude compression is: vl = a* tan
h(vo/b)
( 1)
where parameters a and b must be tuned in order to fit all of the odd spurs at the output of the converter under test.
distortion attached to even spurs is instead considered by the distortion block. The corresponding mathematical formulation is expressed in terms of the transfer function: v3 = v2 + v~
(4)
where v; ---f*[ 1 - c o s
h(v2/e)]
(5)
in which parameters e and f are obtained to fit the appropriate even harmonic level, and fall-off rate of even spurs.
3.2. Jitter block
4. A parallel A D C error model
The effect of sampling jitter at the ADC output results in a reduction of the signal-to-noise ratio, evidenced in the frequency domain as a noise floor growth. Therefore, ADC behavioral models can use proper jitter blocks in order to fit the signalto-noise ratio at the output of the ADC under test. The expression used to simulate the jitter effect was derived from that employed by Gray et al. in Ref. [15] to describe the sample and hold jitter:
The main drawback of the model presented in Section 3 comes from the objective difficulty to conform model parameters to actual ADC behavior. This difficulty is due to the chain structure of the model itself: the in-series structure implies that any parameter change requires the rearrangement of all the other parameters in the model. Thus, the parameters cannot be evaluated separately from each other, but they must be fixed all at once. In this section a different model structure is described, with the aim of obtaining parameters as independent as possible from each other. The solution is an error model with a parallel structure, which allows a more robust parameter identification technique and, at the same time, a better fitting of the model output to the experimental data in terms of frequency spectrum. The parallel ADC error model (Fig. 2) includes: (i) a delay block, (ii) an amplitude compression block, (iii) a distortion block, and (iv) a gain block. With regard to the amplitude compression and the distortion blocks, they work like those already examined in the previous section, but now
1~2 = V1 -[- V~
(2)
where
v~ = (c- d*lvl I)*6vl/6t
(3)
and parameters c and d should be evaluated in order to best fit the noise floor present at the output of the ADC under test.
3.3. Distortion block The aforementioned amplitude compression block accounts for any odd spur. The harmonic
142
A. Baccigalupi, M. D 'Apuzzo
ampfitudecompression (tanh)
V2
distortion (cosh)
v3
v4
ia at
~
/16 ID
]quantizer
Fig. 2. Block diagram of the parallel ADC error model.
they are in parallel so there is no mutual influence in fixing parameters a, b, c and d. In addition, the jitter block, used to adjust the noise floor, is no longer present because the noise floor is fixed by varying the resolution of the ideal quantizer block (quantization noise). Furthermore, the gain factor k is used to scale the magnitude of the fundamental compared with the total harmonic distortion. Finally, the delay block z introduces the input/output time shift which can be of great interest in on-lineapplications. As previously mentioned, one of the prime advantages of the parallel over the chain structure lies in the possibility to simplify model parameter identification. In fact, the parallel structure allows one to identify the model parameters individually, according to some physical considerations. In Ref. [16] the authors describe a closed form algorithm to evaluate the model parameters as a function of a set of experiments to be carried out on the actual ADC under test.
5. A neural ADC error model
Both the models proposed in Sections 3 and 4 have the disadvantage that the model parameters are functions of the input signal bandwidth, so they can be properly applied only if the input signal is known to be band limited inside the bandwidth in which the model parameters may be considered to be constant. To overcome this drawback, one of the most interesting proposals for ADC dynamic compensation is referred to as phase plane compensation, proposed by Irons in Ref. [17]. The ADC dynamic
behavior is considered by mapping its conversion errors on the phase plane (i.e., conversion errors are mapped for any level and slope of the input signal). The phase plane implementation stores conversion errors in two-dimensional error tables in which the row index is the signal level (represented by the corresponding ADC output code) and any columnindex is the signal slope (evaluated as the difference between actual and previous ADC output codes scaled by the sampling period). The idea is very interesting, but the implementation becomes impracticable as the ADC resolution (and hence the number of ADC codes) increases. In this case, Irons proposes the abatement of the error table dimension by assuming the signal dynamic in squared areas, endorsed by a number of adjacent rows and columns, to be constant. A different method, which employs artificial neural networks (ANN) to reduce the matrix dimension of the phase plane approach, has been proposed by the authors in Ref. [18]. The basic idea is based on the generalization capabilities of the ANN which is able to forecast the converter behavior all over the phase plane, from the knowledge of a reduced set of the error table (to be used as learning set). As is well known, working ANNs require a preliminary learning phase in which the learning set must be provided to the ANN in terms of input/output values. In the case of interest, the preliminary learning phase works on the principle shown in Fig. 3. At any instant of time, a test signal v(t) is acquired both by the ADC under test and by an ideal quantizer, thus providing y and y~ codes respectively. Furthermore, the value y acquired at the previous time step t_ 1 is stored as x. The error e(x,y) is computed as Y-Yl and is
A. Baccigalupi,M. D'Apuzzo
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143
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l y-yi I Y
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[x(r°windex) I
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'
y (col. index) Fig. 3. Construction of the reduced size error table. stored in the table T at location x,y. This process continues until a sufficient number of e(x,y) values fill in the table T. Once a particular reduced-size error table T has been built up, it is used for the successive ANN learning phase, whose working operation is sketched in Fig. 4, in which the input/output learning set is provided by: (1) (x) and (y) as the input learning set; (2) e(x,y) as the output learning set.
The number of elements chosen for the construction of the reduced size compensation table affects the number of tests required to build the tables themselves, as well as the ANN's compensation performance. Hence, a reduced size choice can be considered proper only if it is able to guarantee a satisfactory trade-off between the number of tests and the related ANN compensation performance.
6. Modeling of advanced transient digitizers Hence, the learning phase tries to find out the ANN weight and bias values which minimize the difference: e(x, y)= e(x, y)-e*(x, y). Once the learning phase is completed, the ANN is ready to perform its compensation task in the so-called production phase. In this phase, the output of the actual ADC feeds the ANN, according to what was learnt in the previous phase, and produces the correction e*(x,y) to apply to the ADC samples, as depicted in Fig. 5.
Technological progress in the field of analog-todigital converters is continuously evolving at a very high speed. Thus, modeling of new digitizers requires continuous adjustments in order to consider the characteristics peculiar to the new technology as well. Scan converter-based digitizers, for example, are characterized by peculiar dynamic error sources arising from the working of such devices [19,20]. Reading and digitizing operations
"
.......
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.
l
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are carried out at a slow speed, so that the corresponding errors turn out to be negligible [21,22]. On the other hand, singular error sources arise from the writing mechanism and from the target semiconductor diodes that remarkably influence the dynamic behavior of the digitizer [23]. The main error sources in the writing mechanism can deform the beam and thus can give rise to trace distortions as a blooming effect near sine wave crests, or insufficient intensity in fast rising edges. Differences in dynamic behavior of the semiconductor diodes usually arise, in spite of their correction through the reference array, depending on the technology and on the practical realization. As a consequence of the aforementioned error sources, in the writing phase, the error magnitude depends (i) on the way the electron beam forces each diode of the target and (ii) on which particular diode is forced. Hence, the errors can vary significantly according to the written area and, correspondingly, to the instantaneous value of the input signal. Owing to such peculiar behavior, the use of the aforementioned models seems not to be well suited to increase scan converter performance by means of error compensation techniques. Thus, a technique for evaluating the distortion of the charge distribution, aimed at improving the signal extraction in scan converters, is proposed in Ref. [24]. Such a technique consists of (i) the analysis of actual charge distributions on the columns through the evaluation of statistical parameters based on the first four moments around the mean, (ii) the characterization of the distortion across the target through the parameter trend assessment, and (iii) the improvement of the signal extraction through the model identification of the distribution [25]. Since the statistical parameters are normalized to
the distribution spread, a suitable model, that relates the spread to the input signal rate, is integrated in the proposed technique to describe adequately dynamic distortion effects. In addition, in order to model the dependence of the scan converter behavior from the beam position, a proper behavioral model has been proposed (see Fig. 6): the scan converter can be seen as a number of different conversion subsystems (S/H and A D C ) each of which operates in an instant of time properly delayed for the sampling period.
7. Concluding remarks ADC modeling is still of great interest in many fields of application, so that much work has been spent in designing different models for different goals. The huge amount of papers actually present in the literature, and the many facets of each of them, did not allow for a complete survey of all the proposed models. Therefore, only a survey of the ADC model techniques set up by the authors has been presented. By inspecting the available references, we can see that the world of ADC modeling is evolving to reach the continuous technological progress which is running at a very high speed. Every new ADC presented on the market shows new performance and new characteristics, requiring new models to be designed in order to evidence the new ADC behavior. The present research is now focused on refining the scan converter model; the basic approach is described in Section 6. The current main difficulty in research arises from the lack, on the market, of proper testing equipment capable of acting as a
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V(t)
%(nAt) Fig. 6. Scan converter behavioral model.
reference for the experimental validation of the proposed theories all over the working range of the scan converter ( 10 Vpp, 200 GHz).
References 1. R.J. Polge, B.K. Bhagavan and L. Callas, Evaluating analog-to-digital converters, Simulations, March 1975, pp. 81-86. 2. Y.C. Jenq, Measuring harmonic distortion and noise floor of an A/D converter using spectral averaging, IEEE Trans. Instrum. Measurement 37 (December 1988). 3. A. Petraglia and S.K. Mitra, Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer, IEEE Trans. Instrum. Measurement 40(5) (October 1991) 831-835. 4. E.G. Soenen, P.M. Vanpeteghem, H. Liu, S. Narayan and J.T. Cummings, A framework for design and testing of analog integrated circuits, IEEE Trans. Instrum. Measurement 39(6) (December 1990) 890-893. 5. K. Hejn and I. Kale, Some theorems on Walsh transforms of quantizer differential and integral non-linearity, Proc. IMTC-90, Atlanta, USA, pp. 55-61. 6. G. Ruan, A behavioral model of A/D converters using a mixed mode simulator, IEEE J. Solid State Circuits 26(3) (March 1991) 283-290. 7. T.R. McComb, J. Kuffel and R. Malewsky, Measuring characteristics of the fastest commercially available digitizers, IEEE Trans. Power Delivery 2(3) (July 1987) 661-670. 8. F.H. Irons, D.M. Hummels and S.P. Kennedy, Improved Compensation for analog-to-digital converters, 1EEE Trans. Circuits Systems 38(8) (August 1991) 958-961. 9. A. Baccigalupi, F. Cennamo and M. D'Apuzzo, Digital recording of high speed voltage transients, Proceedings o f 3rd IMEKO TC4 International Symposium on Measurement and Electronic Power Systems, Zurich, September 1989. 10. M.V. Borsche, J. Shonkens and J. Renneboog, Dynamic
testing and diagnostic of A/D converters, IEEE Trans. C.A.S. 33(8) (August 1986) 775-778. 11. D.W. Doerfler, Dynamic testing of a slow sample rate, high resolution data acquisition system, IEEE Trans. Instrum. Measurement 35(4) (December 1986) 477~82. 12. J. Kuffel, R. Malewsky and R.G. Van Heeswijk, Modeling of the dynamic performance of transient recorders used for high voltage impulse tests, IEEE Trans. Power Delivery 6(2) (April 1991) 507-515. 13. D. Asta and F.H. Irons, Dynamic error compensation of analog to digital converters, Lincoln Lab. J. 2 (1989) 161-182. 14. A. Baccigalupi, P. Daponte and M. D'Apuzzo, An ADC error model for testing digitizing signal analyzers, Proceedings o f 5th International Symposium on Electrical Measuring Instruments for Low and Medium frequencies, Vienna, 1992, pp. 167-174. 15. J.R. Gray and S.C. Kistopoulos, A precision sample and hold circuit with subnanosecond switching, IEEE Trans. Circuit Theory (September 1964) 389-396. 16. A. Baccigalupi, P. Daponte and M. D'Apuzzo, An improved error model of data acquisition systems, IEEE Trans. Instrum. Measurement 43(2) (April 1994) 220-225. 17. T.A. Rebold and F.H. Irons, A phase plane approach to the compensation of high speed analog-to-digital converters, Proceedings o f IEEE International Symposium on Circuits and Systems, 1987, pp. 455458. 18. A. Baccigalupi, A. Bernieri and C. Liguori, Error compensation of A/D converters using neural networks, IEEE Trans. Instrum. Measurement 45(2) (April 1996). 19. P. Arpaia, A. Baccigalupi, F. Cennamo and M. D'Apuzzo, Testing uncertainty of scan converter based transient digitizers, Proceedings o f 7th IMEKO TC4 International Symposium, Prague, September, 1995. 20. P. Arpaia, A. Baccigalupi and F. Cennamo, Measurement on A/N and N/A conversion systems (in Italian), CNR GMEE Symposium, Bologna, 18-20 September 1995. 21. J. Kuffel, R. Malewsky and R.G. van Heeswijk, Modeling of the dynamic performance of transient recorders used for high voltage impulse tests, IEEE Trans. Power Delivery 6 (April 1991) 507-515.
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22. P. Arpaia, F. Cennamo, P. Daponte and M. D'Apuzzo, Dynamic characterization of scan conversion based transient digitizers, IEEE Trans. Instrum. Measurement /June 1995). 23. P. Arpaia, F. Cennamo, P. Daponte and M. D'Apuzzo, A behavioral model for scan converter based transient digitizers, Measurement 17(2) 103 114.
24. P. Arpaia, A. Baccigalupi and F. Cennamo, Techniques of improved signal extraction in scan conversion-based transient digitizers, Proceedings ~?["IEEE Instrumentation and Measurement Technology ConJerence, Brussels, Belgium, 4-6 June 1996. 25. A. Haber and R.P. Runyon, General Statistics Reading, Addison Wesley, Massachusetts, 1969.